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    High Fanout Net Synthesis (HFNS) - LMR

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    PRAKASH WAHURWAGH
    High Fanout Net Synthesis (HFNS) is the process of buffering high fanout nets, which are nets that drive many loads, in order to balance the load on the net and improve timing. HFNS is typically performed during placement after high fanout nets have been identified. Buffering high fanout nets helps balance the load which directly impacts delay, improving overall timing closure. Care must be taken to set appropriate fanout limits and not inhibit buffering during HFNS.

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    High Fanout Net Synthesis (HFNS) - LMR

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    PRAKASH WAHURWAGH
    30 views3 pages
    High Fanout Net Synthesis (HFNS) is the process of buffering high fanout nets, which are nets that drive many loads, in order to balance the load on the net and improve timing. HFNS is typically performed during placement after high fanout nets have been identified. Buffering high fanout nets helps balance the load which directly impacts delay, improving overall timing closure. Care must be taken to set appropriate fanout limits and not inhibit buffering during HFNS.

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    High Fanout Net Synthesis (HFNS) – LMR

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    High Fanout Net Synthesis (HFNS) is the process of buffering high fanout nets, which are nets that drive many loads, in order to balance the load on the net and improve timing. HFNS is typically performed during placement after high fanout nets have been identified. Buffering high fanout nets helps balance the load which directly impacts delay, improving overall timing closure. Care must be taken to set appropriate fanout limits and not inhibit buffering during HFNS.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as pdf or txt
    30 views3 pages

    High Fanout Net Synthesis (HFNS) - LMR

    Uploaded by

    PRAKASH WAHURWAGH
    High Fanout Net Synthesis (HFNS) is the process of buffering high fanout nets, which are nets that drive many loads, in order to balance the load on the net and improve timing. HFNS is typically performed during placement after high fanout nets have been identified. Buffering high fanout nets helps balance the load which directly impacts delay, improving overall timing closure. Care must be taken to set appropriate fanout limits and not inhibit buffering during HFNS.

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    11/13/21, 12:35 PM High Fanout Net Synthesis (HFNS) – LMR

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    High Fanout Net


    Synthesis (HFNS)
    by
    Jarmo
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    May 8, 2021
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    Technologies
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    https://lmr.fi/int/high-fanout-net-synthesis-hfns/ 1/6
    11/13/21, 12:35 PM High Fanout Net Synthesis (HFNS) – LMR

    Before going to discuss about we have to know the basic terminology like What is
    Fanout? What are High Fanout Nets (HFN)? Why we are going for High Fanout
    Net Synthesis (HFNS)?

    What is fanout?
    Fanout is the number of gate inputs to which the output can be safely connected.
    i.e., The load that a gate output can drive. The maximum fanout of an output
    measures it’s load-driving capability. Fanout belongs to the output.

    Liittyvät Viestit

    Floorplanning

    Static Timing Analysis (STA) Overview

    Physical Design Flow


    What are High Fanout Nets(HFN) ?


    High Fanout Nets are the nets which drive more number of load. We set some
    max fanout limit by using the command set_max_fanout. The nets which have
    greater than these limit are considered as High Fanout Nets (HFN). Generally
    clock nets, reset, scan, enable nets are High Fanout Nets.

    What is High Fanout Net Synthesis


    (HFNS)?
    High Fanout Net Synthesis (HFNS) is the process of buffering the High Fanout
    Nets to balance the load.

    https://lmr.fi/int/high-fanout-net-synthesis-hfns/ 2/6
    11/13/21, 12:35 PM High Fanout Net Synthesis (HFNS) – LMR

    Why HFNS?
    To balance the load HFNS is perfomed. Too many load affects delay numbers and
    transition times. Because load is directly proportional to the delay. By buffering
    the HFN the load can be balanced. This is called as High Fanout Net
    Synthesis(HFNS).

    Where HFNS ?
    Generally at placement step HFNS performed. HFNS can also be performed at
    synthesis step using Design Compiler. But it’s not good idea, Buffers will be
    removed during PD and again HFNS is performed. It’s very time consuming
    process. So HFNS at synthesis step is not recommended. HFNS at synthesis step
    gives an idea whether HFN are present in data path or not. Generally HFN are
    present in clock paths, rest, enable and scan paths.

    Care that should taken during HFNS:


    1. Make sure an appropriate fanout limit is set using set_max_fanout
    command

    2. Verify the SDC used for PD should not have set_ideal_network or


    set_dont_touch commands on High Fanout Nets.

    3. Use ideal clock network – As clock nets are synthesized separately during
    Clock Tree Synthesis (CTS) step, we set clock network as ideal network.

    NOTE:
    As clock nets are considered as ideal, buffering is not performed on the clock nets
    even they are High Fanout Nets. So, HFNS is the process of synthesizing other than
    clock nets, such as reset, scan, test enable nets is called as High Fanout Net Synthesis
    (HFNS) 

    https://lmr.fi/int/high-fanout-net-synthesis-hfns/ 3/6

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