ST.

JOSEPH COLLEGE OF ENGINEERING

SRIPERUMBUDUR
DEPARTMENT OF ELECTRONICS AND COMMUNICATION
ENGINEERING

LAB OBSERVATION
(REGULATION 2013)

SUBJECT CODE : EC6311

SUBJECT NAME : ANALOG AND DIGITAL CIRCUITS

LABORATORY

YEAR : II YEAR ECE (JUNE-NOVEMBER 2015)

SEMESTER : III SEMESTER

BRANCH OF STUDENTS: ECE

PREPARED BY
Mr.S.SANTHOSH AP/ECE/SJCE

2015-2016
 INDEX
DATE SIGN
S.NO. TITLE PAGE
NO.
(a)HWR & FWR
(b)Frequency Response of CE amplifier
1. (c) Frequency Response of CB amplifier

Frequency response of CS Amplifiers

2.
Darlington Amplifier
3.
Differential Amplifiers- Transfer characteristic
4.
CMRR Measurement
5.

6. Cascode / Cascade amplifier

Determination of bandwidth of single stage and
multistage amplifiers
7.
Spice Simulation of Common Emitter and Common
Source amplifiers
8.
Design and implementation of code converters using
logic gates
i)BCD to excess-3 code and vice versa
9. ii)Binary to gray and vice-versa

10. Design and implementation of 4 bit binary Adder/

Subtractor and BCD adder using IC 7483
Design and implementation of Multiplexer and De-
11. multiplexer using logic gates
12. Design and implementation of encoder and decoder
using logic gates
13. Construction and verification of 4 bit ripple counter
and Mod-10 / Mod-12
14. Design and implementation of 3-bit synchronous
up/down counter
Implementation of SISO, SIPO, PISO and PIPO shift
registers using Flip- flops
15.
EXP NO: HALF WAVE RECTIFIER
DATE:
AIM:
To construct half wave rectifier with and without filter and to draw their input and output
waveforms.
APPARATUS REQUIRED:

S.No. Name Range Quantity

1. Transformer 230 V / 6-0-(-6) 1

2. Diode IN4007 1

3. Resistor 1 kΩ 1

4. Capacitor 100µF 1

5. CRO 30 MHz 1

6. Bread Board 1

CIRCUIT DIAGRAM:

WITHOUT FILTER:
WITH FILTER:

FORMULA USED:

Ripple Factor =

Where Im is the peak current

THEORY:

Half wave rectifier:

A rectifier is a circuit, which uses one or more diodes to convert A.C voltage into D.C
voltage. In this rectifier during the positive half cycle of the A.C input voltage, the diode is forward
biased and conducts for all voltages greater than the offset voltage of the semiconductor material
used. The voltage produced across the load resistor has same shape as that of the positive input half
cycle of A.C input voltage.

During the negative half cycle, the diode is reverse biased and it does not conduct. So there is no
current flow or voltage drop across load resistor. The net result is that only the positive half cycle
of the input voltage appears at the output.
PROCEDURE:

1. Connect the circuit as per the circuit diagram.

2. Apply a.c input using transformer.
3. Measure the amplitude and time period for the input and output waveforms.
4. Calculate ripple factor.
MODEL GRAPH:

FIG.13.5

HALF WAVE RECTIFIER:

Without filter With filter

Input signal Output signal

Amplitude(V) Time period Amplitude(V) Time period

RESULT:

Thus the half wave rectifier was constructed and its input and output waveforms are
drawn. The ripple factor of capacitive filter is calculated as Ripple factor=
EXP NO: FULL WAVE RECTIFIER
DATE:
AIM:
To construct a full wave rectifier and to measure dc voltage under load and to calculate the
ripple factor.

APPARATUS REQUIRED:

S.No. Name Range Quantity

1. Transformer 230 V / 6-0-(-6) 1
2. Diode IN4007 2
3. Resistor 1 kΩ 1
4. Capacitor 100µF 1
5. CRO 30 MHz 1
6. Bread Board 1

FULLWAVE RECTIFIER WITHOUT FILTER

FULLWAVE RECTIFIER WITH FILTER

FORMULA:

Ripple Factor = √ [(Im/√2) / (2*Im /л)] 2-1

Where Im is the peak current

THEORY:

The full wave rectifier conducts for both the positive and negative half cycles of the input
ac supply. In order to rectify both the half cycles of the ac input, two diodes are used in this circuit.
The diodes feed a common load RL with the help of a centre tapped transformer. The ac voltage is
applied through a suitable power transformer with proper turn’s ratio. The rectifier’s dc output is
obtained across the load.

The dc load current for the full wave rectifier is twice that of the half wave rectifier. The
lowest ripple factor is twice that of the full wave rectifier. The efficiency of full wave rectification
is twice that of half wave rectification. The ripple factor also for the full wave rectifier is less
compared to the half wave rectifier.
PROCEDURE:

1. Connections are given as per the circuit diagram wiyhout filter.

2. Note the amplitude and time period of the input signal at the secondary winding of the
transformer and rectified output.
3. Repeat the same steps with the filter and measure Vdc.
4. Calculate the ripple factor.
5. Draw the graph for voltage versus time.
MODEL GRAPH

RESULT:

Thus, the full wave rectifier was constructed and the ripple factor was calculated as
Ripple factor =
EXP NO: COMMON EMITTER AMPLIFIER
Date :
Aim: To find the voltage gain of a common emitter amplifier and to find its frequency response

Apparatus:

S.No. Name Range Quantity

1. Transistor BC107 1
2. Resistor

3. Capacitor
4. Regulated power supply (0-30)V 1
5. Function Generator (0-3) MHz 1
6. CRO 30 MHz 1
7. Bread Board 1

Circuit Diagram:
DESIGN PROCEDURE:
Given specifications:
VCC= 10V, IC=1.2mA, AV= 30, hFE= 100
(i) To calculate RC:
The voltage gain is
given by, AV= -
hfe (RC|| RF) / hie
h ie = β re

re = 26mV / IE = 26mV / 1.2mA

= 21.6Ω hie = 150 x 21.6
=3.2KΏ
Apply KVL to output loop,
VCC= IC RC + VCE+ IE RE ----- (1)
Where VE = IE RE (IC= IE)
VE= VCC / 10= 1V
Therefore RE= 1/1.2x10-3=0.8K= 1KΏ
VCE= VCC/2= 5V
From equation (1), RC= ( Vcc - VCE - IE RE / IC ) = ________
(ii) To calculate R1&R2:
S=1+ (RB/RE)
Where RE = 1 KΏ and S = 9
RB= (S-1) RE= (R1 || R2) =1KΏ
RB=( R 1R2 ) /( R1+ R2) ------- (2)
VB= VBE + VE = 0.7+ 1= 1.7V
VB= VCC (R2 / R1+ R2 )------- (3)
Solving equation (2) & (3),
R1= ____ & R2= ______

(iii) Input coupling capacitor :

Xci= Rif / 10= 2.4 Ω (since XCi << Rif)
Ci = 1/ 2пfXCi = _____
(iv) Output coupling capacitor:
XCO= Rof /10= 5.2 Ω CO = 1/ 2пfXCO = _____
Theory:
The CE amplifier is a small signal amplifier. This small signal amplifier accepts low
voltage ac inputs and produces amplified outputs. A single stage BJT circuit may be employed as a
small signal amplifier; has two cascaded stages give much more amplification. Designing for a
particular voltage gain requires the use of a ac negative feedback to stabilize the gain. For good
bias stability, the emitter resistor voltage drop should be much larger than the base -emitter
voltage. And Re resistor will provide the required negative feedback to the circuit. CE is provided
to provide necessary gain to the circuit. All bypass capacitors should be selected to
have the smallest possible capacitance value, both to minimize the physical size of the circuit for
economy. The coupling capacitors should have a negligible effect on the frequency response of the
circuit.

Procedure:
1. Connect the circuit as per the circuit diagram
2. Determine the Q-point of the CE amplifier using DC analysis.
3. Determine Maximum input voltage that can be applied to CE amplifier using AC analysis.
4. Set the input voltage Vin=V MSH /2 and vary the input signal frequency from 0Hz to
1MHz in incremental steps and note down the corresponding output voltage Vo for at
least 20 different values for the considered range.
5. The voltage gain is calculated as Av = 20log (V0/Vi) dB
6. Find the Bandwidth and Gain-Bandwidth Product from Semi-log graph taking frequency on
x-axis and gain in dB on y-axis., Bandwidth, BW = f2-f1 where f1 lower cut-off frequencyf2
upper cut-off frequency

Model Graph:
TABULATION:

Input voltage (Vi)=

OUTPUT GAIN Av=Vo/Vi GAIN IN dB

FREQUENCY VOLTAGE(Vo) GAIN IN dB 20 log gain

Result:
Thus, the voltage gain and frequency response of a CE amplifier was measured.
EXP NO: COMMON COLLECTOR AMPLIFIER
DATE:

Aim:
To construct a common collector amplifier circuit and to plot the frequency response
characteristics.

Apparatus Required:

S.No. Name Range Quantity

1. Transistor BC 107 1
2. Resistor
3. Capacitor
4. Function Generator (0-3)MHz 1
5. CRO 30MHz 1
6. Regulated power (0-30)V 1
supply
7. Bread Board 1

Theory:

The D.C biasing in common collector is provided by R1, R2 and RE .The load resistance is
capacitor coupled to the emitter terminal of the transistor.

When a signal is applied to the base of the transistor ,VB is increased and decreased as the
signal goes positive and negative, respectively. Considering VBE is constant the variation in the
VB appears at the emitter and emitter voltage VE will vary same as base voltage VB . Since the
emitter is output terminal, it can be noted that the output voltage from a common collector circuit is
the same as its input voltage. Hence the common collector circuit is also known as an emitter
follower.
CIRCUIT DIAGRAM:
Design of Common collector amplifier:
Given specifications:
VCC= 15V, IC=1.2mA, hie = 2.1kΩ hFE= 75 hib= 27.6Ω
(i) To calculate Zb ( Device input impedance )
Zb = hie + hfe ( RE || RL)
Assume RE = 4.7 KΩ and RL= 3.3 KΩ
Zb = 2.1k + 75 (4.7 K || 3.3 K) = __________
(ii) To calculate Zi ( Input Impedance )
Zi = R1 || R2 || Zb
Assume R1= R2= 10k Ω
Zi = _______
(iii)To calculate voltage gaiv Av
Av = [ ( RE || RL ) / ( hib + ( RE || RL) ) ]

Model Graph:

f2 f1 f (Hz)
TABULATION:
Keep the input voltage constant, Vin =

Frequency (in Hz) Output Voltage (in volts) Gain= 20 log(Vo/Vin) (in dB)
 Procedure:
1. Connect the circuit as per the circuit diagram.
2. Set Vi =50 mV, using the signal generator.
3. Keeping the input voltage constant, vary the frequency from 0 Hz to 1M Hz in regular steps
and note down the corresponding output voltage.
4. Plot the graph; Gain (dB) Vs Frequency (Hz).

Result:

Thus, the Common collector amplifier was constructed and the frequency response curve is
plotted.
 VIVA QUESTIONS

1. What do you understand by Operating point?

2. Why do we choose the Q point at the center of the load line?

3. Name the two techniques used in the stability of the q point .explain.?

4. Define stability factor &Give the expression for stability factor?

5. List out the different types of biasing.

6. What do you meant by thermal runway?

7. Why transistor is called as a current controlled device?

8. Define current amplification factor?

9. What are the requirements for biasing circuits?

10. When does a transistor act as a switch?

11. What is biasing?

12. Why at mid range frequency it maintains constant?

13. What are the application of CE config?

14. For a common-emitter amplifier, the purpose of swamping is to?

15. What is d.c load line?

EXP NO: COMMON SOURCE AMPLIFIER
DATE:

Aim:
To find the voltage gain of a CS amplifier and to find its frequency response

Apparatus:

S.No. Name Range Quantity

1. FET BFW10 2
2. Resistor 100MΩ, 1kΩ,2.75KΩ 1,1,2
3. Capacitor 1.59nf, 0.578µf 2,1
4. Regulated power supply (0-30)V 1
5. Function Generator (0-3) MHz 2
6. CRO 30 MHz 1
7. Bread Board 1

Circuit Diagram:

Theory:
The CS amplifier is a small signal amplifier. For good bias stability, the source resistor
voltage drop should be as large as possible. Where the supply voltage is small, Vs may be reduced
to a minimum to allow for the minimum level of Vds.R2 is usually selected as 1MΏ or less as for
BJT capacitor coupled circuit, coupling and bypass capacitors should be selected to have the
smallest possible capacitance values. The largest capacitor in the circuit sets the circuit
low 3dB frequency (capacitor C2). Generally to have high input impedance FET is used. As in BJT
circuit RL is usually much larger than Zo and Zi is often much larger than Rs.
DESIGN ANALYSIS :
Given :
VDD = 20 V, IDSS = 5mA, ID = 1.5 mA,
i) To Find the voltage across the Gate-source region (VGS)
VGS = ID RS
Assume RS = 3.3KΩ,
VGS = 1.5mA x 3.3KΩ = _____
ii) To find Voltage Across Drain to Source (VDS)
VDS= VDD - ID ( RD + Rs) ; Where RD= 3.3 KΩ
= 20V – 1mA ( 3.3 KΩ + 3.3 KΩ)
= ________
iii) To Find input impedance :
Zi = RG ; Assume RG = 1MΩ

TABULATION:
Input voltage =

Output Gain In Db
Gain
S.No Frequency Voltage(Vo) Av=Vo/Vi 20 Log Gain
Model Graph:

Result:

Thus, the voltage gain and frequency response of a CS amplifier was measured.
VIVA QUESTIONS

1. What do you understand by Operating point?

2. Why do we choose the Q point at the center of the load line?

3. Name the two techniques used in the stability of the q point .explain.?

4. Define stability factor &Give the expression for stability factor?

5. List out the different types of biasing.

6. What do you meant by thermal runway?

7. Why transistor is called as a current controlled device?

8. Define current amplification factor?

9. What are the requirements for biasing circuits?

10. When does a transistor act as a switch?

11. What is biasing?

12. Why at mid range frequency it maintains constant?

13. What are the application of CE config?

14. For a common-emitter amplifier, the purpose of swamping is to?

15. What is d.c load line?

EXP NO: DARLINGTON AMPLIFIER USING BJT

DATE:
AIM:

To construct a Darlington current amplifier circuit and to plot the frequency response
characteristics.

APPARATUS REQUIRED:

S.No. Name Range Quantity

1. Transistor BC 107 1
2. Resistor 15kΩ,10kΩ,680Ω,6kΩ 1,1,1,1
3. Capacitor 0.1µF, 47µF 2, 1
4. Function Generator (0-3)MHz 1
5. CRO 30MHz 1
6. Regulated power supply (0-30)V 1
7. Bread Board 1
CIRCUIT DIAGRAM
 THEORY:
In Darlington connection of transistors, emitter of the first transistor is directly
connected to the base of the second transistor .Because of direct coupling dc output current of the
first stage is (1+hfe )Ib1.If Darlington connection for n transitor is considered, then due to direct
coupling the dc output current foe last stage is (1+hfe ) n times Ib1 .Due to very large amplification
factor even two stage Darlington connection has large output current and output stage may have to
be a power stage. As the power amplifiers are not used in the amplifier circuits it is not possible to
use more than two transistors in the Darlington connection.

In Darlington transistor connection, the leakage current of the first transistor is amplified
by the second transistor and overall leakage current may be high, Which is not desired.

DESIGN PROCEDURE:
Given specifications:
VCC= 12V, IC=1.2mA, AV= 30, f1 = 300 HZ, f2 = 500KHZ, hFE= 150
(i) To calculate RC:
Assume R2 = 10KΩ and Ic = 1mA.
Since voltage amplification is done in the Darlington transistor amplifier circuit, we assume equal
drops across VCE and load resistance RC. The ICQ = 1mA is assumed.
Drop across Re is assumed to be 1V.
The drop across VCE with a supply of 1.2 V is given by
12 – 1 = 1V.
It is equal to VRC & VCE = 5.5V x RC
Therefore, Rc = 5.5 KΩ (4.7 KΩ) ; IC = 1mA
(ii) To calculate R1&R2:
S=1+ (RB/RE)
RB= (S-1) RE= (R1 || R2) =1KΏ
RB=( R 1R2 ) /( R1+ R2) ------- (2)
VB= VBE + VE = 0.7+ 1= 1.7V
VB= VCC (R2 / R1+ R2 )------- (3)
Solving equation (2) & (3),
Since R2=10kΩ , the other resistor is found to be, R1= 47kΩ
(iii) To Find Cin :
Cin = * 1 / 2πf1 (Zi / 10) ]
Where Zi = ( RB || hie ) = 1.1KΩ and
f1 = Lower cut-off frequency= 25HZ
= 57.9μF
(iv) To Find CO :
C0 = * 1 / 2πf2 ( (RC + RL) / 10) ]
Where RC = 9KΩ; RL = 90KΩ and
f2 = Upper cut-off frequency= 500KHZ
= 64 μF
 MODEL GRAPH

f1 FIG..2 f2 f (Hz)

TABULATION

Keep the input voltage constant, Vin =

Frequency (in Hz) Output Voltage (in volts) Gain= 20 log(Vo/Vin) (in dB)
PROCEDURE:

1. Connect the circuit as per the circuit diagram.

2. Set Vi =50 mv, using the signal generator.

3. Keeping the input voltage constant, vary the frequency from 0 Hz to 1M Hz in regular steps and
note down the corresponding output voltage.

4. Plot the graph; Gain (dB) vs Frequency(Hz).

5. Calculate the bandwidth from the graph.

RESULT:

Thus, the Darlington current amplifier was constructed and the frequency response curve is
plotted. . The Gain Bandwidth Product is found to be =
 VIVA QUESTIONS

1. What is Darlington pair?

2. The current gain for the Darlington connection is ________.

3. Which of the following configurations has the lowest output impedance? Fixed-bias,

Voltage-divider, Emitter-follower

4. What is swapping resistor?

5. What is cross over distortion?

6. What is figure of merit?

7. What is source follower?

8. List the application of source follower?

9. Compare the features of the three transistor configurations.

10. Explain about the characteristics of a transistor?

EXP NO: DIFFERENTIAL AMPLIFIER USING BJT

DATE:

AIM: To construct a differential amplifier using BJT and to determine the dc collector current of
individual transistors and also to calculate the CMRR.

APPARATUS REQUIRED:

S.No. Name Range Quantity

1. Transistor BC107 2
2. Resistor 4.7kΩ, 10kΩ 2,1
3. Regulated power supply (0-30)V 1
4. Function Generator (0-3) MHz 2
5. CRO 30 MHz 1
6. Bread Board 1
CIRCUIT DIAGRAM
 OBSERVATION

VIN =VO =AC = VO / VIN

FORMULA:

Common mode Gain (Ac) = VO / VIN

Differential mode Gain (Ad) = V0 / VIN

Where VIN = V1 – V2

Common Mode Rejection Ratio (CMRR) = Ad/Ac

Where, Ad is the differential mode gain

Ac is the common mode gain.

THEORY:

The differential amplifier is a basic stage of an integrated operational amplifier. It is used to

amplify the difference between 2 signals. It has excellent stability, high versatility and immunity to
noise. In a practical differential amplifier, the output depends not only upon the difference of the 2
signals but also depends upon the common mode signal.

Transistor Q1 and Q2 have matched characteristics. The values of RC1 and RC2 are equal.
Re1 and Re2 are also equal and this differential amplifier is called emitter coupled differential
amplifier. The output is taken between the two output terminals.
 OBSERVATION

VIN = V1 – V2

V0 =

Ad = V0/ VIN

For the differential mode operation the input is taken from two different sources and the common
mode operation the applied signals are taken from the same source

Common Mode Rejection Ratio (CMRR) is an important parameter of the differential

amplifier. CMRR is defined as the ratio of the differential mode gain, Ad to the common mode
gain, Ac.
 CMRR = Ad / Ac

In ideal cases, the value of CMRR is very high.

PROCEDURE:

1. Connections are given as per the circuit diagram.

2. To determine the common mode gain, we set input signal with voltage Vin=2V
and determine Vo at the collector terminals. Calculate common mode gain, Ac=Vo/Vin.

3. To determine the differential mode gain, we set input signals with voltages V1 and V2.
Compute Vin=V1-V2 and find Vo at the collector terminals. Calculate differential mode
gain, Ad=Vo/Vin.
4. Calculate the CMRR=Ad/Ac.
5. Measure the dc collector current for the individual transistors.

RESULT:

Thus, the Differential amplifier was constructed and dc collector current for the individual
transistors is determined. The CMRR is calculated as
VIVA QUESTIONS

1. A differential amplifier amplifies the ________between two input signals.

2. Noise of input signal in differential amplifier

3. Why the operating point is selected at the Centre of the active region?

4. What is small signal amplifier?

5. What is meant by Differential Amplifier?

6. What do you mean by balanced and unbalanced output?

7. Give few applications of differential amplifier

8. What is the necessity of heat sink?

9. What is the typical value of the current gain of a common-base configuration?

10. List the four differential amplifier configurations

EXP NO: CASCADE / CASCODE AMPLIFIER CIRCUIT

DATE:

AIM:

To construct a cascade / cascode amplifier circuit and to plot the frequency response
characteristics.

APPARATUS REQUIRED:

S.No. Name Range Quantity

1. Transistor BC107 1

2. Resistor 10kΩ,8 kΩ,500 Ω,100Ω 1,1,1,1

3. Regulated power supply (0-30)V 1

4. Signal Generator (0-3)MHz 1

5. CRO 30 MHz 1

6. Bread Board 1

7. Capacitor 0.01µF 5

THEORY:

A cascade amplifier has many of the same benefits as a cascode. A cascade is basically a
differential amplifier with one input grounded and the side with the real input has no load. It can
also be seen as a common collector (emitter follower) followed by a common base.

By cascading a CE stage followed by an emitter-follower (CC) stage, a good voltage

amplifier results. The CE input resistance is high and CC output resistance is low. The CC
contributes no increase in voltage gain but provides a near voltage-source (low resistance) output
so that the gain is nearly independent of load resistance. The high input resistance of the CE stage
makes the input voltage nearly independent of input-source resistance. Multiple CE stages can be
cascaded and CC stages inserted between them to reduce attenuation due to inter-stage loading.
CASCADED AMPLIFIER

CASCODED AMPLIFIER
DESIGN PROCEDURE FOR CASCADED AMPLIFIER

Given specifications:
VCC= 14 V, IC1=1.2mA, RL = 40KΏ hFE= 100
(i) To calculate R5 :
Assume VE1 = 5V , VCE1 = VCE2 = 3V;
VB2 = VC1 = VE1 + VCE1 = 5V + 3V = 8V
VE2 = VB2 – VBE = 8V – 0.7V = 7.3V
VR5 = Vcc – VE2 – VCE2 = 14V – 7.3V – 3V = 3.7V
Choose R5 = RL / 10 = 40KΩ / 10 = 4KΩ ;
IC2 = ( VR5 / R5 ) = 3.7V / 3.9KΩ = 1000μA
(ii) To calculate R6 :
VR6 = VE2 / IC2 = 7.7KΩ;
IC2 = VE2 / R6 = 7.3V / 8.2 KΩ = 890μA
(iii) To calculate R1, R2 , R3 & R4:
Voltage across resistor R3 is given by
VR3 = Vcc – VC1 = 14V – 8V = 6V
R3 = VR3 / IC1 = 6V / 1mA = 6KΩ
R4 = VE1 / IC1 = 5V/ 1mA = 4.7KΩ
Voltage across resistor R2 is given by
VR2 = VE1 – VBE = 5V + 0.7V =5.7V
R2 = 10 R4 = 4.7 KΩ
VR1 = VCC – VB1 = 14V + 5.7V =8.3V
R1 = [ VR1 x R2 / VR2] = 68.4 KΩ

DESIGN PROCEDURE FOR CASCODED AMPLIFIER

Given specifications:

VCC= 14 V, IC1=1.2mA, RL = 40KΏ hFE= 100

(i) To calculate R5 :
Assume VE1 = 5V , VCE1 = VCE2 = 3V;
VB2 = VC1 = VE1 + VCE1 = 5V + 3V = 8V
VE2 = VB2 – VBE = 8V – 0.7V = 7.3V
VR5 = Vcc – VE2 – VCE2 = 14V – 7.3V – 3V = 3.7V
Choose R5 = RL / 10 = 40KΩ / 10 = 4KΩ ;
IC2 = ( VR5 / R5 ) = 3.7V / 3.9KΩ = 1000μA
(ii) To calculate R6 :
VR6 = VE2 / IC2 = 7.7KΩ;
IC2 = VE2 / R6 = 7.3V / 8.2 KΩ = 890μA
(iii) To calculate R1, R2 , R3 & R4:
Voltage across resistor R3 is given by
VR3 = Vcc – VC1 = 14V – 8V = 6V
R3 = VR3 / IC1 = 6V / 1mA = 6KΩ
R4 = VE1 / IC1 = 5V/ 1mA = 4.7KΩ
Voltage across resistor R2 is given by
VR2 = VE1 – VBE = 5V + 0.7V =5.7V
R2 = 10 R4 = 4.7 KΩ
VR1 = VCC – VB1 = 14V + 5.7V =8.3V
R1 = [ VR1 x R2 / VR2] = 68.4 KΩ

MODEL GRAPH

f1 f2 f (Hz)

PROCEDURE:

1. Connections are made as per the circuit diagram.

2. The waveforms at the input and output are observed for cascade operations by
varying the input frequency.

3. The biasing resistances needed to locate the Q-point are determined.

4. Set the input voltage as 1V and by varying the frequency, note the output voltage.

5. Calculate gain=20 log (Vo / Vin.)

6. A graph is plotted between frequency and gain.

TABULATION:

FREQUENCY RESPONSE OF CASCADE AMPLIFIER

Keep the input voltage constant (Vin) =

Frequency (in Hz) Output Voltage (in volts) Gain = 20 log (Vo / Vin) (in dB)

FREQUENCY RESPONSE OF CASCODE AMPLIFIER

Keep the input voltage constant (Vin) =

Frequency (in Hz) Output Voltage (in volts) Gain = 20 log (Vo / Vin) (in dB)

RESULT:

Thus, the Cascade/cascoded amplifier was constructed and the gain was determined.
 VIVA QUESTIONS

1. List out the advantages &disadvantages cascaded amplifie.

2. Cascaded differential amplifier requires level translator because of______________

3. The cascode amplifier is composed of direct coupled_______________ configuration

4. What are the advantages of double tuned over single tuned?

5. What do you mean by frequency response of RC coupled amplifier?

6. Why gain falls at HF and LF?

7. Why the gain remains constant at MF?

8. Explain the function of emitter bypass capacitor, Ce?

9. How the band width will effect as more number of stages are cascaded?

10. What is an effect of cascading?

EXP NO: DETERMINATION OF BANDWIDTH OF SINGLE STAGE
AND MULTISTAGE AMPLIFIERS

Aim:
To determine the bandwidth of Single Stage and Multistage Amplifiers.

Apparatus:

S.No. Name Range Quantity

1. FET , Transistor BFW10 , BC107 1,2
2. Resistor 100MΩ, 1kΩ,2.75KΩ,33KΩ,10KΩ,8.2KΩ 1,1,2 ,4,2,2
3. Capacitor 1.59nf, 0.578µf,10µf,100µf 2,1,3,2
4. Regulated power supply (0-30)V 1
5. Function Generator (0-3) MHz 2
6. CRO 30 MHz 1
7. Bread Board 1

Circuit Diagram:

Single Stage Common Source Amplifier Multistage Amplifier

Theory:
The CS amplifier is a small signal amplifier. For good bias stability, the source resistor
voltage drop should be as large as possible. Where the supply voltage is small, Vs may be
reduced to a minimum to allow for the minimum level of Vds.R2 is usually selected as 1MΏ or
less as for BJT capacitor coupled circuit, coupling and bypass capacitors should be selected to
have the smallest possible capacitance values. The largest capacitor in the circuit sets the circuit
low 3dB frequency (capacitor C2). Generally to have high input impedance FET is used. As in
BJT circuit RL is usually much larger than Zo and Zi is often much larger than Rs.

Procedure:
1. Connect the circuit as per the circuit diagram.
2. Give 1 KHz signal and 25 mv (P-P) as Vs from signal generator.
3. Observe the output on CRO for proper working of the amplifier.
4. After ensuring the amplifier function, vary signal frequency from 50 Hz to 600 Hz in proper
steps for 15-20 readings keeping Vs =25mv(PP) at every frequency ,note down the resulting
output voltage and tabulate it.

TABULATION:
Keep the input voltage constant, Vin =

Frequency (in Hz) Output Voltage (in volts) Gain= 20 log(Vo/Vin) (in dB)

Model Graph:
Result:

Thus, the bandwidth of Single Stage and Multistage Amplifier was determined.
 VIVA QUESTIONS

1. What are the advantages and disadvantages of single-stage amplifiers?

2. Advantages of RC Coupled amplifier?

3. Disadvantages of RC coupled amplifier?

4. Applications of RC Coupled amplifier?

5. What is Tuned voltage amplifier? Specify it purposes?

6. Classification of Tuned Amplifier?

7. What do you mean by Single tuned amplifier.

8. What do you mean by Double Tuned Amplifier.

9. Advantages & Disadvantages of Tuned amplifier

10. Advantages of Double Tuned over single tuned.

EXP NO: SPICE SIMULATION OF COMMON EMITTER &
COMMON SOURCE AMPLIFIERS
DATE:
Aim:
To Simulate the Common Emitter and Common Source Amplifiers using SPICE
software.

Apparatus:

1. PERSONAL COMPUTER 2. SPICE SOFTWARE

Circuit Diagram:

Common Emitter Amplifiers

 Common Source Amplifiers

Theory:

Common Emitter Amplifiers

The CE amplifier is a small signal amplifier. This small signal amplifier accepts low
voltage ac inputs and produces amplified outputs. A single stage BJT circuit may be employed as
a small signal amplifier; has two cascaded stages give much more amplification. Designing for a
particular voltage gain requires the use of a ac negative feedback to stabilize the gain. For good
bias stability, the emitter resistor voltage drop should be much larger than the base -emitter
voltage. And Re resistor will provide the required negative feedback to the circuit. CE is
provided to provide necessary gain to the circuit. All bypass capacitors should be selected to
have the smallest possible capacitance value, both to minimize the physical size of the circuit for
economy. The coupling capacitors should have a negligible effect on the frequency response of
the circuit.
Common Source Amplifiers

The D.C biasing in common collector is provided by R1, R2 and RE .The load resistance
is capacitor coupled to the emitter terminal of the transistor.

When a signal is applied to the base of the transistor, VB is increased and decreased as
the signal goes positive and negative, respectively. Considering VBE is constant the variation in
the VB appears at the emitter and emitter voltage VE will vary same as base voltage VB . Since
the emitter is output terminal, it can be noted that the output voltage from a common collector
circuit is the same as its input voltage. Hence the common collector circuit is also known as an
emitter follower.

Procedure for Common Emitter Amplifiers:

1. Connect the circuit as per the circuit diagram.
2. Give l00Hz signal and 20mv p-p as Vs from the signal generator
3. Observe the output on CRO and note down the output voltage.
4. Keeping input voltage constant and by varying the frequency in steps 100Hz-1MHz, note
down the corresponding output voltages.
5. Calculate gain in dB and plot the frequency response on semi log sheet

Procedure for Common Source Amplifiers:

1. Connect the circuit as per the circuit diagram.
2. Set Vi =50 mV, using the signal generator.
3. Keeping the input voltage constant, vary the frequency from 0 Hz to 1M Hz in regular steps
and note down the corresponding output voltage.
4. Plot the graph; Gain (dB) Vs Frequency (Hz).

Result:

Thus, the Common Emitter and Common Source Amplifiers are simulated using
SPICE software.