Name : Waqar baig

SID:8878
Lab 12
Question) Design a FSM to Detect Negative Edge.

CODE:
library IEEE;

use IEEE.STD_LOGIC_1164.ALL; entity

waqar_12 is

port(

reset, clk, stobe : in std_logic;

output : out std_logic

);

end waqar_12; architecture

Behavioral of waqar_12 is type

mc_state_type is

(idle, s1, s2, s3); signal

r_reg,r_nxt : mc_state_type; begin

-- r_reg

process(clk, reset)

begin

if reset = '1' then

r_reg <= idle; elsif (clk'event and clk

= '0') then r_reg <= r_nxt;

end if;

end process;

-- r_nxt
 process(r_reg,stobe)
begin case
r_reg is when
idle =>
if (stobe = '0') then

r_nxt<= s1;

else

r_nxt<= s2;

end if;

when s1 =>

if (stobe = '0') then

r_nxt<= s1;

else

r_nxt<= s2;
end if;

when s2 =>

if (stobe= '0') then

r_nxt<= s3;

else

r_nxt<= s2;

end if;
when s3 =>

if (stobe = '0') then

r_nxt<= idle;

else

r_nxt<= s2;
end if;

end case;

end process;

-- moore output

process(r_reg)
 begin

output <= '0';

case r_reg is

when idle =>

when s1 =>

when s2 =>

when s3 =>

output <= '1';

end case;

end process;

end Behavioral;

TEST BENCH:
-- Stimulus process

stim_proc: process

begin

-- hold reset state for 100 ns.

wait for 100 ns;

reset<='0' ;wait for 200 ns; stobe<='0' ;wait for 30 ns; stobe<= '0';wait for 50 ns;

stobe<='1';wait for 30 ns; stobe<='1' ;wait for 30 ns; stobe<= '1';wait for 50 ns;

stobe<='0';wait for 30 ns; stobe<='0' ;wait for 30 ns; stobe<= '1';wait for 50 ns;

stobe<='0';wait for 30 ns; wait for clk_period*10; end process;

UCF FILE:
# Switch
NET "stobe" LOC = "G18";
NET "reset" LOC = "H18";
NET "clk" LOC = "B8";

# output
NET "output" LOC = "J14;