FPGA Lab 13

You might also like

Download as pdf or txt
Download as pdf or txt
You are on page 1of 1

PAF KARACHI INSTITUTE OF ECONOMICS AND TECHNOLOGY

Department of Electrical

College of Engineering

EE4423 – FPGA Based System Design


Semester: _____________________________ Date of Experiment: ____________________
Student name: _________________________ Faculty Signature: _____________________
Student ID: ___________________________ Class ID: _____________________________

Lab Design an FSM for The Solution of Any Practical Life Example.
13

PLO_1 – Engineering Knowledge C2 – Understanding


PLO_4 – Investigation P3 – Manipulate with guidance
Bloom’s
PLOs PLO_5 – Modern tool usage
Taxonomy
P3 - (Operate)
PLO_9 – Team Work A3 – Assume responsibility
PLO_8 – Ethics P2 – Set

PERFORMANCE PARAMETERS
Excellent Average Poor M
CLOs Aspects of Assessments
(75-100%) (50-75%) (<50%)
Recall: Recall basic passive Complete understanding of the Understand some concepts / Student lacks clear understanding of
circuit elements and their concepts / actively participate participates less in class / read the basic concepts of digital logic
CLO1
Functionality/Recall the basic during lecture /read and Schematics but unable to fundamental. Read schematic but
10% concepts of combination and interpret schematic diagrams, interpret them accurately. unable to interpret completely.
sequential Circuits
Implementation Construction / Student efficiently construct a Construct a circuit by Construct a circuit accurately only
Realization of Circuits using circuit by following schematic following schematic diagram with help from the teacher.
Spartan 3E Board. diagram. but with minor errors.
CLO2 Analysis Circuit Analysis of Accurately does data analysis / Conducts computations with Able to conduct analysis on
40% provided problem with the help hardware description language minor error; and reasonably collected data, no attempt to
of hardware description language (HDL) and digital logic gates correlates results to known correlate experimental results with
(HDL) and digital logic gates. results to expected theoretical theoretical values. known theoretical values.
values.
Tools Utilization Hardware Effectively use hardware Uses hardware equipment Does not know how to use hardware
CLO4 equipment / Software tool usage equipment / software tools to /software tools to collect data equipment /software tools to collect
30% for Circuit implementation and collect readings. with minor error. and analyze data.
analysis
Team Work Completion of Lab Proactively work with other Worked well with team but did Very little, if any, contributions to
CLO5
tasks with proper team work and team members to complete not offer much positive group and less contribution in
10% contribution. assigned tasks. feedback. completion of overall lab tasks.
Lab Safety Properly handle lab Properly handle lab equipment Moderate level lab handling Minor or no safety measurements
CLO6
infrastructure with safety & obey safety measures. and safety measurements has been considered.
10% precautions
Total Marks: 10

You might also like