Rana University

Faculty of Computer Science

Course Title Digital Gates and Logic Design

Lecturer Name Naveedullah Safi
Credit Hours 3
Lecture Days
Lecture Timing Early Morning, Morning, Afternoon, Evening
Class No.

Course Description

Digital Logic Design includes the following topics which prepare the students for the design of circuits used
in microcomputer: number system, computer codes, logic gates, Boolean algebra, combinational logic
circuits, half adder, full adder, half subtractor, full subtractor, encoder, decoder, Multiplexer and DE
.multiplexer

Course Objective
This course is to familiarize the student with fundamental principles of digital design. It provides coverage
.of classical hardware design for both combinational and sequential logic circuits

Teaching Method

 Explaining the concept and Solving related problems on the white board.
 Using slides and lecture notes related to subject.

Learning Outcome
:A student who successfully fulfills the course requirements will have demonstrated an ability to
.Design combinational and sequential circuits using Boolean algebra .1
.Design combinational and sequential circuits using Karnaugh Maps .2
.Work with the various Complement Arithmetic Systems used for hardware arithmetic .3
.Understand elementary Boolean codes .4

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 Digital Logic Design
Introduction to DLD

Week 1
Objectives of the course
Number System
Conversions
Conversions
Week 2

 Octal to binary
 Binary to octal
 Arithmetic
Binary Hexadecimal to binary
Week 3

 Binary Addition
 Binary Subtraction
 Binary Multiplication
Complements
Week 4

 9’s & 10’s Complements

 1’s & 2’s Complements

Logical Gates
Week 5

Types of Logical Gates

1. OR Gate
2. AND Gate
3. NOTtoGate
Introduction Boolean Algebra
Week 6

• Logical Addition:
• Logical Multiplication
• Logical Negation
Boolean expression
Laws of Boolean Algebra
Week 7

 Commutative law
 Associative law
 Distributive law
Theorems of Boolean Algebra
Week 8

DeMorgan’s Theorem
Simplification of Boolean algebra using DeMorgan’s theorem

MID TERM EXAMINATION

Canonical and standard forms

Week 9

 Sum term (Minterm)

 Product term (Maxterm)
 Sum of product
Conversion
Week 10

 Conversion of Minterm to Maxterm

 Conversion of Maxterm to Minterm

The Karnaugh Map

Week 11

 Karnaugh Map Method

 K-Method Basic idea and Examples

Karnaugh Map SOP Minimizations

Week 12

 Karnaugh Map 2-variable

 Karnaugh Map 3- Variable
 Karnaugh Map 4 Variable

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 Karnaugh Map POS Minimizations

Week 13
 Karnaugh Map 2-variable
 Karnaugh Map 3- Variable
 Karnaugh Map 4 Variable
Combinational Logic
Week 14

 Logic Circuits & Types

 Combinational Circuit

Adders
Week 15

 Half adder
 Full adder
Subtractors
Encoder
Week 16

Decoder
Multiplexer
Demultiplexer

Assessment 1) Midterm exams 20 %

2) Attendance and group work 10 %
3) Projects, presentations, and other tasks 10 %
4) Final Exam 60 %

Total Marks: 100

Recommended Books
1. COMPUTER LOGIC DESIGN by M. Morris Mano
2. DIGITAL COMPUTER ELECTRONICS by Malvino
3. DIGITAL FUNDAMENTALS 7th Edition, Thomas L. Floyd Prentice-Hall International, Inc.

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