HDLC is a standard protocol for data link layers that formats bits in frames for synchronous communication between devices. An HDLC frame contains flag bits at the start and end, address bits, control bits indicating frame type and sequence numbers, data bits which are stuffed to distinguish from flags, a frame check sequence, and notes on acknowledgement protocols. The document details the sequence and purpose of each part of an HDLC frame.
HDLC is a standard protocol for data link layers that formats bits in frames for synchronous communication between devices. An HDLC frame contains flag bits at the start and end, address bits, control bits indicating frame type and sequence numbers, data bits which are stuffed to distinguish from flags, a frame check sequence, and notes on acknowledgement protocols. The document details the sequence and purpose of each part of an HDLC frame.
HDLC is a standard protocol for data link layers that formats bits in frames for synchronous communication between devices. An HDLC frame contains flag bits at the start and end, address bits, control bits indicating frame type and sequence numbers, data bits which are stuffed to distinguish from flags, a frame check sequence, and notes on acknowledgement protocols. The document details the sequence and purpose of each part of an HDLC frame.
HDLC is a standard protocol for data link layers that formats bits in frames for synchronous communication between devices. An HDLC frame contains flag bits at the start and end, address bits, control bits indicating frame type and sequence numbers, data bits which are stuffed to distinguish from flags, a frame check sequence, and notes on acknowledgement protocols. The document details the sequence and purpose of each part of an HDLC frame.
Control) is a standard protocol for the data link network. For synchronous communication between two data link layers on a network.
Chapter-3 L03: "Embedded Systems - " , Raj Kamal,
2008 2 Publs.: McGraw-Hill Education Formats of bits in a HDLC frame There are two formats Standard HDLC and Extended HDLC for 28 and 216 destination devices or systems, respectively .
Chapter-3 L03: "Embedded Systems - " , Raj Kamal,
2008 3 Publs.: McGraw-Hill Education Sequence of bits in a HDLC frame
Chapter-3 L03: "Embedded Systems - " , Raj Kamal,
2008 4 Publs.: McGraw-Hill Education Frame start signaling flag bits; Compulsory- Flag bits at start are (01111110)
Chapter-3 L03: "Embedded Systems - " , Raj Kamal,
2008 5 Publs.: McGraw-Hill Education Address bits for destination compulsory; 8 bits in Standard HDLC Header format and 16 bits in extended format
Chapter-3 L03: "Embedded Systems - " , Raj Kamal,
2008 6 Publs.: McGraw-Hill Education Control bits Case 1: Information Frame; Compulsory as per case 1 or 2 or 3First bit 0, next 3-bits N(S), next bit $P/F and last 3-bits N(R) in standard format
Note: N(R) and N(S) = 7-bits each in
extended format. Explained later.
Chapter-3 L03: "Embedded Systems - " , Raj Kamal,
2008 7 Publs.: McGraw-Hill Education Control bits Case 2: Supervisory Frame; First two bits (10), next 2- bits# RR or RNR or REJ or SREJ, next bit P/F and last 3-bits N(R) in standard format. Note: N(R) and N(S) = 7-bits each in extended format
Chapter-3 L03: "Embedded Systems - " , Raj Kamal,
2008 8 Publs.: McGraw-Hill Education Control bits Case 3: Un-numbered Frame; First two bits (11), next 2-bits ^M, next bit P/F and last 3-bit remaining bits for M. [8-bits are immaterial after M bits in extended format]
Chapter-3 L03: "Embedded Systems - " , Raj Kamal,
2008 9 Publs.: McGraw-Hill Education Data bits; Compulsory; m frame bits transmitted; Each bit is at the serial line for time ∆T or, each frame is at the line for time m.∆T. [Note: Five consecutive 1s when present, then one additional 0 is stuffed in the data. This is to distinct the data from the start and ending bytes at the header and at the end. Number of frame bits extend.] Chapter-3 L03: "Embedded Systems - " , Raj Kamal, 2008 10 Publs.: McGraw-Hill Education FCS (Frame Check Sequence) bits; Compulsory; 16 bits in standard format and 32 in extended format
Chapter-3 L03: "Embedded Systems - " , Raj Kamal,
2008 11 Publs.: McGraw-Hill Education Frame End flag bits; Compulsory; Flag bits at end = (01111110)
Chapter-3 L03: "Embedded Systems - " , Raj Kamal,
2008 12 Publs.: McGraw-Hill Education Notes P/F when 1 then it means a primary (command) device is polling a secondary station. Polling means to detect through an acknowledgement from that; when 0 then receiving device has no data to transmit; it is just responding.
Chapter-3 L03: "Embedded Systems - " , Raj Kamal,
2008 13 Publs.: McGraw-Hill Education N(R) sequence number of frame received earlier from a device to which this HDLC frame is being sent N(S) sequence number of frame sending now to that device This facilitates indirectly an acknowledgement of the past in the new frame sending now.
Chapter-3 L03: "Embedded Systems - " , Raj Kamal,
2008 14 Publs.: McGraw-Hill Education RR- A message in control bits in case 2, which conveys ‘Receiver Ready’ RNR - ‘Receiver Not Ready’
Chapter-3 L03: "Embedded Systems - " , Raj Kamal,
2008 15 Publs.: McGraw-Hill Education REJ – Reject (Sent when a message rejects). Note there is no Accepted message as HDLC follows negative ACK protocol method. Like a child, who cries when milk not received, if given no need to cry! SREJ – ‘Selectively Reject’ Frame received out-of-sequence, repeat suggested.
Chapter-3 L03: "Embedded Systems - " , Raj Kamal,
2008 16 Publs.: McGraw-Hill Education Summary
Chapter-3 L03: "Embedded Systems - " , Raj Kamal,
2008 17 Publs.: McGraw-Hill Education We learnt Formats and sequences of bits In HDLC protocol
Chapter-3 L03: "Embedded Systems - " , Raj Kamal,
2008 18 Publs.: McGraw-Hill Education End of Lesson 3 of Chapter 3