Module:3

Processing Unit – Control Path

L4:Instruction cycle-Fetch , Decode, Execute

Dr. Gayathri Sivakumar

Assistant Professor Sr. Grade
SENSE
VIT, Chennai
 Instruction Cycle
Fetch, Decode and Execute
What is Instruction Cycle?
• The processing required for a single instruction is called instruction cycle Instruction
Fetch
• The control unit’s task is to go through an instruction cycle into five phases
Instruction
Instruction cycle steps and actions Decode

Operand
Fetch

Execute (ADD)

Result
Store

Next
Instruction
Instruction cycle state Diagram
Instruction address calculation (IAC)-Determine the address of the next
instruction to be executed
Instruction fetch (IF): Read instruction from its memory location into the
processor
Instruction operation decoding (ID)-Analyze instruction to determine type
of operation to be performed and operand(s) to be used.
Operand address calculation (OAC): If the operation involves reference to
an operand in memory or available via I/O, then determine the address of the
Operand
Operand fetch (OF): Fetch the operand from memory or read it in from I/O.
Data operation (DO): Perform the operation indicated in the instruction.
Operand store (SR): Write the result into memory or out to I/O.
Instruction cycle state Diagram

Instruction cycle steps and actions

 Instruction cycle flow Diagram
• Each of the basic
operations such as fetch
or read or write
operation constitutes a
machine cycle
• An instruction cycle
consists of several
machine cycles
• 3 different cases of ADD
instruction
• Addressing mode affect
how fast an instruction
cycle is completed
Cont..
Cont..
Cont..
Constituent Elements of Program Execution

-Computer executes a program

-Fetch and execute cycle
-Each cycle has a number of steps
called micro-operations
The Instruction Cycle
 Fetch - four Registers
• Memory Address Register (MAR)
• Connected to address bus
• Specifies address for read or write op
• Memory Buffer Register (MBR)
• Connected to data bus
• Holds data to write or last data read
• Program Counter (PC)
• Holds address of next instruction to be
fetched
• Instruction Register (IR)
• Holds last instruction fetched
 t1: MAR <- (PC)
t2: MBR <- (memory)
Fetch Sequence PC <- (PC) +I
t3: IR <- (MBR)
• Address of next instruction is in PC (tx = time unit/clock cycle)
• Address (MAR) is placed on address bus or
• Control unit issues READ command on t1: MAR <- (PC)
control bus
t2: MBR <- (memory)
• Result (data from memory) appears on data
bus t3: PC <- (PC) +I
• Data from data bus copied into MBR IR <- (MBR)
• PC incremented by 1 (in parallel with data
fetch from memory)
• Data (instruction) moved from MBR to IR
• MBR is now free for further data fetches
 Cont..

t1: MAR <- (PC)

t2: MBR <- (memory)
PC <- (PC) +1
t3: IR <- (MBR)
Rules for Clock Cycle Grouping

• Proper sequence must be followed

• MAR <- (PC) must precede MBR <- (memory)
• Conflicts must be avoided
• Must not read & write same register at same time
• MBR <- (memory) & IR <- (MBR) must not be in same cycle
• Also: PC <- (PC) +1 involves addition
• Use ALU
• May need additional micro-operations
Indirect Cycle

• MAR <- (IRaddress) - address

field of IR
• MBR <- (memory)
• IRaddress <- (MBRaddress)

• MBR contains an address

• IR is now in same state as if
direct addressing had not been
used
Interrupt Cycle

t1: MBR <-(PC)

t2: MAR <- save-address
PC <- routine-address
t3: memory <- (MBR)
• This is a minimum
• May be additional micro-ops to get addresses
• saving context is done by interrupt handler routine, not micro-ops
Execute Cycle (ADD)

• Different for each instruction

• e.g. ADD R1,X - add the contents of location X to Register 1, result in
R1
t1: MAR <- (IRaddress)
t2: MBR <- (memory)
t3: R1 <- R1 + (MBR)
• Note no overlap of micro-operations
Execute Cycle (ISZ)

• ISZ X - increment and skip if zero

t1: MAR <- (IRaddress)
t2: MBR <- (memory)
t3: MBR <- (MBR) + 1
t4: memory <- (MBR)
if (MBR) == 0 then PC <- (PC) + 1
• Notes:
• if is a single micro-operation
• Micro-operations done during t4
Execute Cycle (BSA)

• BSA X - Branch and save address

• Address of instruction following BSA is saved in X
• Execution continues from X+1
t1: MAR <- (IRaddress)
MBR <- (PC)
t2: PC <- (IRaddress)
memory <- (MBR)
t3: PC <- (PC) + I
Instruction Cycle

• Each phase decomposed into sequence of elementary micro-operations

• E.g. fetch, indirect, and interrupt cycles
• Execute cycle
• One sequence of micro-operations for each opcode
• Need to tie sequences together
• Assume new 2-bit register
• Instruction cycle code (ICC) designates which part of cycle processor is in
• 00: Fetch
• 01: Indirect
• 10: Execute
• 11: Interrupt
Flowchart for Instruction Cycle

01
Reference

• William Stallings, 8th Edition, Computer Organization and

Architecture, Designing for Performance, Pearson, 2010, New Jersey
• B.Govindarajalu, 2nd Edition, Computer Architecture and
Organization, Design Principles and Applications, Tata-McGraw-Hill,
2010, New Delhi