A B C D E

1 1

2
LCFC Confidential 2

NM-A221 Rev1.0 Schematic

Intel Crescent Bay Processor with DDRIIIL + Wild Cat Point PCH
3 AMD Opal-XT/ Jet-XT 3

2013-09-07 Rev1.0

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2013/09/07 Deciphered Date 2014/09/07 COVER PAGE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 1 of 81
A B C D E
 A B C D E

USB 2.0 Port 7

Broad Well
eDP Conn.
USB Port 7
DP Port0 Memory BUS (DDRIII)
DP Port 0
1DPC (Interleaved) DDR3L-SO-DIMM X2
Page 38
BANK 0, 1, 2, 3
USB 2.0 Port 2 & 3 5V 480MHz 1.35V DDRIIIL 1333/1600 MT/s
1 UP TO 16G Page 18~19 1

OneLink board
Intel
USB 3.0 Port 4 5V 5GT/s
Page 34 Crescent Bay
Processor Jet-XT M2 (AMD Radeon R5 M240)
PCIE Port 5 Topaz-XT M2(AMD Radeon R5 M240)
DP Repeater DDI1 HDMI
On OneLink board BGA1168 VRAM 128M*16 *8
VRAM 256M*16 *8
PCIe port 5
DDI1 40mm*24mm
MUX Page 20~29

HDMI Conn. DDI2 DP DDI1

Page 42 USB Left
Page 46
USB 2.0 Port 0,1
5V 480MHz JUSB1 JUSB2
USB 3.0 Port 2 USB 3.0 Port 1
VGA Conn DP DDI2 USB 2.0 Port 1 USB 2.0 Port 0
Traslater to USB 3.0 Port1,2 Page 41 Page 40
CRT
2

Page 44 Page 43 + 5V 5GT/s

2

PCIe Gen1 Port 3

NGFF Card
Intel
WGI218V-QQJZ Non Vpro NGFF Card WLAN NGFF Card
RJ45 Conn. PCIe Gen1 Port 4 SATA Gen3 Port 1 PCIe Port 3 mSATA/WWAN(option)
WGI218LM QQJY Vpro
QFN48_6X6 USB 2.0 port6 SATA Port 1
Page 48 USB 2.0 port4
PCIe port 4 USB 2.0 port 4&6 page 52 page 52
Page 47
Intel WPT Point
Realtek PCH USB 2.0 Port 5 Finger printer
RTS5227E PCIe Gen1 Port 6 Page 50
SD/MMC/XD Conn
Page 32 SATA Gen3 Port 0 SATA HDD
3
SATA Port 0 3
page 37
Power Circuit DC/DC
Page 65~70 SPI ROM SPI BUS
(8MB for NVpro) 3.3V 33MHz
SATA Gen2 Port 1 SATA ODD
SATA Port 1
(12MB for Vpro) page 37
One-Link Docking Board LPC BUS
Page 9
& 3.3V 33MHz
USB3.0 Port3 HD Audio Codec SP_OUTR/L
3.3V 24MHz ALC3232-CG SPK Conn.
Page 36
EC Page 35, 36
Mirror function USB 2.0 Port 4
ITE IT8586E/FX
HP_R/L_JACK
Page 62
Combon Jack Board Ext Mic

Combon Jack
Page 54
4
Thermal Sensor Int.KBD Touch Pad Conn 4

Power Board Fintek F75303M USB Port 4

Page 55 Page 51 Page 51

Security Classification LC Future Center Secret Data Title

Issued Date 2013/09/07 Deciphered Date 2014/09/07 XXXX

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 2 of 81
A B C D E
 A B C D E

UC1
High Speed I/O port UC1
Voltage Rails ( O --> Means ON , X --> Means OFF )
I/O High Speed Signal Configuration Port assignment
+5VS Broadwell-1.8GHz 15W 2+2U 1600 DDR ES2
QGH9@
+3VS 1 USB3 1 USB3 1 On MB USB Haswell-ULT-CL8064701478202_SR16Q SA000810900
SR16Q@
Power Plane +1.5VS SA00005VY10 UC1

+VCCSA
2 USB3 2 USB3 2 On MB USB UC1

1
+V1.5S_VCCP 3 PCIE 1 / USB3 3 NC NC 1

+CPU_CORE Broadwell-1.6GHz ULV 15W 2+2U 1600 DDR ES2

+3VALW 4 PCIE 2 / USB3 4 USB3 4 Docking USB QGHB@
+VGA_CORE Broadwell-ULT-CL8065801674128_QG21SA000811100
B+ +1.5V QG21@
+GFX_CORE 5 PCIE 3 PCIE 3 WLAN SA000067H00 UC1

+5VALW +1.8VS UC1

+1.05VS
6 PCIE 4 PCIE 4 LAN
State +0.75VS 7 PCIE 5 L0 PCIE 5 L0 GPU Broadwell-1.6GHz 15W 2+2U 1333 DDR ES2
QGHA@
+3.3VS_VGA Broadwell-ULT-CL8065801675027_QG22SA000811000
QG22@
+1.5VS_VGA
8 PCIE 5 L1 PCIE 5 L1 GPU SA000067I00 UC1

+1.05VS_VGA 9 PCIE 5 L2 PCIE 5 L2 GPU UC1

10 PCIE 5 L3 PCIE 5 L3 GPU Haswell-CL8064701478404 QEAR D0

QEAR@
S0 O O O O 11 PCIE 6 L0 / SATA 3 PCIE 6 Cardreader Haswell-ULT-CL8064701477400_SR1ED SA00005YZ00
SR1ED@
SA00005YW10 UC1
12 PCIE 6 L1 / SATA 2 SATA 2 mSATA
S3 O O O X 13 PCIE 6 L2 / SATA 1 SATA 1 ODD UV1
Haswell-CL8064701477600 QEAH D0 2.0G
2 QEAH@ 2
14 PCIE 6 L3 / SATA 0 SATA 0 HDD SA000066W00

S5 S4/AC Only O O X X BOM Structure Table JET M2 XT

JET@
SA000066500
BOM Structure NOTE
S5 S4
Battery only O X X X PCB@ For PCB load BOM ZZZ7 X76_S2G@ ZZZ8 X76_H2G@ ZZZ9 X76_M2G@

3G@ 3G function(Option with TS@)

S5 S4
TPM@ Trusted Platform Module (TPM) K4W4G1646D-BC1A H5TC4G63AFR-11C MT41J256M16HA-093G:E
AC & Battery X X X X X7603901003 X7603901001 X7603901002

don't exist NM14@ 14" SKU ID ZZZ10 X76_S1G@ ZZZ11 X76_H1G@ ZZZ12 X76_M1G@

NM15@ 15" SKU ID

SMBUS Control Table UMA@ UMA SKU ID K4W2G1646Q-BC1A H5TC2G63FFR-11C MT41J128M16JT-093G:K

X7603901004 X7603901005 X7603901006

Main WLAN Thermal CP

DIS@ Optimus SKU ID
SOURCE LAN BATT IT8586E SODIMM PCH Charger
VGA WiMAX Sensor Module
3 X76@ GPU VRAM Setting UL1 VPRO@ 3

PCH_SML0_CLK PCH
M2G@ Micron 256Mx16 VRAM
PCH_SML0_DAT X V X X X X X X X X
+3V_PCH +3V_PCH M1G@ Micron 128Mx16 VRAM WGI218LM-QQJY-B1_QFN48_6X6
SA00005TP10

PCH_SML1CLK PCH
S2G@ Samsung 256Mx16 VRAM UC1 UC1 UC1
PCH_SML1DATA V X X V X X V X X X
+3V_PCH +3VS +3VS +3VS S1G@ Samsung 128Mx16 VRAM

EC_SMB_CK1 IT8586E
ME@ ME Connector BDW-3205U-1.5G BDW-3755U-1.7G BDW-i7-2.2G
EC_SMB_DA1 X X V X X X X X X V QGZ6@ QGZ5@ QH15@
+3VL +3VL +3VL TS@ Touch screen function SA000072M00 SA000072J00 SA000072L00

UC1 UC1 UC1 UC1

PCH_SMBCLK PCH
DEBUG@ For debug
PCH_SMBDATA
+3V_PCH X X X X V X X V V X BYPASS@ For bypass
+3VS +3V_PCH +3VS
BDW-i3-2G BDW-i3-2G BDW-i5-2G BDW-3805U-1.9G
QH18@ QGZ3@ QH17@ QGZ4@
MIRROR@ For mirror function SA000072H00 SA000072P00 SA000072K00 SA000072N00

SIGNAL NVPRO@ For Non-VPRO function UC1 UC1 UC1 ZZZ1

STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
4 4

Full ON HIGH HIGH HIGH HIGH ON ON ON ON

VPRO@ For VPRO function
X76_S2G@
S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
For Samsung 2G VRAM HSW I3 4030U HSW I5 4210U HSW I3 4005U
SR1EN@ SR1EF@ SR1EK@
NM-A221
PCB@
S2G@ SA000810100 SA000066Y20 SA00005YZ20 DAZ0TS00100

S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF Security Classification LC Future Center Secret Data Title

S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF

Issued Date 2013/09/07 Deciphered Date 2014/09/07 NOTE LIST
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
AITE1_NM-A221 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Thursday, November 06, 2014 Sheet 3 of 81
A B C D E
 5 4 3 2 1

Hot plug detect for IFP link E

Performance Mode P0 TDP at Tj = 102 C* (GDDR5)
FBVDDQ PCI Express I/O and I/O and Other
VGA and GDDR5 Voltage Rails (N13Px GPIO) GPU Mem NVCLK FBVDD (GPU+Mem) (1.05V) PLLVDD PLLVDD
(4) (1,5) /MCLK NVVDD (1.35V) (1.35V) (6) (1.8V) (1.05V) (3.3V)
GPIO I/O ACTIVE Function Description Products (W) (W) (MHz) (V) (A) (W) (A) (W) (A) (W) (mA) (W) (mA) (W) (mA) (W) (mA) (W)

GPIO0 OUT - GPU VID4 N13X

128bit TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
D
1GB D
GPIO1 OUT - GPU VID3 GDDR5

GPIO2 OUT - VGA_BL_PWM Physical Logical Logical Logical Logical

Strapping pin Power Rail Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
GPIO3 OUT - VGA_ENVDD ROM_SCLK +3VS_VGA PCI_DEVID[4] SUB_VENDOR SLOT_CLK_CFG PEX_PLL_EN_TERM
GPIO4 OUT ROM_SI +3VS_VGA RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0]
- VGA_ENBKL
ROM_SO +3VS_VGA FB[1] FB[0] SMB_ALT_ADDR VGA_DEVICE
GPIO5 OUT - GPU VID1
STRAP0 +3VS_VGA USER[3] USER[2] USER[1] USER[0]
GPIO6 OUT - GPU VID2 STRAP1 +3VS_VGA 3GIO_PAD_CFG_ADR[3] 3GIO_PAD_CFG_ADR[2] 3GIO_PAD_CFG_ADR[1] 3GIO_PAD_CFG_ADR[0]
STRAP2 +3VS_VGA PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]
GPIO7 OUT - DPRSLPVR_VGA
STRAP3 +3VS_VGA SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED
GPIO8 I/O - Thermal Catastrophic Over Temperature STRAP4 +3VS_VGA RESERVED PCIE_SPEED_ PCIE_MAX_SPEED DP_PLL_VDD33V
CHANGE_GEN3
GPIO9 OUT - GPIO9
Device ID setting I2C Slave addrees ID
GPIO10 OUT - Memory VREF Control N13P-GT SMB_ALT_ADDR
(28nm) 0x0FDB 0 0x9E
(ROM_SO Bit 1)
GPIO11 OUT - GPU VID0
C C
1 0x9C
GPIO12 IN AC Power Detect Input (10K pull High)

GPIO13 OUT - GPU VID5

GPIO14 OUT - FB_CLAMP_TOGGLE_REQ#

GPU ROM_SO ROM_SCLK STRAP0 STRAP1 STRAP2 STRAP3 STRAP4
GPIO15 IN N/A (100K pull low)
PU 10K PU 25K PU 45K PD 35K PD 10K PU 5K PD 10K Master
GPIO16 OUT - FRMLCK# N13P-GT1
28nm PU 20K PU 25K PU 45K PD 35K PD 10K PD 5K PD 10K Slave
GPIO17 IN N/A

GPIO18 IN - dGPU_HDMI_HPD

GPIO19 IN - HPD_IRQ
GPU N13P-GT

FB Memory (GDDR5) ROM_SI

Samsung K4G10325FG-HC04
B
+3VS_VGA 2500MHz B

32Mx32 PD 45K
+VGA_CORE
Hynix H5GQ1H24BFR-T2C
tNVVDD >0 2500MHz
+1.5VS_VGA 32Mx32 PD 35K
tFBVDDQ >0
Samsung K4G20325FD-FC04
+1.05VS_VGA 2500MHz
tPEX_VDD >0 64Mx32 PD 30K

Hynix H5GQ2H24MFR-T2C
1. all power rail ramp up time should be larger than 40us
2500MHz
64Mx32 PD 25K

Other Power rail

+3VS_VGA
A A

Tpower-off <10ms

Security Classification LC Future Center Secret Data Title

1.all GPU power rails should be turned off within 10ms Issued Date 2013/09/07 Deciphered Date 2014/09/07 VGA NOTE
2. Optimus system VDD33 avoids drop down earlier than NVDD and FBVDDQ
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 4 of 81
5 4 3 2 1
 5 4 3 2 1

D D

UC1A HSW_ULT_DDR3L QFSY@

DDI1_MUX_TX0- C54 C45 CPU_EDP_TX0-

<42> DDI1_MUX_TX0- C55 DDI1_TXN0 EDP_TXN0 B46 CPU_EDP_TX0- <38>
DDI1_MUX_TX0+ CPU_EDP_TX0+
<42> DDI1_MUX_TX0+ DDI1_MUX_TX1- B58 DDI1_TXP0 EDP_TXP0 A47 CPU_EDP_TX1- CPU_EDP_TX0+ <38>
<42> DDI1_MUX_TX1- C58 DDI1_TXN1 EDP_TXN1 B47 CPU_EDP_TX1- <38>
For 14" : DOCKING DDI1_MUX_TX1+ CPU_EDP_TX1+
<42> DDI1_MUX_TX1+ DDI1_MUX_TX2- B55 DDI1_TXP1 EDP_TXP1 CPU_EDP_TX1+ <38>
For 15" : HDMI & DOCKING <42> DDI1_MUX_TX2- DDI1_MUX_TX2+ A55 DDI1_TXN2 C47
<42> DDI1_MUX_TX2+ A57 DDI1_TXP2 EDP_TXN2 C46
DDI1_MUX_TX3-
<42> DDI1_MUX_TX3- DDI1_MUX_TX3+ B57 DDI1_TXN3 EDP_TXP2 A49
<42> DDI1_MUX_TX3+ DDI1_TXP3 DDI EDP EDP_TXN3 B49
DDI2_VGA_TX0- C51 EDP_TXP3
<43> DDI2_VGA_TX0- DDI2_VGA_TX0+ C50 DDI2_TXN0 A45 CPU_EDP_AUX#
For 14" : HDMI <43> DDI2_VGA_TX0+ DDI2_VGA_TX1- C53 DDI2_TXP0 EDP_AUXN B45 CPU_EDP_AUX
CPU_EDP_AUX# <38>
For 15" : VGA <43> DDI2_VGA_TX1- DDI2_TXN1 EDP_AUXP CPU_EDP_AUX <38>
DDI2_VGA_TX1+ B54
<43> DDI2_VGA_TX1+ C49 DDI2_TXP1 D20 1 2
EDP_COMP RC1 24.9_0402_1% +VCCIOA_OUT
B50 DDI2_TXN2 EDP_RCOMP A43
A53 DDI2_TXP2 EDP_DISP_UTIL
B53 DDI2_TXN3 EDP_RCOMP
DDI2_TXP3 1. Trace width=20 mils, Spacing=25mil, Max length=100mils
2. RC25 close to MCP
C
Trace Width=20mil, Spacing=25mil, Max length=100mil C

1 OF 19
Broadwell-ULT_CL8064701614813_QFSY
SA000064600

PU/PD Res. For CPU-XDP SIGNAL, Place R Closer to CPU

+1.05VS_VCCST HSW_ULT_DDR3L
UC1B
+1.05VS_VCCST
1

D61
K61 PROC_DETECT MISC XDP_TDI RC164 1 XDP@ 2 51_0402_1%
RC2 H_PECI N62 CATERR J62 XDP_PRDY# 1
<62> H_PECI PECI PRDY K62 XDP_PREQ# 1 T1 XDP_TDO 1 XDP@ 2 51_0402_1%
62_0402_5% RC3
PREQ E60 T2
XDP_TCLK
2

PROC_TCK E61 XDP_TMS 1 XDP_TCLK RC4 1 2 51_0402_1%

VR_HOT# 1 2 VR_HOT#_R K63 JTAG PROC_TMS E59 XDP_TRST# T3
<62,67,73> VR_HOT# RC5 56_0402_5%
PROCHOT THERMAL
PROC_TRST F63 XDP_TDI 1 XDP_TRST# RC6 1 @ 2 51_0402_1%
PROC_TDI F62 T4
XDP_TDO
PROC_TDO
RC7 1 2 10K_0402_5% H_CPUPWRGD C61
PROCPWRGD PWR
J60
B BPM#0 H60 B
BPM#1 H61

RC8 1 2 200_0402_1% SM_RCOMP0 AU60

BPM#2
BPM#3
H62
K59
XDP PU/PD portion need to check agian.
RC9 1 2 120_0402_1% SM_RCOMP1 AV60 SM_RCOMP0 DDR3L BPM#4 H63
RC10 1 2 100_0402_1% SM_RCOMP2 AU61 SM_RCOMP1 BPM#5 K60
DDR3_DRAMRST# AV15 SM_RCOMP2 BPM#6 J61
<18,19> DDR3_DRAMRST# DDR_PG_CTRL AV61 SM_DRAMRST BPM#7
<18> DDR_PG_CTRL SM_PG_CNTL1

DDR3 COMPENSATION SIGNALS Broadwell-ULT_CL8064701614813_QFSY

2 OF 19
1. Trace width=12~15 mil, Spcing=20 mils,
Max trace length= 500 mil,
2. All of R Close to MCP

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/09/07 Deciphered Date 2014/09/07 BDW_DDI/EDP/XDP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 5 of 81
5 4 3 2 1
 5 4 3 2 1

Interleaved (Butterfly Topology) Channel A Byte 0 & 1 Channel A Byte 4 & 5

Broadwell Platform System Memory Interface Channel B Byte 0 & 1 Channel B Byte 4 & 5
Document Number: 528378 MCP MCP
D
BDW U DDR3L/DDR3L-RS SO-DIMM Interleaved Recommendations D
Channel A Byte 2 & 3 Channel A Channel A Byte 6 & 7 Channel B
Channel B Byte 2 & 3 Channel B Byte 6 & 7

<18> DDR_A_D[0..63] <19> DDR_B_D[0..63]

<18> DDR_A_DQS#[0..7] <19> DDR_B_DQS#[0..7]
<18> DDR_A_DQS[0..7] <19> DDR_B_DQS[0..7]
<18> DDR_A_MA[0..15] <19> DDR_B_MA[0..15]

HSW_ULT_DDR3L HSW_ULT_DDR3L
UC1C UC1D

DDR_A_D0 AH63 AU37 SA_CLK_DDR#0

DDR_A_D1 AH62 SA_DQ0 SA_CLK#0 AV37 SA_CLK_DDR0 SA_CLK_DDR#0 <18> DDR_A_D32 AY31 AM38 SB_CLK_DDR#0
DDR_A_D2 AK63 SA_DQ1 SA_CLK0 AW36 SA_CLK_DDR#1 SA_CLK_DDR0 <18> DDR_A_D33 AW31 SB_DQ0 SB_CK#0 AN38 SB_CLK_DDR0 SB_CLK_DDR#0 <19>
AK62 SA_DQ2 SA_CLK#1 AY36 SA_CLK_DDR#1 <18> AY29 SB_DQ1 SB_CK0 AK38 SB_CLK_DDR0 <19>
DDR_A_D3 SA_CLK_DDR1 DDR_A_D34 SB_CLK_DDR#1
AH61 SA_DQ3 SA_CLK1 SA_CLK_DDR1 <18> AW29 SB_DQ2 SB_CK#1 AL38 SB_CLK_DDR#1 <19>
DDR_A_D4 DDR_A_D35 SB_CLK_DDR1
DDR_A_D5 AH60 SA_DQ4 AU43 DDRA_CKE0_DIMMA DDR_A_D36 AV31 SB_DQ3 SB_CK1 SB_CLK_DDR1 <19>
DDR_A_D6 AK61 SA_DQ5 SA_CKE0 AW43 DDRA_CKE1_DIMMA DDRA_CKE0_DIMMA <18> DDR_A_D37 AU31 SB_DQ4 AY49 DDRB_CKE0_DIMMB
C DDR_A_D7 AK60 SA_DQ6 SA_CKE1 AY42 DDRA_CKE1_DIMMA <18> DDR_A_D38 AV29 SB_DQ5 SB_CKE0 AU50 DDRB_CKE1_DIMMB DDRB_CKE0_DIMMB <19> C
DDR_A_D8 AM63 SA_DQ7 SA_CKE2 AY43 DDR_A_D39 AU29 SB_DQ6 SB_CKE1 AW49 DDRB_CKE1_DIMMB <19>
DDR_A_D9 AM62 SA_DQ8 SA_CKE3 DDR_A_D40 AY27 SB_DQ7 SB_CKE2 AV50
DDR_A_D10 AP63 SA_DQ9 AP33 DDRA_CS0_DIMMA# DDR_A_D41 AW27 SB_DQ8 SB_CKE3
DDR_A_D11 AP62 SA_DQ10 SA_CS#0 AR32 DDRA_CS1_DIMMA# DDRA_CS0_DIMMA# <18> DDR_A_D42 AY25 SB_DQ9 AM32 DDRB_CS0_DIMMB#
DDR_A_D12 AM61 SA_DQ11 SA_CS#1 DDRA_CS1_DIMMA# <18> DDR_A_D43 AW25 SB_DQ10 SB_CS#0 AK32 DDRB_CS1_DIMMB# DDRB_CS0_DIMMB# <19>
AM60 SA_DQ12 AP32 1 AV27 SB_DQ11 SB_CS#1 DDRB_CS1_DIMMB# <19>
DDR_A_D13 DDRA_ODT0 DDR_A_D44
AP61 SA_DQ13 SA_ODT0 T5 AU27 SB_DQ12 AL32 1
DDR_A_D14 DDR_A_D45 DDRB_ODT0
DDR_A_D15 AP60 SA_DQ14 AY34 DDR_A_RAS# DDR_A_D46 AV25 SB_DQ13 SB_ODT0 T6
DDR_B_D0 AP58 SA_DQ15 SA_RAS AW34 DDR_A_WE# DDR_A_RAS# <18> DDR_A_D47 AU25 SB_DQ14 AM35 DDR_B_RAS#
DDR_B_D1 AR58 SA_DQ16 SA_WE AU34 DDR_A_CAS# DDR_A_WE# <18> DDR_B_D32 AM29 SB_DQ15 SB_RAS AK35 DDR_B_WE# DDR_B_RAS# <19>
AM57 SA_DQ17 SA_CAS DDR_A_CAS# <18> AK29 SB_DQ16 SB_WE AM33 DDR_B_WE# <19>
DDR_B_D2 DDR_B_D33 DDR_B_CAS#
AK57 SA_DQ18 AU35 AL28 SB_DQ17 SB_CAS DDR_B_CAS# <19>
DDR_B_D3 DDR_A_BS0 DDR_B_D34
DDR_B_D4 AL58 SA_DQ19 SA_BA0 AV35 DDR_A_BS1 DDR_A_BS0 <18> DDR_B_D35 AK28 SB_DQ18 AL35 DDR_B_BS0
DDR_B_D5 AK58 SA_DQ20 SA_BA1 AY41 DDR_A_BS2 DDR_A_BS1 <18> DDR_B_D36 AR29 SB_DQ19 SB_BA0 AM36 DDR_B_BS1 DDR_B_BS0 <19>
DDR_B_D6 AR57 SA_DQ21 SA_BA2 DDR_A_BS2 <18> DDR_B_D37 AN29 SB_DQ20 SB_BA1 AU49 DDR_B_BS2 DDR_B_BS1 <19>
AN57 SA_DQ22 AU36 AR28 SB_DQ21 SB_BA2 DDR_B_BS2 <19>
DDR_B_D7 DDR_A_MA0 DDR_B_D38
DDR_B_D8 AP55 SA_DQ23 SA_MA0 AY37 DDR_A_MA1 DDR_B_D39 AP28 SB_DQ22 AP40 DDR_B_MA0
DDR_B_D9 AR55 SA_DQ24 SA_MA1 AR38 DDR_A_MA2 DDR_B_D40 AN26 SB_DQ23 SB_MA0 AR40 DDR_B_MA1
DDR_B_D10 AM54 SA_DQ25 SA_MA2 AP36 DDR_A_MA3 DDR_B_D41 AR26 SB_DQ24 SB_MA1 AP42 DDR_B_MA2
DDR_B_D11 AK54 SA_DQ26 SA_MA3 AU39 DDR_A_MA4 DDR_B_D42 AR25 SB_DQ25 SB_MA2 AR42 DDR_B_MA3
DDR_B_D12 AL55 SA_DQ27 SA_MA4 AR36 DDR_A_MA5 DDR_B_D43 AP25 SB_DQ26 SB_MA3 AR45 DDR_B_MA4
DDR_B_D13 AK55 SA_DQ28 SA_MA5 AV40 DDR_A_MA6 DDR_B_D44 AK26 SB_DQ27 SB_MA4 AP45 DDR_B_MA5
DDR_B_D14 AR54 SA_DQ29 SA_MA6 AW39 DDR_A_MA7 DDR_B_D45 AM26 SB_DQ28 SB_MA5 AW46 DDR_B_MA6
DDR_B_D15 AN54 SA_DQ30 DDR CHANNEL A SA_MA7 AY39 DDR_A_MA8 DDR_B_D46 AK25 SB_DQ29 SB_MA6 AY46 DDR_B_MA7
DDR_A_D16 AY58 SA_DQ31 SA_MA8 AU40 DDR_A_MA9 DDR_B_D47 AL25 SB_DQ30 SB_MA7 AY47 DDR_B_MA8
DDR_A_D17 AW58 SA_DQ32 SA_MA9 AP35 DDR_A_MA10 DDR_A_D48 AY23 SB_DQ31 DDR CHANNEL B SB_MA8 AU46 DDR_B_MA9
DDR_A_D18 AY56 SA_DQ33 SA_MA10 AW41 DDR_A_MA11 DDR_A_D49 AW23 SB_DQ32 SB_MA9 AK36 DDR_B_MA10
DDR_A_D19 AW56 SA_DQ34 SA_MA11 AU41 DDR_A_MA12 DDR_A_D50 AY21 SB_DQ33 SB_MA10 AV47 DDR_B_MA11
DDR_A_D20 AV58 SA_DQ35 SA_MA12 AR35 DDR_A_MA13 DDR_A_D51 AW21 SB_DQ34 SB_MA11 AU47 DDR_B_MA12
DDR_A_D21 AU58 SA_DQ36 SA_MA13 AV42 DDR_A_MA14 DDR_A_D52 AV23 SB_DQ35 SB_MA12 AK33 DDR_B_MA13
DDR_A_D22 AV56 SA_DQ37 SA_MA14 AU42 DDR_A_MA15 DDR_A_D53 AU23 SB_DQ36 SB_MA13 AR46 DDR_B_MA14
B DDR_A_D23 AU56 SA_DQ38 SA_MA15 DDR_A_D54 AV21 SB_DQ37 SB_MA14 AP46 DDR_B_MA15 B
DDR_A_D24 AY54 SA_DQ39 AJ61 DDR_A_DQS#0 DDR_A_D55 AU21 SB_DQ38 SB_MA15
DDR_A_D25 AW54 SA_DQ40 SA_DQSN0 AN62 DDR_A_DQS#1 DDR_A_D56 AY19 SB_DQ39 AW30 DDR_A_DQS#4
DDR_A_D26 AY52 SA_DQ41 SA_DQSN1 AM58 DDR_B_DQS#0 DDR_A_D57 AW19 SB_DQ40 SB_DQSN0 AV26 DDR_A_DQS#5
DDR_A_D27 AW52 SA_DQ42 SA_DQSN2 AM55 DDR_B_DQS#1 DDR_A_D58 AY17 SB_DQ41 SB_DQSN1 AN28 DDR_B_DQS#4
DDR_A_D28 AV54 SA_DQ43 SA_DQSN3 AV57 DDR_A_DQS#2 DDR_A_D59 AW17 SB_DQ42 SB_DQSN2 AN25 DDR_B_DQS#5
DDR_A_D29 AU54 SA_DQ44 SA_DQSN4 AV53 DDR_A_DQS#3 DDR_A_D60 AV19 SB_DQ43 SB_DQSN3 AW22 DDR_A_DQS#6
DDR_A_D30 AV52 SA_DQ45 SA_DQSN5 AL43 DDR_B_DQS#2 DDR_A_D61 AU19 SB_DQ44 SB_DQSN4 AV18 DDR_A_DQS#7
DDR_A_D31 AU52 SA_DQ46 SA_DQSN6 AL48 DDR_B_DQS#3 DDR_A_D62 AV17 SB_DQ45 SB_DQSN5 AN21 DDR_B_DQS#6
DDR_B_D16 AK40 SA_DQ47 SA_DQSN7 DDR_A_D63 AU17 SB_DQ46 SB_DQSN6 AN18 DDR_B_DQS#7
DDR_B_D17 AK42 SA_DQ48 AJ62 DDR_A_DQS0 DDR_B_D48 AR21 SB_DQ47 SB_DQSN7
DDR_B_D18 AM43 SA_DQ49 SA_DQSP0 AN61 DDR_A_DQS1 DDR_B_D49 AR22 SB_DQ48 AV30 DDR_A_DQS4
DDR_B_D19 AM45 SA_DQ50 SA_DQSP1 AN58 DDR_B_DQS0 DDR_B_D50 AL21 SB_DQ49 SB_DQSP0 AW26 DDR_A_DQS5
DDR_B_D20 AK45 SA_DQ51 SA_DQSP2 AN55 DDR_B_DQS1 DDR_B_D51 AM22 SB_DQ50 SB_DQSP1 AM28 DDR_B_DQS4
DDR_B_D21 AK43 SA_DQ52 SA_DQSP3 AW57 DDR_A_DQS2 DDR_B_D52 AN22 SB_DQ51 SB_DQSP2 AM25 DDR_B_DQS5
DDR_B_D22 AM40 SA_DQ53 SA_DQSP4 AW53 DDR_A_DQS3 DDR_B_D53 AP21 SB_DQ52 SB_DQSP3 AV22 DDR_A_DQS6
DDR_B_D23 AM42 SA_DQ54 SA_DQSP5 AL42 DDR_B_DQS2 DDR_B_D54 AK21 SB_DQ53 SB_DQSP4 AW18 DDR_A_DQS7
DDR_B_D24 AM46 SA_DQ55 SA_DQSP6 AL49 DDR_B_DQS3 DDR_B_D55 AK22 SB_DQ54 SB_DQSP5 AM21 DDR_B_DQS6
DDR_B_D25 AK46 SA_DQ56 SA_DQSP7 DDR_B_D56 AN20 SB_DQ55 SB_DQSP6 AM18 DDR_B_DQS7
DDR_B_D26 AM49 SA_DQ57 AP49 SM_DIMM_VREFCA DDR_B_D57 AR20 SB_DQ56 SB_DQSP7
AK49 SA_DQ58 SM_VREF_CA AR51 SM_DIMM_VREFCA <18> AK18 SB_DQ57
DDR_B_D27 SA_DIMM_VREFDQ DDR_B_D58
AM48 SA_DQ59 SM_VREF_DQ0 AP51 SA_DIMM_VREFDQ <18> AL18 SB_DQ58
DDR_B_D28 SB_DIMM_VREFDQ DDR_B_D59
DDR_B_D29 AK48 SA_DQ60 SM_VREF_DQ1 SB_DIMM_VREFDQ <19> DDR_B_D60 AK20 SB_DQ59
DDR_B_D30 AM51 SA_DQ61 DDR_B_D61 AM20 SB_DQ60
DDR_B_D31 AK51 SA_DQ62 DDR_B_D62 AR18 SB_DQ61
SA_DQ63 DDR_B_D63 AP18 SB_DQ62
SB_DQ63

A A

Broadwell-ULT_CL8064701614813_QFSY
3 OF 19 Broadwell-ULT_CL8064701614813_QFSY
4 OF 19

Security Classification LC Future Center Secret Data Title

Issued Date 2013/09/07 Deciphered Date 2014/09/07 BDW_DDR3L INT

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 6 of 81
5 4 3 2 1
 5 4 3 2 1

RTC External Circuit JCMOS, JME Setting, Need Under DDR Door RTC Crystal
+RTCBATT +RTCVCC +RTCVCC PCH_RTCX1
D JCMOS1 @ PCH_RTCX2 D
1 2 1 RC12 2 PCH_RTCRST# 1 2 1 RC13 2
RC11 0_0402_5%
20K_0402_5%
CC1 1 2 1U_0402_10V6-K 10M_0402_5% 1. Space > 15mils
1 2. No trace under crystal
CC2 YC1
+RTCBATT, +RTCVCC @ 1 2 3. Place on oppsosit side of
Trace width = 20mils 2
1U_0402_10V6-K
1 RC14 2 1
JME1 @
2
1 1 MCP for temp influence
PCH_SRTCRST# 32.768KHZ_12.5PF_9H03200042
CC3 CC4
20K_0402_5% 1 2 1U_0402_10V6-K 12P_0402_50V8-J 12P_0402_50V8-J
CC5
2 2

UC1E HSW_ULT_DDR3L

C C
+RTCVCC PCH_RTCX1 AW5
PCH_RTCX2 AY5 RTCX1
RC16 1 2 1M_0402_5% PCH_INTRUDER# AU6 RTCX2 J5 SATA_PRX_DTX_N0
INTRUDER SATA_RN0/PERN6_L3 SATA_PRX_DTX_N0 <37>
RC15 1 2 330K_0402_5% PCH_INTVRMEN AV7 H5 SATA_PRX_DTX_P0
INTVRMEN SATA_RP0/PERP6_L3 SATA_PRX_DTX_P0 <37>
PCH_SRTCRST# AV6 RTC B15 SATA_PTX_DRX_N0 HDD
SRTCRST SATA_TN0/PETN6_L3 SATA_PTX_DRX_N0 <37>
PCH_RTCRST# AU7 A15 SATA_PTX_DRX_P0 SATA_PTX_DRX_P0 <37>
RTCRST SATA_TP0/PETP6_L3
J8 SATA_PRX_DTX_N1
SATA_RN1/PERN6_L2 SATA_PRX_DTX_N1 <37>
H8 SATA_PRX_DTX_P1
SATA_RP1/PERP6_L2 SATA_PRX_DTX_P1 <37>
A17 SATA_PTX_DRX_N1 ODD, only for 15"
SATA_TN1/PETN6_L2 B17 SATA_PTX_DRX_N1 <37>
SATA_PTX_DRX_P1
SATA_TP1/PETP6_L2 SATA_PTX_DRX_P1 <37>
HDA_BCLK AW8 J6 SATA_PRX_DTX_N2
HDA_BCLK/I2S0_SCLK SATA_RN2/PERN6_L1 SATA_PRX_DTX_N2 <52>
HDA_SYNC AV11 H6 SATA_PRX_DTX_P2
HDA_SYNC/I2S0_SFRM SATA_RP2/PERP6_L1 SATA_PRX_DTX_P2 <52>
HDA_RST# AU8 B14 SATA_PTX_DRX_N2 SSD(NGFF)
AY10 HDA_RST/I2S_MCLK AUDIO SATA SATA_TN2/PETN6_L1 C15 SATA_PTX_DRX_N2 <52>
PCH_HDA_SDIN0 SATA_PTX_DRX_P2
<35> PCH_HDA_SDIN0 AU12 HDA_SDI0/I2S0_RXD SATA_TP2/PETP6_L1 SATA_PTX_DRX_P2 <52>
HDA_SDOUT AU11 HDA_SDI1/I2S1_RXD F5 PCIE6_CRX_DTX_N
HDA_SDO/I2S0_TXD SATA_RN3/PERN6_L0 PCIE6_CRX_DTX_N <32>
AW10 E5 PCIE6_CRX_DTX_P
HDA_DOCK_EN/I2S1_TXD SATA_RP3/PERP6_L0 PCIE6_CRX_DTX_P <32>
AV10 C17 PCIE6_CTX_DRX_N CC23 1 2 0.1U_0402_10V7-K PCIE6_CTX_C_DRX_N Card Reader
HDA_DOCK_RST/I2S1_SFRM SATA_TN3/PETN6_L0 PCIE6_CTX_C_DRX_N <32>
AY8 D17 PCIE6_CTX_DRX_P CC24 1 2 0.1U_0402_10V7-K PCIE6_CTX_C_DRX_P PCIE6_CTX_C_DRX_P <32>
I2S1_SCLK SATA_TP3/PETP6_L0

V1 PCH_GPIO34
SATA0GP/GPIO34 U1
SATA1GP/GPIO35
ODD_DETEC#
ODD_DETEC# <37> Only for 15"
V6 PCH_GPIO36
SATA2GP/GPIO36 AC1 EC_SCI#
SATA3GP/GPIO37 EC_SCI# <62>
1 PCH_JTAG_TRST# AU62
T8 1 PCH_JTAG_TCK AE62 PCH_TRST A12
T9 PCH_TCK SATA_IREF +1.05VS_PSATA3PLL
1 PCH_JTAG_TDI AD61 L11
T10 1 PCH_JTAG_TDO AE61 PCH_TDI RSVD3 K10 +3VS
B T11 1 AD62 PCH_TDO RSVD4 C12 1 2 B
PCH_JTAG_TMS JTAG SATACOMP RC22 3.01K_0402_1% +1.05VS_PSATA3PLL
T12 AL11 PCH_TMS SATA_RCOMP U3 RPC1
AC4 RSVD1 SATALED PCH_GPIO34 1 8
1 PCH_JTAGX AE63 RSVD2 PCH_GPIO36 2 7
T13 AV2 JTAGX SATACOMP ODD_DETEC# 3 6
RSVD0 EC_SCI# 4 5
SATA Impedance Compensation :
--> Place the resistor within 500 mils of the PCH. 10K_0804_8P4R_5%
Avoid routing next to clock pins.
Broadwell-ULT_CL8064701614813_QFSY
5 OF 19

RPC25
1 8 HDA_RST#
<35> PCH_HDA_RST# 2 7 HDA_BCLK
<35> PCH_HDA_BCLK 3 6 HDA_SDOUT
<35> PCH_HDA_SDOUT 4 5 HDA_SYNC
<35> PCH_HDA_SYNC
33_0804_8P4R_5%
SD30000370T

RC44 1 2 0_0402_5%
<62> ME_FLASH

A A

INTVRMEN

* HIntegrated VRM enable

1. INTVRMEN, should always be pull high
 Default Security Classification LC Future Center Secret Data Title
L Integrated VRM disable Issued Date 2013/09/07 Deciphered Date 2014/09/07 RTC/HDA/SATA/PCIe/JTAG
2. Internal Voltage Regulator Enable:
This signal enables the internal 1.05 V regulators. THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 7 of 81
5 4 3 2 1
 5 4 3 2 1

D D

HSW_ULT_DDR3L
UC1F

+3VS

RC29 1 DIS@ 2 10K_0402_5% C43 A25 PCH_XTAL24_IN PCH_XTAL24_IN

C42 CLKOUT_PCIE_N0 XTAL24_IN B25 PCH_XTAL24_OUT
1 UMA@ 2 10K_0402_5% DISCRETE_PRESENCE U2 CLKOUT_PCIE_P0 XTAL24_OUT PCH_XTAL24_OUT 1 RC30 2
RC32
PCIECLKRQ0/GPIO18 K21
B41 RSVD5 M21 1M_0402_5%
A41 CLKOUT_PCIE_N1 RSVD6 C26 DIFFCLK_BIASREF RC23 1 2 3.01K_0402_1% YC2
CLKOUT_PCIE_P1 DIFFCLK_BIASREF +1.05VS_PLPTCLKPLL
PCH_GPIO19 Y5
PCIECLKRQ1/GPIO19 C35 MCP_TESTLOW1 1 3
CLK_PCIE_WLAN# C41 CLOCK TESTLOW_C35 C34 MCP_TESTLOW2 1 3
<52> CLK_PCIE_WLAN#
CLK_PCIE_WLAN B42 CLKOUT_PCIE_N2 TESTLOW_C34 AK8 MCP_TESTLOW3
DIFFCLK_BIASREF GND1 GND2
<52> CLK_PCIE_WLAN CLKOUT_PCIE_P2 TESTLOW_AK8 Width=15mils, Space=12Mil, Length=500Mil 1 1
CLKREQ_PCIE2_WLAN# AD1 SIGNALS AL8 MCP_TESTLOW4
WLAN <52> CLKREQ_PCIE2_WLAN# PCIECLKRQ2/GPIO20 TESTLOW_AL8 2 4
CC6 CC7
CLK_PCIE_LAN# B38 AN15 PCH_PCI_CLK_R RC24 1 2 22_0402_5% 12P_0402_50V8-J 12P_0402_50V8-J
C <47> CLK_PCIE_LAN# C37 CLKOUT_PCIE_N3 CLKOUT_LPC_0 AP15 CLK_PCI_EC <62> 2 2 C
CLK_PCIE_LAN CLK_PCI_TPM_R RC25 1 TPM@ 2 22_0402_5%
<47> CLK_PCIE_LAN CLKREQ_PCIE3_LAN# N1 CLKOUT_PCIE_P3 CLKOUT_LPC_1 CLK_PCI_TPM <56>
LAN <47> CLKREQ_PCIE3_LAN# PCIECLKRQ3/GPIO21
24MHZ_10PF_8Y24000011
B35
CLK_PCIE_VGA# A39 CLKOUT_ITPXDP A35
<20> CLK_PCIE_VGA# CLK_PCIE_VGA B39 CLKOUT_PCIE_N4 CLKOUT_ITPXDP_P
<20> CLK_PCIE_VGA CLKREQ_PCIE4_VGA# U5 CLKOUT_PCIE_P4
VGA <20> CLKREQ_PCIE4_VGA# PCIECLKRQ4/GPIO22
CLK_PCIE_CR# B37
<32> CLK_PCIE_CR# CLK_PCIE_CR A37 CLKOUT_PCIE_N5
CR <32> CLK_PCIE_CR CLKOUT_PCIE_P5
CLKREQ_PCIE5_CR# T2
<32> CLKREQ_PCIE5_CR# PCIECLKRQ5/GPIO23

Broadwell-ULT_CL8064701614813_QFSY6 OF 19

+3VS RPC4
RPC2 MCP_TESTLOW3 1 8
1 8 CLKREQ_PCIE2_WLAN# MCP_TESTLOW4 2 7
2 7 CLKREQ_PCIE3_LAN# MCP_TESTLOW1 3 6
3 6 PCH_GPIO19 MCP_TESTLOW2 4 5
4 5 CLKREQ_PCIE5_CR#
10K_0804_8P4R_5%
10K_0804_8P4R_5%

B B

+3VS
UMA@
RC1651 2 10K_0402_5% CLKREQ_PCIE4_VGA#

RC1661 2 10K_0402_5%

DIS@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/09/07 Deciphered Date 2014/09/07 BDW_CLOCK/PM

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 8 of 81
5 4 3 2 1
 5 4 3 2 1

HSW_ULT_DDR3L
UC1G +3V_PCH
<56,62> LPC_AD[3:0] AU14 AN2 1 2
LPC_AD0 PCH_GPIO11 PCH_SML0_CLK RC92 499_0402_1%
D LPC_AD1 AW12 LAD0 SMBALERT/GPIO11 AP2 PCH_SMB_CLK PCH_SML0_DAT RC93 1 2 499_0402_1% D
EC and TPM Module debug port LPC_AD2 AY12 LAD1 LPC
SMBCLK AH1 PCH_SMB_DATA
LPC_AD3 AW11 LAD2 SMBUS SMBDATA AL2 PCH_GPIO60
LPC_FRAME# AV12 LAD3 SML0ALERT/GPIO60 AN1 PCH_SML0_CLK
Conn to RPC6.3 +3V_PCH
<56,62> LPC_FRAME# LFRAME SML0CLK PCH_SML0_CLK <47>
AK1 PCH_SML0_DAT RPC14
SML0DATA AU4 PCH_GPIO73
PCH_SML0_DAT <47> LAN PHY PCH_SMB_CLK 1 8
RPC23 SML1ALERT/PCHHOT/GPIO73 AU3 PCH_SML1CLK PCH_SMB_DATA 2 7
SPI_IO3_8MB 1 8 SPI_IO3 SPI_CLK SML1CLK/GPIO75 AH3 PCH_SML1DATA PCH_SML1CLK 3 6
SPI_CLK_8MB 2 7 SPI_CLK AA3 SML1DATA/GPIO74 PCH_SML1DATA 4 5
SPI_SI_8MB 3 6 SPI_SI SPI_CS0#_8MB Y7 SPI_CLK AF2 CL_CLK_WLAN
SPI_IO2_8MB 4 5 SPI_IO2 SPI_CS1#_4MB Y4 SPI_CS0 CL_CLK AD2 CL_DATA_WLAN CL_CLK_WLAN <52>
C-LINK 2.2K_0804_8P4R_5%
AC2 SPI_CS1 CL_DATA AF4 CL_RST_WLAN# CL_DATA_WLAN <52>
SPI C-LINK CL_RST_WLAN# <52>
33_0804_8P4R_5% SPI_SI AA2 SPI_CS2 CL_RST
SD30000370T SPI_SO_8MB RC100 1 2 33_0402_5% SPI_SO AA4 SPI_MOSI
SPI_SO_4MB RC101 1 2 33_0402_5% Y6 SPI_MISO RPC15
RPC24 VPRO@ AF1 SPI_IO2 PCH_GPIO11 1 8
SPI_IO3_4MB 1 8 SPI_IO3 +3V_SPI SPI_IO3 PCH_GPIO60 2 7
SPI_CLK_4MB 2 7 SPI_CLK PCH_GPIO73 3 6
SPI_SI_4MB 3 6 SPI_SI RC117 1 2 1K_0402_5% SPI_IO2 4 5
SPI_IO2_4MB 4 5 SPI_IO2 RC118 1 2 1K_0402_5% SPI_IO3
10K_0804_8P4R_5%
33_0804_8P4R_5% Broadwell-ULT_CL8064701614813_QFSY
7 OF 19 SD300002P0T
SD30000370T
VPRO@

Near UC4M1 and UC8M1

C C

Security ROM
+3VS
USROM1
1 8
2 NC_1 VCC 7
NC_2 WP 1
PLTRST#_NEAR 3 6 PM_SMB_CLK CC22
<10,32,47> PLTRST#_NEAR PROT# SCL
4 5 PM_SMB_DAT
GND SDA 0.1U_0402_10V6-K
PCA24S08AD_SO8 2
SA00004MK00/SA00004ML00
SM Bus
DIMM1, DIMM2,
WLAN(@), CP, Security ROM
Touch Panel
+3VS +3VS

M3 Support + Intel LAN PHY / Wireless LAN Solution RC106 1 2 4.7K_0402_5%

2
G
RC107 1 2 4.7K_0402_5%
+3V_SPI

RC110 1 @ 2 0_0402_5% +3V_SPI PCH_SMB_CLK 6 1 PM_SMB_CLK

+3VS

S
PM_SMB_CLK <18,19,49>

D
5
B QC1A B
0.085 A

G
RC112 1 2 0_0402_5% 2N7002KDWH_SOT363-6
+3VM +3V_SPI

PCH_SMB_DATA 3 4 PM_SMB_DAT

S
PM_SMB_DAT <18,19,49>

D
1
QC1B
UC8M1 CC25 +3V_SPI 2N7002KDWH_SOT363-6
SPI_CS0#_8MB 1 8 +3V_SPI 0.1U_0402_10V7-K UC4M1
CS# VCC 2 SPI_CS1#_4MB 1 8 +3V_SPI
CS# VCC 1
SPI_SO_8MB 2 7 SPI_IO3_8MB SPI_SO_4MB 2 7 SPI_IO3_4MB CC26
DO HOLD# SPI_IO2_4MB 3 DO HOLD# 6 SPI_CLK_4MB VPRO@
SPI_IO2_8MB 3 6 SPI_CLK_8MB 4 WP# CLK 5 SPI_SI_4MB 0.1U_0402_10V7-K
WP# CLK GND DI 2
4 5 SPI_SI_8MB W25Q32FVSSIQ_SO8 +3VS GPU, EC, Thermal Sensor
GND DI VPRO@

W25Q64FVSSIQ_SO8 2N7002KDWH

2
G
Vth= min 1V, max 2.5V
ESD 2KV
PCH_SML1CLK 6 1 EC_SMB_CK3

S
EC_SMB_CK3 <21,34,55,62>

D
5
QC2A

G
Mirror Code 2N7002KDWH_SOT363-6

RE19 1 2 0_0402_5% SPI_CS0#_8MB PCH_SML1DATA 3 4 EC_SMB_DA3

S
<62> FSCE# 1 2 EC_SMB_DA3 <21,34,55,62>
RE21 0_0402_5% SPI_SI_8MB

D
<62> SPI_FMOSI# 1 2
RE22 0_0402_5% SPI_SO_8MB QC2B
<62> SPI_FMISO 1 2 SPI_CLK_8MB
RE24 0_0402_5% 2N7002KDWH_SOT363-6
A <62> SPI_FSCK A

Close to SPI ROM (UC8M1).

Security Classification LC Future Center Secret Data Title

Issued Date 2013/09/07 Deciphered Date 2014/09/07 BDW_LPC/SPI/SM BUS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 9 of 81
5 4 3 2 1
 5 4 3 2 1

D D
RC43 2 1 0_0402_5% EC_RSMRST#

UC1H HSW_ULT_DDR3L RC52 1 @ 2 0_0402_5%

EC_DPWROK <62>
SYSTEM POWER MANAGEMENT +RTCVCC
+3VALW
RC37 1 @ 2 0_0402_5% SUSACK#_R AK2 AW7 DSWODVREN RC45 1 2 330K_0402_5%
<62> SUSACK# SYS_RESET# AC3 SUSACK DSWVRMEN AV5 EC_DPWROK_R 1 2 100K_0402_5%
RC33 @
PCH_SYSPWROK AG2 SYS_RESET RTC DPWROK AJ5 PCIE_WAKE#
<62> PCH_SYSPWROK 1 2 PWROK AY7 SYS_PWROK WAKE
RC41 0_0402_5% 1
<62> PCH_PWROK 1 2 AB5 PCH_PWROK RTC
RC42 0_0402_5% APWROK CC8
<78> PCH_APWROK PLTRST# AG7 APWROK V5 CLKRUN# CLKRUN# <56>
VPRO@ @
<20> PLTRST# PLTRST CLKRUN/GPIO32 AG4 1 @ 2
SUS_STAT# RC47 0_0402_5% 1U_0402_10V6-K
SUS_STAT/GPIO61 AE6 SUSCLK_32K LPC_PD# <56> 2
SUSCLK/GPIO62 AP5 PM_SLP_S5# SUSCLK_32K <52>
AW6 SLP_S5/GPIO63 PM_SLP_S5# <62>
EC_RSMRST#
<62> EC_RSMRST# 1 2 SUSWARN#_R AV4 RSMRST
RC39 @ 0_0402_5%
<62> SUSWARN# AL7 SUSWARN/SUSPWRDNACK/GPIO30 AJ6
PBTN_OUT# PM_SLP_S4#
<62> PBTN_OUT# AC_PRESENT AJ8 PWRBTN SLP_S4 AT4 PM_SLP_S3# PM_SLP_S4# <62>
<62> AC_PRESENT BATLOW# AN4 ACPRESENT/GPIO31 SLP_S3 AL5 PM_SLP_A# PM_SLP_S3# <62>
AF3 BATLOW/GPIO72 SLP_A AP4 PCH_SLP_SUS# PM_SLP_A# <62>
1 PCH_SLP_WLAN# AM5 SLP_S0 SLP_SUS AJ7 PCH_SLP_LAN# 1 PCH_SLP_SUS# <62>
T17 SLP_WLAN/GPIO29 SLP_LAN T18

1. must be always pulled-up to VCCRTC.

2. 1 = Enable DSW 3.3V-to-1.05V Integrated DeepSx Well DSW On-Die Voltage Regulator.
This must always be pulled high on production boards.
Broadwell-ULT_CL8064701614813_QFSY
8 OF 19
C C

+3VALW
UC3
+3VALW +3VS +3V_PCH 1 5
RPC18 NC VCC
1 8 AC_PRESENT RC108 1 2 10K_0402_5% SYS_RESET# RC49 1 @ 2 10K_0402_5% SUSWARN#_R PLTRST# 2
2 7 BATLOW# IN_A
3 6 PCIE_WAKE# RC51 1 2 8.2K_0402_5% CLKRUN# 3 4 RC48 1 2 33_0402_5%
1, 10K PU to VCCSUS Follow CRB GND OUT_Y PLTRST#_NEAR <32,47,9>

1
4 5 PCH_APWROK
2, No Need PU for Check List used as SUSWARN#
10K_0804_8P4R_5% * 3, Need PU for GPIO30 and not used RC26 TC7SG17FE_SON5
1
CC9
SD300002P0T 100K_0402_5%
100P_0402_50V8-J

2
2

RC50 1 2 33_0402_5%
PLTRST#_FAR <52,56,62>
1
CC82
RC27 1 2 10K_0402_5% EC_RSMRST# RC125 1 @ 2 PCH_APWROK
<14,62,70> 1.05VS_PGOOD
100P_0402_50V8-J
B RC28 1 @ 2 100K_0402_1% EC_DPWROK_R 10K_0402_5% 2 B

1
CC40
@
.01U_0402_16V7-K
2

RC109
SUSWARN#_R 1 2 SUSACK#_R
A SUSACK# and SUSWARN# can be tied together if EC does not want to involve in the A
0_0402_5% handshake mechanism for the Deep Sleep state entry and exit.

RC111
APWROK 1 2 PWROK
For platforms not supporting IntelR AMT it can be connected to PWROK.
0_0402_5% Title
Security Classification LC Future Center Secret Data
Issued Date 2013/09/07 Deciphered Date 2014/09/07 BDW_SYS PM
This signal can be tied to RSMRST# for platforms that do not support the Deep Sx state.
RSMRST# <--> DPWROK THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 10 of 81
5 4 3 2 1
 5 4 3 2 1

D D

籔 絋絋  絋絋
HSW_ULT_DDR3L
UC1I
1. VENDOR PU , Vih anf Vil
Τmeet SPEC value.
<38> PCH_EDP_PWM
PCH_EDP_PWM B8
EDP_BKLCTL DDPB_CTRLCLK
B9 PCH_MUX_CLK
PCH_MUX_CLK <42>
2. Vender fine tune recommend value.(Pass
A9 C9
<62> ENBKL
ENBKL
PCH_ENVDD C6 EDP_BKLEN eDP SIDEBAND DDPB_CTRLDATA D9
PCH_MUX_DAT
PCH_VGA_CLK PCH_MUX_DAT <42> Through Mode)
<38> PCH_ENVDD EDP_VDDEN DDPC_CTRLCLK
DDPC_CTRLDATA
D11 PCH_VGA_DAT 3. Vendor recommend use PU 4.7K ohm. (10/1)
Intel Spec is PU 2.2K ohm
From VGA_CORE IC PU TO +3VS DGPU_PWROK U6 +3VS
<29,76> DGPU_PWROK PIRQA/GPIO77
To VGA_CORE IC<20,29,72,76,77> VGA_ON VGA_ON P4 C5 PCH_MUX_AUX#
N4 PIRQB/GPIO78 DDPB_AUXN B6 PCH_MUX_AUX# <42>
DGPU_HOLD_RST# PCH_VGA_AUX#
<20> DGPU_HOLD_RST# BT_ON N2 PIRQC/GPIO79 DISPLAY DDPC_AUXN B5 PCH_MUX_AUX PCH_VGA_AUX# <43>
<52> BT_ON AD4 PIRQD/GPIO80 DDPB_AUXP A6 PCH_VGA_AUX PCH_MUX_AUX <42> PCH_MUX_CLK 1 2
RC115 4.7K_0402_5%
C PME PCIE DDPC_AUXP PCH_VGA_AUX <43> PCH_MUX_DAT 1 2 C
RC116 4.7K_0402_5%
PCH_TSOFF# U7
<51> PCH_TSOFF# FN_LED# L1 GPIO55
<51> FN_LED# L3 GPIO52 C8
F4_LED# PCH_MUX_HPD PCH_MUX_HPD <42>
<51> F4_LED# PLANARID3 R5 GPIO54 DDPB_HPD A8 PCH_VGA_HPD PCH_VGA_CLK 1 2 2.2K_0402_5%
<12> PLANARID3 PCH_VGA_HPD <43> RC31
F1_LED# L4 GPIO51 DDPC_HPD D6 CPU_EDP_HPD PCH_VGA_DAT RC40 1 2 2.2K_0402_5%
<51> F1_LED# GPIO53 EDP_HPD CPU_EDP_HPD <38>

PCH_MUX_HPD RC157 1 @ 2 100K_0402_5%

Broadwell-ULT_CL8064701614813_QFSY
9 OF 19
PCH_VGA_HPD RC158 1 2 100K_0402_5%
After testing, check if can un-stuff.
CPU_EDP_HPD RC159 1 2 100K_0402_5%

ENBKL RC156 1 2 100K_0402_5%

+3VS

RPC16
1 8 VGA_ON
2 7 DGPU_HOLD_RST#
3 6 BT_ON
4 5 CP_BYPASS CP_BYPASS <12,49>
10K_0804_8P4R_5%

B RPC17 B
1 8 PCH_TSOFF#
2 7 F4_LED#
3 6 F1_LED#
4 5 FN_LED#

10K_0804_8P4R_5%

1 UMA@ 2 DGPU_PWROK
RC85 10K_0402_5%

DDPB_CTRLDATA: Port B Detected

DDPC_CTRLDATA: Port C Detected

1: Port B or C is detected
A * 0: Port B or C is not detected A

Internal PD 15K~40K, nominal 20K

Security Classification LC Future Center Secret Data Title

Issued Date 2013/09/07 Deciphered Date 2014/09/07 BDW_eDP SBAND/DDPx

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 11 of 81
5 4 3 2 1
 5 4 3 2 1

+1.05VS_VCCST
UC1J HSW_ULT_DDR3L
THRMTRIP# RC53 1 2 1K_0402_1%
Intel recommend OPI_RCOMP PD 50 ohm 1%
RC54 1 @ 2
H_THERMTRIP# <21>
0_0402_5%
D PCH_GPIO76 P1 D60 THRMTRIP# D
RF_OFF# AU2 BMBUSY/GPIO76 THRMTRIP V4 KBRST#
<52> RF_OFF# LANPHYPC AM7 GPIO8 RCIN/GPIO82 T4 SERIRQ KBRST# <62>
<47> LANPHYPC PCH_GPIO15 AD6 LAN_PHY_PWR_CTRL/GPIO12 CPU/ SERIRQ AW15 SERIRQ <56,62>
ODD_EN Y1 GPIO15 MISC PCH_OPI_RCOMP AF20 OPI_RCOMP RC55 1 2 49.9_0402_1%
<37> ODD_EN T3 GPIO16 RSVD7 AB21
Only for 15" <37> ODD_DA#
ODD_DA#
GPIO17 RSVD8 OPI_RCOMP
PCH_GPIO24 AD5
EC_WAKE# RC167 1 @ 2 0_0402_5% DS_WAKE# AN5 GPIO24 Width 20Mil, Space 15Mil, Length 500Mil
PCH_GPIO28 AD7 GPIO27
RC168 1 @ 2 0_0402_5% PCH_GPIO26 AN3 GPIO28
<47> PCH_LAN_WAKE# GPIO26 R6 PCH_GPIO83
PCH_GPIO56 AG6 GSPI0_CS/GPIO83 L6 PCH_GPIO84
PCH_GPIO57 AP1 GPIO56 GSPI0_CLK/GPIO84 N6 PCH_GPIO85
PCH_GPIO58 AL4 GPIO57 GSPI0_MISO/GPIO85 L8 PCH_GPIO86
PCH_GPIO59 AT5 GPIO58 GSPI0_MOSI/GPIO86 R7 PCH_GPIO87
PCH_GPIO44 AK4 GPIO59 GPIO GSPI1_CS/GPIO87 L5 PCH_GPIO88
PCH_GPIO47 AB6 GPIO44 GSPI1_CLK/GPIO88 N7 PCH_GPIO89
PLANARID0 U4 GPIO47 GSPI1_MISO/GPIO89 K2 PCH_GPIO90
PLANARID1 Y3 GPIO48 GSPI_MOSI/GPIO90 J1 PCH_GPIO91
PLANARID2 P3 GPIO49 UART0_RXD/GPIO91 K3 CP_RESET#
Y2 GPIO50 UART0_TXD/GPIO92 J2 CP_RESET# <49>
CP_BYPASS
1 2 0_0402_5% EC_WAKE_R# AT3 HSIOPC/GPIO71 SERIAL IO UART0_RTS/GPIO93 G1 TP_REST CP_BYPASS <11,49>
RC169
<62> EC_WAKE# PCH_GPIO14 AH4 GPIO13 UART0_CTS/GPIO94 K4 PCH_GPIO0 TP_REST <49>
PCH_GPIO25 AM4 GPIO14 UART1_RXD/GPIO0 G2 PCH_GPIO1
PCH_GPIO45 AG5 GPIO25 UART1_TXD/GPIO1 J3 PCH_GPIO2
PCH_GPIO46 AG3 GPIO45 UART1_RST/GPIO2 J4 PCH_GPIO3
GPIO46 UART1_CTS/GPIO3 F2 WWAN_DET#
AM3 I2C0_SDA/GPIO4 F3 WWAN_DET# <52>
<34> ONEDOCK_DET# ONEDOCK_DET#
GPIO9 I2C0_SCL/GPIO5
WWAN_DISABLE#
WWAN_DISABLE# <52> Only for 15"
PCH_GPIO10 AM2 G4 PCH_GPIO6
DEVSLP0 P2 GPIO10 I2C1_SDA/GPIO6 F1 FW_GPIO
<37> DEVSLP0 PCH_GPIO70 C4 DEVSLP0/GPIO33 I2C1_SCL/GPIO7 E3 PCH_GPIO64 FW_GPIO <38>
Planar ID
DEVSLP1 L2 SDIO_POWER_EN/GPIO70 SDIO_CLK/GPIO64 F4 PCH_GPIO65
C <52> DEVSLP1 PCH_GPIO39 N5 DEVSLP1/GPIO38 SDIO_CMD/GPIO65 D3 PCH_GPIO66 PLANARID0 GPIO18 PLANARID2 PLANARID3 C
PCH_BEEP V2 DEVSLP2/GPIO39 SDIO_D0/GPIO66 E4 PCH_GPIO67 (GPIO48) (GPIO50) (GPIO51)
<36> PCH_BEEP SPKR/GPIO81 SDIO_D1/GPIO67 C3 PCH_CMOS_ON
PCH_CMOS_ON <38>
0 14" UMA HSW NA
SDIO_D2/GPIO68 E2 PCH_GPIO69
SDIO_D3/GPIO69
1 15" OPT BDW PU
10 OF 19 * * +3VS
Broadwell-ULT_CL8064701614813_QFSY

SATA Port

1
DEVSLP0 SATA Port 0

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%
RC67 RC68 RC69 RC70
DEVSLP1 SATA Port 1 BDW@ 15NM@

2
PLANARID0

PLANARID1

PLANARID2

<11> PLANARID3

1
10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%
RC71 RC72 RC73 RC74
+3VALW +3V_PCH +3VS +3VS @ HSW@ @ 14NM@

RPC5 RPC8 RPC20

2
1 2 PCH_GPIO25 8 1 PCH_GPIO59 8 1 ODD_DA# 8 1 PCH_GPIO91
RC90 10K_0402_5% 7 2 PCH_GPIO56 7 2 PCH_GPIO83 7 2 PCH_GPIO84
1 2 DS_WAKE# 6 3 PCH_GPIO47 6 3 PCH_GPIO69 6 3 PCH_GPIO87
RC91 10K_0402_5% 5 4 PCH_GPIO44 5 4 PCH_GPIO89 5 4 PCH_GPIO88
B B
GPIO15, Internal PD
10K_0804_8P4R_5% 10K_0804_8P4R_5% 10K_0804_8P4R_5% 1: INTEL ME TLS W Confidentiality
RPC6 0: INTEL ME TLS WO Confidentiality
8 1 PCH_GPIO58 RPC9 RPC21
7 2 PCH_GPIO57 8 1 PCH_GPIO76 8 1 SERIRQ +3V_PCH
6 3 PCH_GPIO10 7 2 ODD_EN 7 2 KBRST#
5 4 ONEDOCK_DET# 6 3 PCH_GPIO6 6 3 WWAN_DET# PCH_GPIO15 2 1
5 4 WWAN_DISABLE# 5 4 PCH_GPIO39 RC75 1K_0402_5%
10K_0804_8P4R_5%
10K_0804_8P4R_5% 10K_0804_8P4R_5% GPIO66, Internal 20K PD
RPC7 1: Top-Block Swap Override EN
8 1 RF_OFF# RPC10 *0: Disable
7 2 PCH_GPIO46 8 1 FW_GPIO 1 2 DEVSLP0 +3VS
6 3 EC_WAKE_R# 7 2 PCH_GPIO70 RC83 10K_0402_5%
5 4 PCH_GPIO26 6 3 PCH_GPIO90 1 2 DEVSLP1 PCH_GPIO66 2 @ 1
5 4 PCH_CMOS_ON RC84 10K_0402_5% RC76 1K_0402_5%
10K_0804_8P4R_5%
10K_0804_8P4R_5% GPIO81, No Reboot, Internal PD
1: Enabled No Reboot Mode
RPC19 RPC11 *0: Disable No Reboot Mode
8 1 PCH_GPIO24 8 1 PCH_GPIO1 +3VS
7 2 PCH_GPIO28 7 2 PCH_GPIO2
6 3 PCH_GPIO14 6 3 PCH_GPIO3 PCH_BEEP 2 @ 1
5 4 PCH_GPIO45 5 4 PCH_GPIO0 RC77 1K_0402_5%

10K_0804_8P4R_5% 4.7K_0804_8P4R_5% GPIO86, Internal PD

1: Enabled
RPC12 *0: SPI ROM +3VS
8 1 PCH_GPIO64
7 2 PCH_GPIO65
6 3 PCH_GPIO67 PCH_GPIO86 2 @ 1
5 4 PCH_GPIO85 RC80 1K_0402_5%
A 2 1 A
10K_0804_8P4R_5% RC82 1K_0402_5%

2013/08/29 Set Nactive and Pull Down

Security Classification LC Future Center Secret Data Title

Issued Date 2013/09/07 Deciphered Date 2014/09/07 BDW_GPIO/SIO

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 12 of 81
5 4 3 2 1
 5 4 3 2 1

D D

UC1K HSW_ULT_DDR3L

PCIE_CRX_GTX_N0 F10 AN8 USB20_N0

<20> PCIE_CRX_GTX_N0 PERN5_L0 USB2N0 USB20_N0 <40>
PCIE_CRX_GTX_P0 E10 AM8 USB20_P0
<20> PCIE_CRX_GTX_P0 PERP5_L0 USB2P0 USB20_P0 <40> On Board Back
CC10 DIS@ 1 2 0.1U_0402_10V7-K PCIE5_PTX_DRX_N0 C23 AR7 USB20_N1
<20> PCIE_CTX_C_GRX_N0 PETN5_L0 USB2N1 USB20_N1 <41>
CC11 DIS@ 1 2 0.1U_0402_10V7-K PCIE5_PTX_DRX_P0 C22 AT7 USB20_P1
On Board /Charge Port Front
C <20> PCIE_CTX_C_GRX_P0 PETP5_L0 USB2P1 USB20_P1 <41> C
PCIE_CRX_GTX_N1 F8 AR8 USB20_N2
<20> PCIE_CRX_GTX_N1 PERN5_L1 USB2N2 USB20_N2 <34>
PCIE_CRX_GTX_P1 E8 AP8 USB20_P2
<20> PCIE_CRX_GTX_P1 PERP5_L1 USB2P2 USB20_P2 <34> Sub/B
CC12 DIS@ 1 2 0.1U_0402_10V7-K PCIE5_PTX_DRX_N1 B23 AR10 USB20_N3
<20> PCIE_CTX_C_GRX_N1 PETN5_L1 USB2N3 USB20_N3 <34>
CC13 DIS@ 1 2 0.1U_0402_10V7-K PCIE5_PTX_DRX_P1 A23 AT10 USB20_P3
DOCKING
<20> PCIE_CTX_C_GRX_P1 PETP5_L1 USB2P3 USB20_P3 <34>
PCIE_CRX_GTX_N2 H10 AM15 USB20_N4
<20> PCIE_CRX_GTX_N2 PERN5_L2 USB2N4
PCIE_CRX_GTX_P2 G10 AL15 USB20_P4
GPU <20> PCIE_CRX_GTX_P2 PERP5_L2 USB2P4 TOUCH PANEL/WWAN
CC14 DIS@ 1 2 0.1U_0402_10V7-K PCIE5_PTX_DRX_N2 B21 AM13 USB20_N5
<20> PCIE_CTX_C_GRX_N2 PETN5_L2 USB2N5 USB20_N5 <50>
CC15 DIS@ 1 2 0.1U_0402_10V7-K PCIE5_PTX_DRX_P2 C21 AN13 USB20_P5
FPR
<20> PCIE_CTX_C_GRX_P2 PETP5_L2 USB2P5 USB20_P5 <50>
PCIE_CRX_GTX_N3 E6 AP11 USB20_N6
<20> PCIE_CRX_GTX_N3 PERN5_L3 USB2N6 USB20_N6 <52>
PCIE_CRX_GTX_P3 F6 AN11 USB20_P6
<20> PCIE_CRX_GTX_P3 PERP5_L3 USB2P6 USB20_P6 <52> BT
CC16 DIS@ 1 2 0.1U_0402_10V7-K PCIE5_PTX_DRX_N3 B22 AR13 USB20_N7
<20> PCIE_CTX_C_GRX_N3 PETN5_L3 USB2N7 USB20_N7 <38>
CC17 DIS@ 1 2 0.1U_0402_10V7-K PCIE5_PTX_DRX_P3 A21 AP13 USB20_P7
CAMERA
<20> PCIE_CTX_C_GRX_P3 PETP5_L3 USB2P7 USB20_P7 <38>
PCIE3_CRX_DTX_N G11
<52> PCIE3_CRX_DTX_N PERN3
PCIE3_CRX_DTX_P F11 G20 USB3P1_RXN
<52> PCIE3_CRX_DTX_P PERP3 USB3RN1 USB3P1_RXN <40>
H20 USB3P1_RXP
WLAN <52> PCIE3_CTX_C_DRX_N
CC18 1 2 0.1U_0402_10V7-K PCIE3_CTX_DRX_N C29
PETN3 PCIE USB
USB3RP1 USB3P1_RXP <40>
On Board Back
CC19 1 2 0.1U_0402_10V7-K PCIE3_CTX_DRX_P B30 C33 USB3P1_TXN
<52> PCIE3_CTX_C_DRX_P PETP3 USB3TN1 B34 USB3P1_TXP USB3P1_TXN <40>
PCIE4_CRX_DTX_N F13 USB3TP1 USB3P1_TXP <40>
<47> PCIE4_CRX_DTX_N PERN4
PCIE4_CRX_DTX_P G13 E18 USB3P2_RXN
LAN <47> PCIE4_CRX_DTX_P PERP4 USB3RN2
USB3RP2
F18 USB3P2_RXP
USB3P2_RXN
USB3P2_RXP
<41>
<41>
CC20 1 2 0.1U_0402_10V7-K PCIE4_CTX_DRX_N B29
<47> PCIE4_CTX_C_DRX_N
CC21 1 2 0.1U_0402_10V7-K PCIE4_CTX_DRX_P A29 PETN4 B33 USB3P2_TXN
On Board Front
<47> PCIE4_CTX_C_DRX_P PETP4 USB3TN2 A33 USB3P2_TXP USB3P2_TXN <41>
USB3P3_RXN G17 USB3TP2 USB3P2_TXP <41>
B <38> USB3P3_RXN PERN1/USB3RN3 B
USB3P3_RXP F17
<38> USB3P3_RXP PERP1/USB3RP3
3D CCD <38> USB3P3_TXN
USB3P3_TXN C30
PETN1/USB3TN3 USBRBIAS/USBRBIAS#
USB3P3_TXP C31 AJ10 RC81
<38> USB3P3_TXP PETP1/USB3TP3 USBRBIAS AJ11 USBRBIAS 1 2 1. trace length and no longer than 450 mils to resistor.
USB3P4_RXN F15 USBRBIAS AN10 2. Avoid routing next to clock pins or under stitching capacitors.
<34> USB3P4_RXN
USB3P4_RXP G15 PERN2/USB3RN4 RSVD11 AM10
<450mils 22.6_0402_1%
<34> USB3P4_RXP PERP2/USB3RP4 RSVD12 Recommended minimum spacing to other signal traces is 15 mils (0.381 mm).
DOCKNG <34> USB3P4_TXN
USB3P4_TXN B31
PETN2/USB3TN4
USB3P4_TXP A31
<34> USB3P4_TXP PETP2/USB3TP4 AL3 USB_OC0#
OC0/GPIO40 AT1 USB_OC1#
USB_OC0# <41> On Board Front Charger Port
OC1/GPIO41 AH2 USB_OC2# USB_OC1# <40> On Board Back
+1.05VS_PUSB3PLL E15 OC2/GPIO42 AV3 USB_OC3# USB_OC2# <34> Docking board USB2
E13 RSVD9 OC3/GPIO43
RC87 1 2 3K_0402_1% PCIE_RCOMP A27 RSVD10
B27 PCIE_RCOMP
PCIE_IREF

PCIE_RCOMP&PCIE_IREF (Shared with DMI)

Width 20Mil, Space 15Mil, Length 500Mil USB3.0 Port NO. USB2.0 Port NO. +3V_PCH
Broadwell-ULT_CL8064701614813_QFSY
11 OF 19 USB_OC0# Port 2 Port 1 RPC13
USB_OC0# 1 8
USB_OC1# 2 7
USB_OC1# Port 1 Port 0 USB_OC2# 3 6
USB_OC3# 4 5
USB_OC2# Unused. Port 2
USB_OC3# Unused. Unused. 10K_0804_8P4R_5%
USB20_N4 RC34 1 2 0_0402_5%
USB20_N4_TPANEL <51>
USB20_P4 RC35 1 2 0_0402_5%
USB20_P4_TPANEL <51>

A RC36 1 2 3G@ 0_0402_5% A

1 2 3G@ 0_0402_5% USB20_N4_WWAN <52>
RC38
USB20_P4_WWAN <52>

Close to device side

Security Classification LC Future Center Secret Data Title

Issued Date 2013/09/07 Deciphered Date 2014/09/07 BDW_PCIE/USB BUS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 13 of 81
5 4 3 2 1
 5 4 3 2 1

Haswell MCP (Power)

+1.05VS +1.05VS_VCCST +1.35V

+VCC_CORE
UC1L HSW_ULT_DDR3L
RC119
1 2 30.5A +1.35V
L59 C36
0_0603_5% J58 RSVD13 VCC8 C40
RSVD14 VCC9 C44
+VCC_CORE 1.4A VCC10
AH26 C48
D AJ31 VDDQ1 VCC11 C52 D
AJ33 VDDQ2 VCC12 C56
VDDQ3 VCC13

330U_D2_2V_Y
AJ37 E23 1@ @
VDDQ4 VCC14

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M
AN33 E25 1 1 1 1 1@ 1@ 1 1 1 1
VDDQ5 VCC15

CC83

CC27

CC28

CC29

CC30
+VCC_CORE AP43 E27 +
VDDQ6 VCC16

CC31

CC32

CC33

CC34

CC35

CC36
AR48 E29
AY35 VDDQ7 VCC17 E31
VDDQ8 VCC18

1
AY40 E33 2 2 2 2 2 2 2 2 2 2 2
RC120 AY44 VDDQ9 VCC19 E35
AY50 VDDQ10 VCC20 E37
VDDQ11 VCC21 E39
100_0402_1% 0.5A VCC22
F59 E41
2 N58 VCC1 VCC23 E43
AC58 RSVD15 VCC24 E45
RSVD16 VCC25 E47
RC121 2 1 0_0402_5% E63 VCC26 E49
<73> VCCSENSE 1 AB23 VCC_SENSE VCC27 E51
TP28 A59 RSVD17 VCC28 E53
+VCCIO_OUT VCCIO_OUT VCC29
E20 E55
+VCCIOA_OUT VCCIOA_OUT VCC30
AD23 E57
AA23 RSVD18 VCC31 F24
RSVD19 VCC32
HW 4PCS 2.2UF CAP Mounted
AE59 F28 HW 6PCS 10UF CAP Mounted
RSVD20 VCC33 F32
VR_SVID_ALRT#_R L62 VCC34 F36
PWR 2PCS 470U Near VR Output
VR_SVID_CLK N63 VIDALERT HSW ULT POWER VCC35 F40
<73> VR_SVID_CLK L63 VIDSCLK VCC36 F44
VR_SVID_DAT VCC_SENSE
VCCST_PWRGD B59 VIDSOUT VCC37 F48
VCCST_PWRGD VCC38
Length Match: No More Than 25Mil
VR_ON F60 F52 Space: More Than 25Mil
<73> VR_ON C59 VR_EN Out VCC39 F56
VGATE
<73> VGATE VR_READY In 1.05V VCC40 G23 GND Reference
D63 VCC41 G25
1 2 150_0402_1% PWR_DEBUG H59 VSS344 VCC42 G27
C +1.05VS_VCCST RC122
PWR_DEBUG VCC43 SVID C
P62 G29
1 P60 VSS345 VCC44 G31
TP6 RSVD_TP1 VCC45
1, Stripline Line, No More Than 6000Mil
1 P61 G33 2, Alert# Route Between CLK and Data
TP7 1 N59 RSVD_TP2 VCC46 G35
TP8 1 N61 RSVD_TP3 VCC47 G37
3, CLK Length<Data Length<CLK Length + 2000Mil
TP9 T59 RSVD_TP4 VCC48 G39 4, Space at least 18Mil
AD60 RSVD21 VCC49 G41
AD59 RSVD22 VCC50 G43
AA59 RSVD23 VCC51 G45
AE60 RSVD24 VCC52 G47
AC59 RSVD25 VCC53 G49
RSVD26 VCC54 +VCC_CORE[1..68] 32A
AG58 G51
+1.05VS_VCCST U59 RSVD27 VCC55 G53
V59 RSVD28 VCC56 G55
RSVD29 VCC57 G57
0.1A VCC58
AC22 H23 +1.05VS_VCCST[1..3] 0.1A
AE22 VCCST1 VCC59 J23
VCCST2 VCC60
22U_0603_6.3V6-M

+VCC_CORE AE23 K23

VCCST3 VCC61
1U_0402_6.3VA-K

1@ 1@ 3A K57
AB57 VCC62 L22
VCC2 VCC63
CC37

CC38

AD57 M23 VDDQ[1..11] 1.4A

AG57 VCC3 VCC64 M57
2 2 C24 VCC4 VCC65 P57
C28 VCC5 VCC66 U57
C32 VCC6 VCC67 W57
VCC7 VCC68
12 OF 19
Broadwell-ULT_CL8064701614813_QFSY

SVID ALERT
B +1.05VS_VCCST B

+1.05VS_VCCST
Place the PU

2
RC161
resistors close to CPU
1

75_0402_1%
RC124 DC1
0_0402_5% RC123

1
RB521CS-30GT2RA_VMN2-2 10K_0402_5%
1 2 1 2 RC162
2

<62> VCCST_PG_EC VR_SVID_ALRT# 1 2 VR_SVID_ALRT#_R

1 2 VCCST_PWRGD <73> VR_SVID_ALRT#
RC126 @ 0_0402_5%
<10,62,70> 1.05VS_PGOOD
43_0402_1%

SVID DATA
+1.05VS_VCCST

Place the PU

1
RC163
130_0402_1%
resistors close to CPU

2
A VR_SVID_DAT A
<73> VR_SVID_DAT

Security Classification LC Future Center Secret Data Title

Issued Date 2013/09/07 Deciphered Date 2014/09/07 XXXX

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 14 of 81
5 4 3 2 1
 5 4 3 2 1

Haswell MCP (Power2)

+1.05VS +1.05VS
+1.05VS_PLPTVCC1P05 +1.05VS_PUSB3PLL
RC127 1 @ 2 0_0402_5% VCCDSW3_3 +1.05VM_PCH_VCCASW
+3VL
1 2 LC1 1 2 LC4 +3VS RC130 1 @ 2 0_0402_5% +3VM_VCCSPI
2.2UH_LQM21PN2R2MC0D 2.2UH_LQM21PN2R2MC0D RC131 1 2 0_0402_5%
+1.05VS
RC132 1 2 0_0402_5%
+3VALW 0.67 A
+1.05VS_PLPTCLKPLL +1.05VS_PSATA3PLL RC133 1 2 0_0402_5% RC134 1 @ 2 0_0603_5%
+3VM +1.05VM
1 2 LC2 1 2 LC5
2.2UH_LQM21PN2R2MC0D 2.2UH_LQM21PN2R2MC0D

+1.05VS_POPIPLL
D D
1 2 LC3
2.2UH_LQM21PN2R2MC0D

UC1M HSW_ULT_DDR3L

+1.05VS K9
L10 VCCHSIO[1]
M9 VCCHSIO[2]
VCCHSIO 1.838A +1.05VS_PUSB3PLL 41mA VCCHSIO[3]
N8 HSIO RTC AH11
+1.05VS_POPIPLL 57mA VCC1_05[1] VCCSUS3_3[5] +3V_PCH
+1.05VS +1.05VS +1.05VS_PUSB3PLL P9 AG10
VCC1_05[2] VCCRTC +RTCVCC
+1.05VS_POPIPLL +1.05VS_PUSB3PLL B18 AE7 +DCPRTC
B11 VCCUSB3PLL DCPRTC
+1.05VS_PSATA3PLL VCCSATA3PLL

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

100U_1206_6.3V6-M
@
10U_0603_6.3V6-M

1U_0402_10V6-K

1U_0402_10V6-K

100U_1206_6.3V6-M

1U_0402_10V6-K
1U_0402_10V6-K

1 Y20 SPI Y8 +3VM_VCCSPI

1 1 1 1 1 1 1 1 TP10 RSVD30 VCCSPI

CC48

CC43

CC84
1@ 1 +1.05VS_POPIPLL AA21 OPI
VCCAPLL[1]
CC39

CC46

CC47

CC44

CC45
W21
VCCAPLL[2]
CC41

CC42

AG14 VCCASW[1:5] 658mA

2 2 2 2 2 2 2 2 VCCASW[1] AG13
2 2
VCCHDA 11mA VCCASW[2] +1.05VM_PCH_VCCASW
+1.05VS_DCPSUS3 J13 USB3
DCPSUS3 J11
VCC1_05[3] +1.05VS
CRB 100uF x1+1uF x1 H11
AH14 HDA VCC1_05[4] H15
CRB 100uF x1+1uF x1 PDG 1uF x2 +3V_PCH VCCHDA VCC1_05[5]
Close J11 H11 H15 PDG 1uF x1 Close K9 ,L10 ,M9 AE8
VCC1_05[6] AF22
Close B18 and B11 VCC1_05[7]
+1.05VS_DCPSUS2 AH13 VRM AG19 +PCH_DCPSUSBYP
Close AA21 DCPSUS2 DCPSUSBYP[1]
CORE AG20
DCPSUSBYP[2] AE9
VCCASW[3] +1.05VM_PCH_VCCASW
AF9
AC9 VCCASW[4] AG8
AA9 VCCSUS3_3[1] GPIO/LPC
VCCASW[5] AD10 +1.05VS_DCPSUS1
+3V_PCH VCCSUS3_3[2] DCPSUS1[1]
+1.05VS_PLPTCLKPLL 31mA +1.05VS_PLPTVCC1P05 185mA +1.05VS_PSATA3PLL 42mA VCCDSW3_3 AH10 AD8
V8 VCCDSW3_3 DCPSUS1[2]
+3VS VCC3_3[1]
+1.05VS +1.05VS_PLPTCLKPLL +1.05VS +1.05VS_PLPTVCC1P05 +1.05VS_PSATA3PLL W9 VCCTS1_5 3mA
VCC3_3[2] J15
C +1.5VS C
THERMAL SENSOR VCCTS1_5 K14
VCC3_3[3] +3VS
K16
VCC3_3[4]
1U_0402_10V6-K

100U_1206_6.3V6-M

100U_1206_6.3V6-M

100U_1206_6.3V6-M

2.2U_0402_6.3V6-K
1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K
1 1 1 1 1 1 1 1 1
+1.05VS_PLPTVCC1P05 J18
VCCCLK[1]
CC53

CC54

CC55

CC56

CC57

CC59

CC60

CC62
CC51 K19 SERIAL IO U8
VCCCLK[2] VCCSDIO[1] +3VS
+1.05VS_PLPTCLKPLL A20 T9
2 2 2 2 2 2 2 2 2 J17 VCCACLKPLL VCCSDIO[2]
+1.05VS VCCCLK[3]
R21
T21 VCCCLK[4] LPT LP POWER
1 K18 VCCCLK[5] SUS OSCILLATOR AB8 +1.05VS_DCPSUS4
TP11 RSVD31 DCPSUS4
CRB 100uF x1+1uF x1 CRB 100uF x1+1uF x1 1 M20
TP12 RSVD32
Close AG16 PDG 1uF x2 PDG 1uF x3 VCCSUS3_3[1:5] 65mA 1 V21
TP13 AE20 RSVD33 AC20 1
Close A20 Close J17 R21 Close J18,J17 Close B11 +3V_PCH VCCSUS3_3[3] RSVD34 T14
AE21 AG16 +1.05VS
VCCSUS3_3[4] USB2 VCC1_05[8] AG17
VCC1_05[9]

13 OF 19
Broadwell-ULT_CL8064701614813_QFSY
+3V_PCH +3V_PCH +3V_PCH
1U_0402_10V6-K

22U_0603_6.3V6-M

1U_0402_10V6-K

1 1 1
CC63

CC64

CC65

2 2 2
DCPSUS[4:1]

+1.05VS_DCPSUS4 +1.05VS_DCPSUS3 +1.05VS_DCPSUS2 +1.05VS_DCPSUS1

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K
B
Close AH14 Close AC9 Close AH11 B
1 1 1 1
@ @ @ @
CC66 CC67 CC68 CC69
2 2 2 2
VCC3_3[1:4] 41mA VCCSDIO 17mA
+RTCVCC
+3VS +3VS +3VS VCCDSW 114mA
VCCDSW3_3 Close AB8 Close J13 Close AH13 Close AD10,AD8
0.1U_0402_10V6-K

22U_0603_6.3V6-M

1U_0402_10V6-K

1U_0402_10V6-K

0.1U_0402_10V6-K

0.1U_0402_10V6-K

1U_0402_10V6-K

1 1 1@
1 1 1 1
CC73

CC74

CC75

@
CC70 CC71 CC72 CC76
2 2 2
2 2 2 2

Close K14,K16 Close V8,W9 Close U8,T9 Close AG10 Close AH10

VCCSPI 18mA
+3VM_VCCSPI +1.05VM_PCH_VCCASW +DCPRTC +PCH_DCPSUSBYP
0.1U_0402_10V6-K

0.1U_0402_10V6-K

1U_0402_10V6-K

1
22U_0603_6.3V6-M

@ 1 1
1U_0402_10V6-K

CC78 1 1
CC77

CC80 CC81
2
CC79

A 2 2 A
2 2

Close Y8 Close AE9 AF9 AG8 Close AE7 Close AG19

Security Classification LC Future Center Secret Data Title

Issued Date 2013/09/07 Deciphered Date 2014/09/07 XXXX

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 15 of 81
5 4 3 2 1
 5 4 3 2 1

Haswell MCP (VSS)

D D

UC1N HSW_ULT_DDR3L UC1O HSW_ULT_DDR3L UC1P HSW_ULT_DDR3L

H17
A11 AJ35 AP22 AV59 D33 VSS300 H57
A14 VSS1 VSS65 AJ39 AP23 VSS129 VSS193 AV8 D34 VSS257 VSS301 J10
A18 VSS2 VSS66 AJ41 AP26 VSS130 VSS194 AW16 D35 VSS258 VSS302 J22
A24 VSS3 VSS67 AJ43 AP29 VSS131 VSS195 AW24 D37 VSS259 VSS303 J59
A28 VSS4 VSS68 AJ45 AP3 VSS132 VSS196 AW33 D38 VSS260 VSS304 J63
A32 VSS5 VSS69 AJ47 AP31 VSS133 VSS197 AW35 D39 VSS261 VSS305 K1
A36 VSS6 VSS70 AJ50 AP38 VSS134 VSS198 AW37 D41 VSS262 VSS306 K12
A40 VSS7 VSS71 AJ52 AP39 VSS135 VSS199 AW4 D42 VSS263 VSS307 L13
A44 VSS8 VSS72 AJ54 AP48 VSS136 VSS200 AW40 D43 VSS264 VSS308 L15
A48 VSS9 VSS73 AJ56 AP52 VSS137 VSS201 AW42 D45 VSS265 VSS309 L17
A52 VSS10 VSS74 AJ58 AP54 VSS138 VSS202 AW44 D46 VSS266 VSS310 L18
A56 VSS11 VSS75 AJ60 AP57 VSS139 VSS203 AW47 D47 VSS267 VSS311 L20
AA1 VSS12 VSS76 AJ63 AR11 VSS140 VSS204 AW50 D49 VSS268 VSS312 L58
AA58 VSS13 VSS77 AK23 AR15 VSS141 VSS205 AW51 D5 VSS269 VSS313 L61
AB10 VSS14 VSS78 AK3 AR17 VSS142 VSS206 AW59 D50 VSS270 VSS314 L7
AB20 VSS15 VSS79 AK52 AR23 VSS143 VSS207 AW60 D51 VSS271 VSS315 M22
AB22 VSS16 VSS80 AL10 AR31 VSS144 VSS208 AY11 D53 VSS272 VSS316 N10
AB7 VSS17 VSS81 AL13 AR33 VSS145 VSS209 AY16 D54 VSS273 VSS317 N3
C AC61 VSS18 VSS82 AL17 AR39 VSS146 VSS210 AY18 D55 VSS274 VSS318 P59 C
AD21 VSS19 VSS83 AL20 AR43 VSS147 VSS211 AY22 D57 VSS275 VSS319 P63
AD3 VSS20 VSS84 AL22 AR49 VSS148 VSS212 AY24 D59 VSS276 VSS320 R10
AD63 VSS21 VSS85 AL23 AR5 VSS149 VSS213 AY26 D62 VSS277 VSS321 R22
AE10 VSS22 VSS86 AL26 AR52 VSS150 VSS214 AY30 D8 VSS278 VSS322 R8
AE5 VSS23 VSS87 AL29 AT13 VSS151 VSS215 AY33 E11 VSS279 VSS323 T1
AE58 VSS24 VSS88 AL31 AT35 VSS152 VSS216 AY4 E17 VSS280 VSS324 T58
AF11 VSS25 VSS89 AL33 AT37 VSS153 VSS217 AY51 F20 VSS281 VSS325 U20
AF12 VSS26 VSS90 AL36 AT40 VSS154 VSS218 AY53 F26 VSS282 VSS326 U22
AF14 VSS27 VSS91 AL39 AT42 VSS155 VSS219 AY57 F30 VSS283 VSS327 U61
AF15 VSS28 VSS92 AL40 AT43 VSS156 VSS220 AY59 F34 VSS284 VSS328 U9
AF17 VSS29 VSS93 AL45 AT46 VSS157 VSS221 AY6 F38 VSS285 VSS329 V10
AF18 VSS30 VSS94 AL46 AT49 VSS158 VSS222 B20 F42 VSS286 VSS330 V3
AG1 VSS31 VSS95 AL51 AT61 VSS159 VSS223 B24 F46 VSS287 VSS331 V7
AG11 VSS32 VSS96 AL52 AT62 VSS160 VSS224 B26 F50 VSS288 VSS332 W20
AG21 VSS33 VSS97 AL54 AT63 VSS161 VSS225 B28 F54 VSS289 VSS333 W22
AG23 VSS34 VSS98 AL57 AU1 VSS162 VSS226 B32 F58 VSS290 VSS334 Y10
AG60 VSS35 VSS99 AL60 AU16 VSS163 VSS227 B36 F61 VSS291 VSS335 Y59
AG61 VSS36 VSS100 AL61 AU18 VSS164 VSS228 B4 G18 VSS292 VSS336 Y63
AG62 VSS37 VSS101 AM1 AU20 VSS165 VSS229 B40 G22 VSS293 VSS337
AG63 VSS38 VSS102 AM17 AU22 VSS166 VSS230 B44 G3 VSS294
AH17 VSS39 VSS103 AM23 AU24 VSS167 VSS231 B48 G5 VSS295 V58
AH19 VSS40 VSS104 AM31 AU26 VSS168 VSS232 B52 G6 VSS296 VSS338 AH46
AH20 VSS41 VSS105 AM52 AU28 VSS169 VSS233 B56 G8 VSS297 VSS339 V23
AH22 VSS42 VSS106 AN17 AU30 VSS170 VSS234 B60 H13 VSS298 VSS340 E62 RC142 1 2 0_0402_5%
AH24 VSS43 VSS107 AN23 AU33 VSS171 VSS235 C11 VSS299 VSS_SENSE AH16 VSSSENSE <73>
VSS44 VSS108 VSS172 VSS236 VSS341

1
AH28 AN31 AU51 C14 16 OF 19
AH30 VSS45 VSS109 AN32 AU53 VSS173 VSS237 C18 Broadwell-ULT_CL8064701614813_QFSY
AH32 VSS46 VSS110 AN35 AU55 VSS174 VSS238 C20 RC143
AH34 VSS47 VSS111 AN36 AU57 VSS175 VSS239 C25 QFSY@ 100_0402_1%
AH36 VSS48 VSS112 AN39 AU59 VSS176 VSS240 C27

2
AH38 VSS49 VSS113 AN40 AV14 VSS177 VSS241 C38
B AH40 VSS50 VSS114 AN42 AV16 VSS178 VSS242 C39 B
AH42 VSS51 VSS115 AN43 AV20 VSS179 VSS243 C57
AH44 VSS52 VSS116 AN45 AV24 VSS180 VSS244 D12
AH49 VSS53 VSS117 AN46 AV28 VSS181 VSS245 D14
VSS54 VSS118 VSS182 VSS246 VSS_SENSE
AH51 AN48 AV33 D18
AH53 VSS55 VSS119 AN49 AV34 VSS183 VSS247 D2
VSS56 VSS120 VSS184 VSS248
Length Match: No More Than 25Mil
AH55 AN51 AV36 D21 Space: More Than 25Mil
AH57 VSS57 VSS121 AN52 AV39 VSS185 VSS249 D23
AJ13 VSS58 VSS122 AN60 AV41 VSS186 VSS250 D25
GND Reference
AJ14 VSS59 VSS123 AN63 AV43 VSS187 VSS251 D26
AJ23 VSS60 VSS124 AN7 AV46 VSS188 VSS252 D27
AJ25 VSS61 VSS125 AP10 AV49 VSS189 VSS253 D29
AJ27 VSS62 VSS126 AP17 AV51 VSS190 VSS254 D30
AJ29 VSS63 VSS127 AP20 AV55 VSS191 VSS255 D31
VSS64 VSS128 VSS192 15 OF 19 VSS256
Broadwell-ULT_CL8064701614813_QFSY

14 OF 19
Broadwell-ULT_CL8064701614813_QFSY

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/09/07 Deciphered Date 2014/09/07 XXXX

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 16 of 81
5 4 3 2 1
 5 4 3 2 1

Haswell MCP (OTHER)

D CFG4 RC144 1 2 1K_0402_1% D

CFG4
UC1Q HSW_ULT_DDR3L
*L: Embedded DisplayPort Enabled
H: Embedded DisplayPort Disabled
DC_TEST_AY2_AW2 AY2 A3 DC_TEST_A3_B3
TP14 DC_TEST_AY3_AW3 AY3 DAISY_CHAIN_NCTF_AY2 DAISY_CHAIN_NCTF_A3 A4 TP_DC_TEST_A4 1 TP15
@ 1 TP_DC_TEST_AY60 AY60 DAISY_CHAIN_NCTF_AY3 DAISY_CHAIN_NCTF_A4 @
DC_TEST_AY61_AW61 AY61 DAISY_CHAIN_NCTF_AY60 A60 TP_DC_TEST_A60 1 TP16
DC_TEST_AY62_AW62 AY62 DAISY_CHAIN_NCTF_AY61 DAISY_CHAIN_NCTF_A60 A61 DC_TEST_A61_B61 @
TP17 1 TP_DC_TEST_B2 B2 DAISY_CHAIN_NCTF_AY62 DAISY_CHAIN_NCTF_A61 A62 TP_DC_TEST_A62 1 @ TP18
@ DC_TEST_A3_B3 B3 DAISY_CHAIN_NCTF_B2 DAISY_CHAIN_NCTF_A62 AV1 TP_DC_TEST_AV1 1 @ TP19 CFG0 2 @ 1
DC_TEST_A61_B61 B61 DAISY_CHAIN_NCTF_B3 DAISY_CHAIN_NCTF_AV1 AW1 TP_DC_TEST_AW1 1 TP20 RC145 1K_0402_1%
DC_TEST_A62_B63 B62 DAISY_CHAIN_NCTF_B61 DAISY_CHAIN_NCTF_AW1 AW2 DC_TEST_AY2_AW2 @ CFG1 2 @ 1
B63 DAISY_CHAIN_NCTF_B62 DAISY_CHAIN_NCTF_AW2 AW3 DC_TEST_AY3_AW3 RC146 1K_0402_1%
DC_TEST_C1_C2 C1 DAISY_CHAIN_NCTF_B63 DAISY_CHAIN_NCTF_AW3 AW61 DC_TEST_AY61_AW61 CFG8 2 @ 1
C2 DAISY_CHAIN_NCTF_C1 DAISY_CHAIN_NCTF_AW61 AW62 DC_TEST_AY62_AW62 RC147 1K_0402_1%
DAISY_CHAIN_NCTF_C2 DAISY_CHAIN_NCTF_AW62 AW63 TP_DC_TEST_AW63 1 TP21 CFG9 2 @ 1
17 OF 19 DAISY_CHAIN_NCTF_AW63 @ RC148 1K_0402_1%
Broadwell-ULT_CL8064701614813_QFSY CFG10 2 @ 1
RC149 1K_0402_1%

UC1R HSW_ULT_DDR3L
C C

N23 1 TP22
RSVD42 R23 1 TP23
@
RSVD43 T23 1 @
TP25
TP24 1 AT2 RSVD44
RSVD35 U10 1 TP27
@
TP26@ 1 AU44 RSVD45
TP28 remove for layout routing AV44 RSVD36 @ 2 @ 1
@ CFG3
D15 RSVD37 RC150 1K_0402_1%
RSVD38 AL1 1 TP29
RSVD46 AM11 @
RSVD47 AP7 1 TP31
TP30 1 F22 RSVD48
RSVD39 AU10 @
@ H22 RSVD49
RSVD40 AU15 1 TP33
1 J21 RSVD50
RSVD41 AW14 1 TP34
@
TP32@ RSVD51 AY14 1 @
TP35
RSVD52 @
18 OF 19
Broadwell-ULT_CL8064701614813_QFSY
CFG3
1: Disable
0: Enable, Set DFX Enabled BIT
In Debug Interface MSR

UC1S HSW_ULT_DDR3L

B TP36 1CFG0 AC60 AV63 1 TP37 B

TP38@ 1CFG1 AC62 CFG0 RSVD_TP5 AU63 1 @
TP39
TP40@ 1CFG2 AC63 CFG1 RSVD_TP6 @
TP41@ 1CFG3 AA63 CFG2
CFG4 @ AA60 CFG3 C63 1 TP43
TP44 1CFG5 Y62 CFG4 RSVD_TP7 C62 1 @
TP45
TP46@ 1CFG6 Y61 CFG5 RSVD_TP8 B43 @
TP47@ 1CFG7 Y60 CFG6 RSVD58
TP48@ 1CFG8 V62 CFG7 A51 1 TP49
TP50@ 1CFG9 V61 CFG8 RSVD_TP9 B51 1 TP51
@
TP52@ 1CFG10 V60 CFG9 RSVD_TP10 @
TP53@ 1CFG11 U60 CFG10 L60 1 TP54
TP55@ 1CFG12 T63 CFG11 RSVD_TP11 @
TP56@ 1CFG13 T62 CFG12 RESERVED N60
TP57@ 1CFG14 T61 CFG13 RSVD59
TP58@ 1CFG15 T60 CFG14 W23 1 TP59
@ CFG15 RSVD60 Y22 1 TP60
@
TP61 1 CFG16 AA62 RSVD61 AY15 PROC_OPI_COMP @ 2 1
TP62@ 1 CFG18 U63 CFG16 PROC_OPI_RCOMP RC151 49.9_0402_1%
1 CFG17 AA61 CFG18 AV62 1
TP63@
CFG17 RSVD62
TP64 OPI_RCOMP
TP65@ 1 CFG19 U62 D58 1 TP66
@ Width 20Mil
@ CFG19 RSVD63 @ Space 15Mil
2 1 CFG_RCOMP V63 P22
RC152 49.9_0402_1% CFG_RCOMP VSS342 N21
Length 500Mil
A5 VSS343
RSVD53 P20 1
CFG_RCOMP&TD_IREF RSVD64
TP67
Width 20Mil E1 R20 1 TP68
@
D1 RSVD54 RSVD65 @
Space 15Mil RSVD55
J20
Length 500Mil H18 RSVD56
2 1 TD_IREF B12 RSVD57
RC153 8.2K_0402_1% TD_IREF
A 19 OF 19 A
Broadwell-ULT_CL8064701614813_QFSY

Security Classification LC Future Center Secret Data Title

Issued Date 2013/09/07 Deciphered Date 2014/09/07 XXXX

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 17 of 81
5 4 3 2 1
 5 4 3 2 1

Layout Note:
Place near JDIMM1
+1.35V DDR_A_DQS#[0..7] <6>
+1.35V +1.35V
<6> SA_DIMM_VREFDQ DDR_A_DQS[0..7] <6>
JDIMM1 ME@

1
+V_DDR_REFA 1 2
3 VREF_DQ VSS1 4 DDR_A_D[0..63] <6> +1.35V
RD1 DDR_A_D4
DIMM1@ DDR_A_D0 5 VSS2 DQ4 6 DDR_A_D5 DIMM1@ DIMM1@ DIMM1@ DIMM1@ DIMM1@ DIMM1@ DIMM1@
DDR_A_D1 7 DQ0 DQ5 8 DDR_A_MA[0..15] <6>
DIMM1@ 1.8K_0402_1% CD13 CD14 CD15 CD16 CD19 CD20 CD21 CD22
9 DQ1 VSS3 10 DDR_A_DQS#0

2
1 RD2 VSS4 DQS#0

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M

330U_D2_2V_Y
2 11 12 DDR_A_DQS0 1
DM0 DQS0 +1.35V

2.2U_0402_6.3V6-K
1 13 14 1 1 1 1 1 1 1
2_0402_1% VSS5 VSS6

1
1.8K_0402_1%

0.1U_0402_10V7-K
D CD2 DDR_A_D2 15 16 DDR_A_D6 + D
1 1 DQ2 DQ6

DIMM1@

DIMM1@
DIMM1@ DDR_A_D3 17 18 DDR_A_D7
DQ3 DQ7

1
RD3

CD3

CD1
0.022U_0402_25V7-K 19 20
2 @ DDR_A_D8 21 VSS7 VSS8 22 DDR_A_D12 RD21 2 2 2 2 2 2 2 2
DQ8 DQ12
1

2 2 DDR_A_D9 23 24 DDR_A_D13

2
RD4 25 DQ9 DQ13 26 470_0402_5%
DIMM1@ DDR_A_DQS#1 27 VSS9 VSS10 28

2
24.9_0402_1% DDR_A_DQS1 29 DQS#1 DM1 30 DDR3_DRAMRST#
DQS1 RESET# DDR3_DRAMRST# <19,5>
31 32
2

33 VSS11 VSS12 34
DDR_A_D10
DQ10 DQ14
DDR_A_D14 1 For RF solution.
Close to JDIMM1 DDR_A_D11 35 36 DDR_A_D15
37 DQ11 DQ15 38 @ CD59 DIMM1@ DIMM1@
DDR_A_D16 39 VSS13 VSS14 40 DDR_A_D20 0.1U_0402_10V7-K CD8 CD9 CD10 CD11 CRF1 CRF2
DDR_A_D17 41 DQ16 DQ20 42 DDR_A_D21 2
DQ17 DQ21

1U_0402_6.3VA-K

1U_0402_6.3VA-K

1U_0402_6.3VA-K

1U_0402_6.3VA-K

2200P_0402_50V7-K

47P_0402_50V8-J
43 44 @ @ RF_NS@ RF_NS@
DDR_A_DQS#2 45 VSS15 VSS16 46
DQS#2 DM2 1 1 1 1 1 1
DDR_A_DQS2 47 48
49 DQS2 VSS17 50 DDR_A_D22
DDR_A_D18 51 VSS18 DQ22 52 DDR_A_D23
DDR_A_D19 53 DQ18 DQ23 54 2 2 2 2 2 2
55 DQ19 VSS19 56 DDR_A_D28
DDR_A_D24 57 VSS20 DQ28 58 DDR_A_D29
DDR_A_D25 59 DQ24 DQ29 60
61 DQ25 VSS21 62 DDR_A_DQS#3
63 VSS22 DQS#3 64 DDR_A_DQS3
65 DM3 DQS3 66
DDR_A_D26 67 VSS23 VSS24 68 DDR_A_D30
DDR_A_D27 69 DQ26 DQ30 70 DDR_A_D31
71 DQ27 DQ31 72
VSS25 VSS26
Layout Note:
Place near JDIMM1.203,204
C DDRA_CKE0_DIMMA 73 74 DDRA_CKE1_DIMMA C
<6> DDRA_CKE0_DIMMA CKE0 CKE1 DDRA_CKE1_DIMMA <6>
75 76
77 VDD1 VDD2 78 DDR_A_MA15 +0.675VS
DDR_A_BS2 79 NC1 A15 80 DDR_A_MA14 DIMM1@ DIMM1@
<6> DDR_A_BS2 BA2 A14
81 82 CD23 CD24 CD25 CD26
DDR_A_MA12 83 VDD3 VDD4 84 DDR_A_MA11
A12/BC# A11

1U_0402_6.3VA-K

1U_0402_6.3VA-K

1U_0402_6.3VA-K

1U_0402_6.3VA-K
DDR_A_MA9 85 86 DDR_A_MA7 @ @
87 A9 A7 88
VDD5 VDD6 1 1 1 1
DDR_A_MA8 89 90 DDR_A_MA6
DDR_A_MA5 91 A8 A6 92 DDR_A_MA4
93 A5 A4 94
DDR_A_MA3 95 VDD7 VDD8 96 DDR_A_MA2 2 2 2 2
DDR_A_MA1 97 A3 A2 98 DDR_A_MA0
99 A1 A0 100
SA_CLK_DDR0 101 VDD9 VDD10 102 SA_CLK_DDR1
<6> SA_CLK_DDR0 CK0 CK1 SA_CLK_DDR1 <6>
SA_CLK_DDR#0 103 104 SA_CLK_DDR#1
<6> SA_CLK_DDR#0 CK0# CK1# SA_CLK_DDR#1 <6>
105 106
DDR_A_MA10 107 VDD11 VDD12 108 DDR_A_BS1
A10/AP BA1 DDR_A_BS1 <6> +1.35V
DDR_A_BS0 109 110 DDR_A_RAS#
<6> DDR_A_BS0 BA0 RAS# DDR_A_RAS# <6>
111 112
DDR_A_WE# 113 VDD13 VDD14 114 DDRA_CS0_DIMMA#
<6> DDR_A_WE# WE# S0# DDRA_CS0_DIMMA# <6> All VREF traces should

1
DDR_A_CAS# 115 116 SA_ODT0
<6> DDR_A_CAS# CAS# ODT0 have 10 mil trace width
117 118 RD9
DDR_A_MA13 119 VDD15 VDD16 120 SA_ODT1
DDRA_CS1_DIMMA# 121 A13 ODT1 122 1.8K_0402_1%
<6> DDRA_CS1_DIMMA# S1# NC2
123 124

2
125 VDD17 VDD18 126 +VREF_CA 1 RD10 2
NCTEST VREF_CA SM_DIMM_VREFCA <6>
127 128 1
VSS27 VSS28 2_0402_1%

1
0.1U_0402_10V7-K

2.2U_0402_6.3V6-K
DDR_A_D32 129 130 DDR_A_D36 CD12
DDR_A_D33 131 DQ32 DQ36 132 DDR_A_D37 RD11
DQ33 DQ37 1 1
DIMM1@
133 134 0.022U_0402_25V7-K
VSS29 VSS30 2

CD17

CD18
DDR_A_DQS#4 135 136 1.8K_0402_1%
DQS#4 DM4

1
B DDR_A_DQS4 137 138 @ B

2
139 DQS4 VSS31 140 DDR_A_D38 2 2 RD12
DDR_A_D34 141 VSS32 DQ38 142 DDR_A_D39
DDR_A_D35 143 DQ34 DQ39 144 24.9_0402_1%
145 DQ35 VSS33 146 DDR_A_D44

2
DDR_A_D40 147 VSS34 DQ44 148 DDR_A_D45
149 DQ40 DQ45 150 +VREF_CA <19>
DDR_A_D41
151 DQ41 VSS35 152 DDR_A_DQS#5
153 VSS36 DQS#5 154 DDR_A_DQS5
155 DM5 DQS5 156
close to JDDR3L.126
DDR_A_D42 157 VSS37 VSS38 158 DDR_A_D46 +1.35V
DDR_A_D43 159 DQ42 DQ46 160 DDR_A_D47 UD1
161 DQ43 DQ47 162 1 6
VSS39 VSS40 NC1 Vcc 1
DDR_A_D48 163 164 DDR_A_D52 CD61
DDR_A_D49 165 DQ48 DQ52 166 DDR_A_D53 DDR_PG_CTRL 2 5
DQ49 DQ53 <5> DDR_PG_CTRL A NC2
167 168 0.1U_0402_10V7-K
DDR_A_DQS#6 169 VSS41 VSS42 170 3 4 2 SM_PG_CTRL
DDR_A_DQS6 171 DQS#6 DM6 172 GND Y SM_PG_CTRL <69>
173 DQS6 VSS43 174 DDR_A_D54 74AUP1G07GF_SOT891-6_1X1
DDR_A_D50 175 VSS44 DQ54 176 DDR_A_D55
DDR_A_D51 177 DQ50 DQ55 178
179 DQ51 VSS45 180 DDR_A_D60 +5V_DDR +1.35V
DDR_A_D56 181 VSS46 DQ60 182 DDR_A_D61
DQ56 DQ61

1
DDR_A_D57 183 184
185 DQ57 VSS47 186 DDR_A_DQS#7 RD23
187 VSS48 DQS#7 188 DDR_A_DQS7
189 DM7 DQS7 190 220K_0402_5% QD1
VSS49 VSS50

1
DDR_A_D58 191 192 DDR_A_D62 D LBSS138LT1G_1N_SOT23-3

2
DDR_A_D59 193 DQ58 DQ62 194 DDR_A_D63 SM_PG_CTRL 2
195 DQ59 DQ63 196 G RD5 1 DIMM1@2 66.5_0402_1% SA_ODT0
VSS51 VSS52

1
197 198 S RD6 1 DIMM1@2 66.5_0402_1% SA_ODT1

3
199 SA0 EVENT# 200
A +3VS VDDSPD SDA PM_SMB_DAT <19,49,9> A
201 202 @ RD24 RD7 1 DIMM2@2 66.5_0402_1% SB_ODT0
203 SA1 SCL 204 PM_SMB_CLK <19,49,9> 1 DIMM2@2 SB_ODT1 SB_ODT0 <19>
+0.675VS +0.675VS 2M_0402_5% RD8 66.5_0402_1%
VTT1 VTT2 SB_ODT1 <19>

2
2.2U_0402_6.3V6-K

0.1U_0402_10V6-K

@ 205 206
G1 G2
1

1
DIMM1@

0_0402_5%

0_0402_5%

1 1
CD30

RD13

RD14

LCN_DAN06-K4406-0102
CD29

2 2 Security Classification LC Future Center Secret Data Title

Channel A
2

Issued Date 2013/09/07 Deciphered Date 2014/09/07 XXXX

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 18 of 81
5 4 3 2 1
 5 4 3 2 1

+1.35V
+1.35V +1.35V
JDIMM2 ME@ Layout Note:
DDR_B_DQS#[0..7] <6>

1
+V_DDR_REFB 1 2
RD15 3 VREF_DQ VSS_2 4 DDR_B_D4 Place near JDIMM2
DDR_B_D0 5 VSS_1 DQ4 6 DDR_B_D5 DDR_B_DQS[0..7] <6>
DIMM2@
1.8K_0402_1% DDR_B_D1 7 DQ0 DQ5 8
9 DQ1 VSS_4 10 DDR_B_D[0..63] <6> +1.35V
DDR_B_DQS#0

2
1 RD17 2 11 VSS_3 DQS0# 12 DDR_B_DQS0
<6> SB_DIMM_VREFDQ DM0 DQS0 DDR_B_MA[0..15] <6>
1 13 14 DIMM2@ DIMM2@ DIMM2@ DIMM2@ DIMM2@ DIMM2@ DIMM2@
2_0402_1% VSS_5 VSS_6

2.2U_0402_6.3V6-K
DDR_B_D2 15 16 DDR_B_D6 CD42 CD43 CD44 CD45 CD46 CD47 CD48
DQ2 DQ6

CD32 DIMM2@
0.022U_0402_25V7-K CD31 RD16 1 1 DDR_B_D3 17 18 DDR_B_D7
DIMM2@ DQ3 DQ7

0.1U_0402_10V7-K
DIMM2@ DIMM2@ 19 20
2 VSS_7 VSS_8

CD33

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M
1.8K_0402_1% DDR_B_D8 21 22 DDR_B_D12 1 1 1 1 1 1 1
DQ8 DQ12
1
D @ DDR_B_D9 23 24 DDR_B_D13 D

2
2 2 25 DQ9 DQ13 26
24.9_0402_1% RD18 DDR_B_DQS#1 27 VSS_9 VSS_10 28
DIMM2@ DDR_B_DQS1 29 DQS1# DM1 30 DDR3_DRAMRST# 2 2 2 2 2 2 2
DQS1 RESET# DDR3_DRAMRST# <18,5>
31 32
2

DDR_B_D10 33 VSS_11 VSS_12 34 DDR_B_D14

DQ10 DQ14 1
DDR_B_D11 35 36 DDR_B_D15
37 DQ11 DQ15 38 @ CD60
Close to JDIMM2 DDR_B_D24 39 VSS_13 VSS_14 40 DDR_B_D28 0.1U_0402_10V7-K
DDR_B_D25 41 DQ16 DQ20 42 DDR_B_D29 2
43 DQ17 DQ21 44
DDR_B_DQS#3 45 VSS_15 VSS_16 46
DQS2# DM2 For RF solution.
DDR_B_DQS3 47 48 DIMM2@ DIMM2@
49 DQS2 VSS_18 50 DDR_B_D30 CD38 CD39 CD40 CD41 CRF3 CRF4
DDR_B_D26 51 VSS_17 DQ22 52 DDR_B_D31
DDR_B_D27 53 DQ18 DQ23 54
55 DQ19 VSS_20 56 DDR_B_D20
VSS_19 DQ28

1U_0402_6.3VA-K

1U_0402_6.3VA-K

1U_0402_6.3VA-K

1U_0402_6.3VA-K

2200P_0402_50V7-K

47P_0402_50V8-J
DDR_B_D16 57 58 DDR_B_D21 @ @ RF_NS@ RF_NS@
DDR_B_D17 59 DQ24 DQ29 60
DQ25 VSS_22 1 1 1 1 1 1
61 62 DDR_B_DQS#2
63 VSS_21 DQS3# 64 DDR_B_DQS2
65 DM3 DQS3 66
DDR_B_D18 67 VSS_23 VSS_24 68 DDR_B_D22 2 2 2 2 2 2
DDR_B_D19 69 DQ26 DQ30 70 DDR_B_D23
71 DQ27 DQ31 72
VSS_25 VSS_26

DDRB_CKE0_DIMMB 73 74 DDRB_CKE1_DIMMB
<6> DDRB_CKE0_DIMMB CKE0 CKE1 DDRB_CKE1_DIMMB <6>
75 76
77 VDD_1 VDD_2 78 DDR_B_MA15
DDR_B_BS2 79 NC_1 A15 80 DDR_B_MA14
<6> DDR_B_BS2 BA2 A14
81 82
C DDR_B_MA12 83 VDD_3 VDD_4 84 DDR_B_MA11 C
DDR_B_MA9 85 A12/BC# A11 86 DDR_B_MA7
87 A9 A7 88
Layout Note:
DDR_B_MA8 89 VDD_5 VDD_6 90 DDR_B_MA6 Place near JDIMM2.203,204
DDR_B_MA5 91 A8 A6 92 DDR_B_MA4
93 A5 A4 94 +0.675VS
DDR_B_MA3 95 VDD_7 VDD_8 96 DDR_B_MA2
DDR_B_MA1 97 A3 A2 98 DDR_B_MA0 DIMM2@ DIMM2@ DIMM2@ DIMM2@ DIMM2@ DIMM2@
99 A1 A0 100 CD51 CD52 CD53 CD54 CD55 CD56
SB_CLK_DDR0 101 VDD_9 VDD_10 102 SB_CLK_DDR1
<6> SB_CLK_DDR0 CK0 CK1 SB_CLK_DDR1 <6>

1U_0402_6.3VA-K

1U_0402_6.3VA-K

1U_0402_6.3VA-K

1U_0402_6.3VA-K

10U_0603_6.3V6-M

10U_0603_6.3V6-M
SB_CLK_DDR#0 103 104 SB_CLK_DDR#1
<6> SB_CLK_DDR#0 CK0# CK1# SB_CLK_DDR#1 <6>
105 106 1 1 1 1 1 1
DDR_B_MA10 107 VDD_11 VDD_12 108 DDR_B_BS1
A10/AP BA1 DDR_B_BS1 <6>
DDR_B_BS0 109 110 DDR_B_RAS#
<6> DDR_B_BS0 BA0 RAS# DDR_B_RAS# <6>
111 112
DDR_B_WE# 113 VDD_13 VDD_14 114 DDRB_CS0_DIMMB# 2 2 2 2 2 2
<6> DDR_B_WE# WE# S0# DDRB_CS0_DIMMB# <6>
DDR_B_CAS# 115 116 SB_ODT0
<6> DDR_B_CAS# CAS# ODT0 SB_ODT0 <18>
117 118
DDR_B_MA13 119 VDD_15 VDD_16 120 SB_ODT1
A13 ODT1 SB_ODT1 <18>
DDRB_CS1_DIMMB# 121 122
<6> DDRB_CS1_DIMMB# S1# NC_2
123 124
125 VDD_17 VDD_18 126 +VREF_CA
TEST VREF_CA +VREF_CA <18>
127 128
DDR_B_D32 129 VSS_27 VSS_28 130 DDR_B_D36
DDR_B_D33 131 DQ32 DQ36 132 DDR_B_D37
133 DQ33 DQ37 134
VSS_29 VSS_30 1
DDR_B_DQS#4 135 136 CD49
DDR_B_DQS4 137 DQS4# DM4 138 DIMM2@
139 DQS4 VSS_32 140 DDR_B_D38
All VREF traces should
0.1U_0402_10V7-K
DDR_B_D34 141 VSS_31 DQ38 142 DDR_B_D39 2 have 10 mil trace width
DDR_B_D35 143 DQ34 DQ39 144
145 DQ35 VSS_34 146 DDR_B_D44
B DDR_B_D40 147 VSS_33 DQ44 148 DDR_B_D45 B
DDR_B_D41 149 DQ40 DQ45 150
151 DQ41 VSS_35 152 DDR_B_DQS#5
153 VSS_36 DQS5# 154 DDR_B_DQS5
155 DM5 DQS5 156
DDR_B_D42 157 VSS_37 VSS_38 158 DDR_B_D46
DDR_B_D43 159 DQ42 DQ46 160 DDR_B_D47
161 DQ43 DQ47 162
DDR_B_D48 163 VSS_39 VSS_40 164 DDR_B_D52
DDR_B_D49 165 DQ48 DQ52 166 DDR_B_D53
167 DQ49 DQ53 168
DDR_B_DQS#6 169 VSS_41 VSS_42 170
DDR_B_DQS6 171 DQS6# DM6 172
173 DQS6 VSS_44 174 DDR_B_D54
DDR_B_D50 175 VSS_43 DQ54 176 DDR_B_D55
DDR_B_D51 177 DQ50 DQ55 178
179 DQ51 VSS_46 180 DDR_B_D60
+3VS DDR_B_D56 181 VSS_45 DQ60 182 DDR_B_D61
DDR_B_D57 183 DQ56 DQ61 184
185 DQ57 VSS_48 186 DDR_B_DQS#7
VSS_47 DQS7#
1

187 188 DDR_B_DQS7

RD19 189 DM7 DQS7 190
DIMM2@ DDR_B_D58 191 VSS_49 VSS_50 192 DDR_B_D62
10K_0402_5% DDR_B_D59 193 DQ58 DQ62 194 DDR_B_D63
195 DQ59 DQ63 196
2

197 VSS_51 VSS_52 198

199 SA0 EVENT# 200
+3VS VDDSPD SDA PM_SMB_DAT <18,49,9>
201 202
203 SA1 SCL 204 PM_SMB_CLK <18,49,9>
+0.675VS VTT_1 VTT_2 +0.675VS
205 206
GND1 GND2
2.2U_0402_6.3V6-K

0.1U_0402_10V6-K

CD58 DIMM2@

@ 207 208
BOSS1 BOSS2
1
0_0402_5%

A A
1 1
RD20
CD57

LCN_DAN06-K4406-0103
2 2
Channel B
2

Security Classification LC Future Center Secret Data Title

<Address: SA1:SA0=10>
Issued Date 2013/09/07 Deciphered Date 2014/09/07 XXXX
DIMM_2 STD H:4mm THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 19 of 81
5 4 3 2 1
 1 2 3 4 5

UV1A OPAL@

PART 1 0F 9

<13> PCIE_CTX_C_GRX_P0 PCIE_CTX_C_GRX_P0 AA38 Y33 PCIE_CRX_C_GTX_P0 CV1 DIS@ 1 2 0.1U_0402_10V7-K PCIE_CRX_GTX_P0
PCIE_RX0P PCIE_TX0P PCIE_CRX_GTX_P0 <13>
CTX0 <13> PCIE_CTX_C_GRX_N0 PCIE_CTX_C_GRX_N0 Y37 Y32 PCIE_CRX_C_GTX_N0 CV2 DIS@ 1 2 0.1U_0402_10V7-K PCIE_CRX_GTX_N0 CRX0
PCIE_RX0N PCIE_TX0N PCIE_CRX_GTX_N0 <13>
A A

<13> PCIE_CTX_C_GRX_P1 PCIE_CTX_C_GRX_P1 Y35 W33 PCIE_CRX_C_GTX_P1 CV3 DIS@ 1 2 0.1U_0402_10V7-K PCIE_CRX_GTX_P1
PCIE_RX1P PCIE_TX1P PCIE_CRX_GTX_P1 <13>
CTX1 <13> PCIE_CTX_C_GRX_N1 PCIE_CTX_C_GRX_N1 W36 W32 PCIE_CRX_C_GTX_N1 CV4 DIS@ 1 2 0.1U_0402_10V7-K PCIE_CRX_GTX_N1 CRX1
PCIE_RX1N PCIE_TX1N PCIE_CRX_GTX_N1 <13>

<13> PCIE_CTX_C_GRX_P2 PCIE_CTX_C_GRX_P2 W38 U33 PCIE_CRX_C_GTX_P2 CV5 DIS@ 1 2 0.1U_0402_10V7-K PCIE_CRX_GTX_P2
PCIE_RX2P PCIE_TX2P PCIE_CRX_GTX_P2 <13>
CTX2 <13> PCIE_CTX_C_GRX_N2 PCIE_CTX_C_GRX_N2 V37 U32 PCIE_CRX_C_GTX_N2 CV6 DIS@ 1 2 0.1U_0402_10V7-K PCIE_CRX_GTX_N2 CRX2
PCIE_RX2N PCIE_TX2N PCIE_CRX_GTX_N2 <13>

PCIE_CTX_C_GRX_P3 V35 U30 PCIE_CRX_C_GTX_P3 CV7 DIS@ 1 2 0.1U_0402_10V7-K PCIE_CRX_GTX_P3

<13> PCIE_CTX_C_GRX_P3 PCIE_RX3P PCIE_TX3P PCIE_CRX_GTX_P3 <13>
CTX3 <13> PCIE_CTX_C_GRX_N3 PCIE_CTX_C_GRX_N3 U36 U29 PCIE_CRX_C_GTX_N3 CV8 DIS@ 1 2 0.1U_0402_10V7-K PCIE_CRX_GTX_N3 CRX3
PCIE_RX3N PCIE_TX3N PCIE_CRX_GTX_N3 <13>

U38 T33
T37 PCIE_RX4P PCIE_TX4P T32
PCIE_RX4N PCIE_TX4N

T35 T30
R36 PCIE_RX5P PCIE_TX5P T29
PCIE_RX5N PCIE_TX5N

R38 P33
P37 PCIE_RX6P PCIE_TX6P P32
PCIE_RX6N PCIE_TX6N

P35 P30
N36 PCIE_RX7P PCIE_TX7P P29
PCIE_RX7N PCIE_TX7N

N38 N33
M37 PCIE_RX8P PCIE_TX8P N32
PCIE_RX8N PCIE_TX8N

PCI EXPRESS INTERFACE

UV1C

M35 N30
B
L36 PCIE_RX9P PCIE_TX9P N29 B
PCIE_RX9N PCIE_TX9N PART 3 0F 9

RC114 1 @ 2 0_0402_5% L38 L33

K37 PCIE_RX10P PCIE_TX10P L32
+3VS_VGA PCIE_RX10N PCIE_TX10N
L->H AV33 XTALIN
+3VS K35 L30 XTALIN
PCIE_RX11P PCIE_TX11P
1

J36 L29
RV9 PCIE_RX11N PCIE_TX11N
5

10K_0402_5%
@ J38 K33 160mA
VCC

PLTRST# 1 H37 PCIE_RX12P PCIE_TX12P K32

<10> PLTRST#
2

IN1 4 PCIE_RX12N PCIE_TX12N AU34 XTALOUT

OUT PLT_RST_VGA# <21,76> XTALOUT
DGPU_HOLD_RST# 2 +1.8VS_VGA MPLL_PVDD
GND

<11> DGPU_HOLD_RST# IN2

1

H35 J33
RV167 G36 PCIE_RX13P PCIE_TX13P J32 LV3 DIS@
UV15 DIS@ 100K_0402_5% PCIE_RX13N PCIE_TX13N 1 2 CV220 CV219 CV218 H7
3

MC74VHC1G08DFT2G_SC70-5 DIS@ H8 MPLL_PVDD_1

MPLL_PVDD_2

10U_0603_6.3V6-M

1U_0402_10V6-K

0.1U_0402_10V7-K
G38 K30 BLM18PG221SN1D_2P
2

F37 PCIE_RX14P PCIE_TX14P K29 AW34

PCIE_RX14N PCIE_TX14N 1 1 1 XO_IN
AM10
SPLL_PVDD

DIS@

DIS@

DIS@
F35 H33

PLLS/XTAL
E37 PCIE_RX15P PCIE_TX15P H32 2 2 2
PCIE_RX15N PCIE_TX15N
AN9 AW35
CLOCK SPLL_VDDC XO_IN2

CLK_PCIE_VGA RV4 1 2 0_0402_5% AB35

75mA
<8> CLK_PCIE_VGA PCIE_REFCLKP
CLK_PCIE_VGA# RV5 1 2 0_0402_5% AA36 AN10
<8> CLK_PCIE_VGA# PCIE_REFCLKN SPLL_PVSS
+0.95VS_VGA +1.8VS_VGA SPLL_PVDD
LV4 DIS@
CALIBRATION 1 2 CV222 CV221 CV225
C Y30 RV6 1 DIS@ 2 1.69K_0402_1% AK10 C
PCIE_CALR_TX CLKTESTA

10U_0603_6.3V6-M

1U_0402_10V6-K

0.1U_0402_10V7-K
BLM18PG121SN1D_2P AF30 AL10
RV7 1 DIS@ 2 1K_0402_5% AH16 Y29 RV8 1 DIS@ 2 1K_0402_5% AF31 NC_XTAL_PVDD CLKTESTB
TEST_PG PCIE_CALR_RX 1 1 1 NC_XTAL_PVSS

DIS@

DIS@

DIS@
PLT_RST_VGA# AA30
PERSTB 2 2 2

216-0855000_A0_FCBGA962
100mA
216-0855000_A0_FCBGA962
+0.95VS_VGA
SPLL_VDDC
LV5 DIS@
1 2 CV226 CV223 CV224

+3VS_VGA

10U_0603_6.3V6-M

1U_0402_10V6-K

0.1U_0402_10V7-K
BLM18PG121SN1D_2P
1 1 1
1

DIS@

DIS@

DIS@
RV11 2 2 2
@
10K_0402_5% RV10 DIS@
2

RV13 @ 1 2
2 1
<11,29,72,76,77> VGA_ON
1M_0402_5%
CV19

0.1U_0402_10V7-K

10K_0402_5%
+3VS_VGA YV1 DIS@
1
4 3 XTALOUT
NC2 OSC2
1
@

XTALIN 1 2
2 RV14 OSC1 NC1
@ 1 27MHZ_16PF_7V27000011 1
D D
10K_0402_5% CV17 CV18
2

QV1 DIS@ DIS@

G

@ 22P_0402_50V8-J 22P_0402_50V8-J
1 3 CLK_REQ_GPU# 2 2
<8> CLKREQ_PCIE4_VGA# CLK_REQ_GPU# <21>
CV20

0.1U_0402_10V7-K

1
2

2N7002WT1G_1N_SC-70-3
SB00000YY00 RV15
@

10K_0402_5% Title
2 1 @ 2 @ Security Classification LC Future Center Secret Data
Issued Date 2012/07/01 Deciphered Date 2014/07/01 XXXX
1

RV16 0_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 20 of 81
1 2 3 4 5
 5 4 3 2 1

UV1B After check with AE, can leave NC for GPIO17. RV110 @
+3VS_VGA
PART 2 0F 9 1 2
H_THERMTRIP# <12>
@
MUTI GFX GPIO17_THERMAL_INT RV104 1 2 47K_0402_5% 0_0402_5%
AD29 AU24 RV105 @
GENLK_CLK TXCAP_DPA3P

1
AC29 AV23 C
GENLK_VSYNC TXCAM_DPA3N GPIO19_CTF RV102 1 @ 2 47K_0402_5% 1 2 2 QV4
AT25 B S TR TTC4116FU NPN SC-70-3
TX0P_DPA2P

0.1U_0402_25V6-K
AJ21 AR24 RV118 2 @ 1 10K_0402_5% 2.2K_0402_5% E SB000010U00

3
SWAPLOCKA TX0M_DPA2N

1
DPA

CV209 @
AK21 1 @
D SWAPLOCKB AU26 RV103 @ D
TX1P_DPA1P AV25 10K_0402_5%
6 1 SMBCLK TX1M_DPA1N

S
<34,55,62,9> EC_SMB_CK3 AR8 AT27 2
DV4 @

2
DIS@ QV5A AU8 DVPCNTL_MVP_0 TX2P_DPA0P AR26 PLT_RST_VGA# 1 2
DVPCNTL_MVP_1 TX2M_DPA0N <20,76> PLT_RST_VGA#
2N7002KDWH_SOT363-6 AP8
AW8 DVPCNTL_0 AR30 RB751V-40_SOD323-2
2 @ 1 RV144 AR3 DVPCNTL_1 TXCBP_DPB3P AT29 SCS00006S00
AR1 DVPCNTL_2 TXCBM_DPB3N
0_0402_5% AU1 DVPCLK AV31
DVPDATA_0 TX3P_DPB2P

5
AU3 AU30

G
AW3 DVPDATA_1 DPB TX3M_DPB2N
AP6 DVPDATA_2 AR32
VID CODES Add Optional Bypass resistor
AW5 DVPDATA_3 TX4P_DPB1P AT31
3 4 SMBDAT AU5 DVPDATA_4 TX4M_DPB1N RV115 1 2 0_0402_5%
SVC SVD Boot Voltage

S
<34,55,62,9> EC_SMB_DA3 DVPDATA_5
AR6 AT33

D
DIS@ QV5B AW6 DVPDATA_6 TX5P_DPB0P AU32 RV116 1 2 0_0402_5%
2N7002KDWH_SOT363-6 AU6 DVPDATA_7 TX5M_DPB0N 0 0 1.1V
AT7 DVPDATA_8 AU14 +1.8VS_VGA
0_0402_5% 2 @ 1 RV142 AV7 DVPDATA_9 TXCCP_DPC3P AV13 0 1 1.0V
AN7 DVPDATA_10 TXCCM_DPC3N +3VS_VGA
PU AT EC SIDE, +3VS AND 4.7K DVPDATA_11 1 0 0.9V(Default)
AV9 AT15
AT9 DVPDATA_12 TX0P_DPC2P AR14 +3VS_VGA
DVPDATA_13 TX0M_DPC2N 1 1 0.8V

CV207

0.1U_0402_10V7-K
AR10
AW10 DVPDATA_14 DPC AU16
DVPDATA_15 TX1P_DPC1P 1
AU10 AV15
DVPDATA_16 TX1M_DPC1N

CV205

0.1U_0402_10V7-K
AP10
DVPDATA_17

@
AV11 AT17 1
+3VS_VGA AT11 DVPDATA_18 TX2P_DPC0P AR16 2
DVPDATA_19 TX2M_DPC0N

1
AR12
DVPDATA_20

@
AW12 AU20 RV91 RV92
RV99 1 DIS@ 2 45.3K_0402_1% AU12 DVPDATA_21 TXCDP_DPD3P AT19 10K_0402_5% 10K_0402_5% 2
AP12 DVPDATA_22 TXCDM_DPD3N @ DIS@ UV14 @
RV98 1 DIS@ 2 45.3K_0402_1% DVPDATA_23 AT21

2
TX3P_DPD2P
TX3M_DPD2N
AR20 SVD 1
VCC(A) VCC(B)
8

SMBCLK AJ23 DPD AU22 GPIO15_PWRCNTL_0 RV89 1 2 0_0402_5% 2 7 RV96 1 @ 2 33_0402_5% SVI2_SVD
AH23 SMBCLK SMBus TX4P_DPD1P AV21 1A 1B SVI2_SVD <76>
SMBDAT
SMBDATA TX4M_DPD1N GPIO20_PWRCNTL_1 RV90 1 2 0_0402_5% 3 6 RV97 1 @ 2 33_0402_5% SVI2_SVC
2A 2B SVI2_SVC <76>
AT23
TX5P_DPD0P
TX5M_DPD0N
AR22 SVC 5
DIR GND
4

1
Test_Point_20MIL 1 TPV13 I2CS_SCL AK26
C Test_Point_20MIL 1 TPV14 I2CS_SDA AJ26 SCL I2C RV127 RV133 C
SDA 10K_0402_5% 10K_0402_5% 74AVCH2T45GD_XSON8_3X2
AD39 DIS@ @
R AD37 +3VS_VGA
GENERAL PURPOSE I/O RV134

2
+3VS_VGA @ 2 10K_0402_5% AVSSN_1
+3VS_VGA RV138 1 AH20
2 10K_0402_5% GPIO_0
RV139 1 @ AH18 AE36 1 2
GPIO_1 G
NC but reserved PU resistor RV140 1 @ 2 10K_0402_5% AN16 AD35
GPIO_2 AVSSN_2

CV206

0.1U_0402_10V7-K

10U_0603_6.3V6-M
10K_0402_5%

CV208
AF37 1 1 @
RV117 GPIO5_AC_BATT AH17 B AE38
DIS@ AJ17 GPIO_5_AC_BATT AVSSN_3
GPIO_6 DAC1 Keep voltage level.

@
2.2K_0402_5% AK17 AC36
GPIO_7_BLON HSYNC 2 2

@
Test_Point_20MIL 1 TPV3 GPIO8_ROMSO AJ13 AC38
2

Test_Point_20MIL 1 TPV4 GPIO9_ROMSI AH15 GPIO_8_ROMSO VSYNC

GPIO_9_ROMSI

1
Test_Point_20MIL 1 TPV5 GPIO10_ROMSCK AJ16 +1.8VS_VGA
DV5 AK16 GPIO_10_ROMSCK AB34 RV145 RV146
VGA_AC_DC# 1 2 GPIO5_AC_BATT AL16 GPIO_11 RSET 10K_0402_5% 10K_0402_5%
MLPS Recommend setting Value
<62> VGA_AC_DC# GPIO_12
AM16 AD34 DIS@ DIS@
RB751V-40_SOD323-2 AM14 GPIO_13 AVDD AE34

2
SCS00006S00 GPIO15_PWRCNTL_0 AM13 GPIO_14_HPD2 AVSSQ
GPIO_15_PWRCNTL_0 RV112 = 8.45K ohm

1
DIS@ AK14 AC33
GPIO_16 VDD1DI
GPIO17_THERMAL_INT AG30
GPIO_17_THERMAL_INT VSS1DI
AC34 RV148 PS_0 PS0[5..1] = 11001 RV113 = 2K ohm
RV149 1 @ 2 0_0402_5% AN14 DIS@
<62,76> GPU_VR_HOT#
GPIO19_CTF AM17 GPIO_18_HPD3 499_0402_1% CV213 = NC
GPIO20_PWRCNTL_1 AL13 GPIO_19_CTF V13

2
AJ14 GPIO_20_PWRCNTL_1 NC_1 U13
Test_Point_20MIL 1 TPV6 GPIO22_ROMCSB AK13 GPIO_21 NC_2 AF33
RV129 1 @ 2 0_0402_5% AN13 GPIO_22_ROMCSB NC_TSVSSQ AF32
RV106 = NC
<20> CLK_REQ_GPU#
RV130 1 @ 2 100_0402_5% CLKREQB NC_7
NC_8
AA29
PS_1 PS1[5..1] = 11000 RV109 = 4.75K ohm
AG21
AG32 NC_9 AC32 CV212 = NC
AG33 GPIO_29 NC_5
GPIO_30 AC31
AJ19 NC_3 AD30
AK19 GENERICA NC_4 AD32
RV108 = NC
+1.8VS_VGA GENERICB NC_6
AJ20
GENERICC +1.8VS_VGA +1.8VS_VGA PS_2 PS2[5..1] = 11000 RV111 = 4.75K ohm
AK20
AJ24 GENERICD CV210 = NC
AH26 GENERICE_HPD4
GENERICF_HPD5

1
AH24
GENERICG_HPD6 RV112 RV108
AM34 PS_0 DIS@ @
RV114 =
2

PS_0
B 8.45K_0402_1% 4.99K_0402_1%
PS_3 PS3[5..1] = 11xxx RV107 = B
RV128 AC30
CV211 = NC

2
499_0402_1% CEC_1 CV213 PS_0 CV210 PS_2
DIS@ AK24 AD31 PS_1
HPD1 MLPS PS_1

0.1U_0402_10V7-K

0.082U_0402_50V7-K
1

1
1 1
RV113 RV111
CV214 VREFG AH13 AG31 PS_2 DIS@ DIS@
VREFG PS_2

@
PX5.0 doesn't need this function. Leave as NC. 2K_0402_1%
2
4.75K_0402_1%
2
0.1U_0402_10V7-K

2
1 BACO RV114 RV107 Strap PS_3[3..1]
Test_Point_20MIL 1 TPV12 RV101 1 @ 2 0_0402_5% AL21 AD33 PS_3
PX_EN PS_3
2

2
+3VS_VGA Memory (GDDR3)
RV160 @
249_0402_1% RV93 1 2 5.11K_0402_1%
DEBUG DDC/AUX AM26
DIS@ DDC1CLK +1.8VS_VGA +1.8VS_VGA
1G PU 8.45K PD 2K 001
RV94 1 DIS@ 2 1K_0402_5% AN26 Samsung
1

AD28 DDC1DATA
TESTEN AM27
AUX1P 2G PU 3.4K PD 10K 110

1
AL27
AUX1N RV106 RV114
Test_Point_20MIL 1 TPV7 JTAG_TRSTB AM23 AM19 @ S2G@ 1G PU 4.53K PD 2K 010
1 JTAG_TDI AN23 JTAG_TRSTB DDC2CLK AL19
Test_Point_20MIL TPV8
JTAG_TDI DDC2DATA
8.45K_0402_1% 3.4K_0402_1% Hynix
Test_Point_20MIL 1 TPV9 JTAG_TCK AK23

2
1 AL24 JTAG_TCK AN20
+3VS_VGA Test_Point_20MIL TPV10 JTAG_TMS
JTAG_TMS AUX2P
CV212 PS_1 CV211 PS_3 2G PU 4.75K NC 111
Test_Point_20MIL 1 TPV11 JTAG_TDO AM24 AM20
JTAG_TDO AUX2N

0.1U_0402_10V7-K

0.1U_0402_10V7-K
1

1
AL30 1 1 1G NC PD 4.75K 000
DDCCLK_AUX3P
1

AM30 RV109 RV107 Micron

DDCDATA_AUX3N
1

RV137 DIS@ S2G@

THERMAL

@
RV131 RV132 RV135 RV136 10K_0402_5% AL29 4.75K_0402_1% 10K_0402_1% 2G PU 3.24K PD 5.62K 101
10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% @ AF29 DDCCLK_AUX4P AM29 2 2

2
@ @ @ @ AG29 DPLUS DDCDATA_AUX4N
2

DMINUS AN21
2

DIS@ DDCCLK_AUX5P AM21

JTAG_TRSTB RV147 1 2 FDO AK32 DDCDATA_AUX5N
JTAG_TMS
JTAG_TDI
13mA 10K_0402_5% AL31
GPIO_28_FDO
DDCCLK_AUX6P
AK30
AK29
JTAG_TDO +1.8VS_VGA TS_A DDCDATA_AUX6N
LV6
AJ30
1 2 CV216 CV217 CV215 AJ32 DDCVGACLK AJ31
A AJ33 TSVDD DDCVGADATA A
TSVSS
10U_0603_6.3V6-M

0.1U_0402_10V7-K

BLM15PX121SN1D_2P
1U_0402_10V6-K

DIS@ 1 1 1

E450 unused. 216-0855000_A0_FCBGA962

DIS@

DIS@

DIS@

2 2 2

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 XXXX

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 21 of 81
5 4 3 2 1
 1 2 3 4 5

100mA
+1.8VS_VGA

1.5A UV1E TPV1

Test_Point_32MIL CV21 CV24 CV25

10U_0603_6.3V6-M
+1.5VS_VGA PART 5 0F 9

1U_0402_10V6-K

1U_0402_10V6-K
MEM I/O 1 1 1

1
CV22 CV26 CV27 CV28 CV23 CV29 CV30 CV31 AC7 AA31
AD11 VDDR1_1 NC_PCIE_VDDR_1 AA32
VDDR1_2 NC_PCIE_VDDR_2

.01U_0402_16V7-K

0.1U_0402_10V7-K

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

10U_0603_6.3V6-M

DIS@

DIS@

DIS@
AF7 AA33
AG10 VDDR1_3 NC_PCIE_VDDR_3 AA34 2 2 2

A
1 1 1 1 1 1 1 1
AJ7
AK8
VDDR1_4
VDDR1_5
NC_PCIE_VDDR_4
NC_PCIE_VDDR_5
W30
Y31
1A A
VDDR1_6 NC_PCIE_VDDR_6

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@
AL9 V28 +0.95VS_VGA
2 2 2 2 2 2 2 2 G11 VDDR1_7 NC_BIF_VDDC_1 W29
G14 VDDR1_8 NC_BIF_VDDC_2 AB37
G17 VDDR1_9 PCIE_PVDD
0.8A

PCIE
G20 VDDR1_10 G30 CV32 CV33 CV34 CV35 CV36 CV37 CV38
G23 VDDR1_11 PCIE_VDDC_1 G31
VDDR1_12 PCIE_VDDC_2

10U_0603_6.3V6-M
G26 H29 +0.95VS_VGA
VDDR1_13 PCIE_VDDC_3

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K
G29 H30 1 1 1 1 1 1 1
H10 VDDR1_14 PCIE_VDDC_4 J29
J7 VDDR1_15 PCIE_VDDC_5 J30 CV227
VDDR1_16 PCIE_VDDC_6

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@
J9 L28
VDDR1_17 PCIE_VDDC_7 2 2 2 2 2 2 2

1U_0402_10V6-K
K11 M28
K13 VDDR1_18 PCIE_VDDC_8 N28
VDDR1_19 PCIE_VDDC_9 1
K8 R28
L12 VDDR1_20 PCIE_VDDC_10 T28
VDDR1_21 PCIE_VDDC_11

DIS@
L16 U28
L21
L23
VDDR1_22
VDDR1_23
PCIE_VDDC_12 2 37A
L26 VDDR1_24 N27
L7 VDDR1_25 BACO BIF_VDDC_1 T27 +VGA_CORE
M11 VDDR1_26 BIF_VDDC_2
N11 VDDR1_27
13mA P7
R11
VDDR1_28
VDDR1_29 CORE VDDC_1
AA15
AA17
CV39 CV40 CV41 CV42 CV43 CV44 CV45 CV46 CV47 CV48 CV49 CV50 CV51 CV52
VDDR1_30 VDDC_2

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M
+1.8VS_VGA U11 AA20
U7 VDDR1_31 VDDC_3 AA22
VDDR1_32 VDDC_4 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Y11 AA24
CV53 Y7 VDDR1_33 VDDC_5 AA27
VDDR1_34 VDDC_6

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

@
AB16
VDDC_7 AB18 2 2 2 2 2 2 2 2 2 2 2 2 2 2
VDDC_8
1U_0402_10V6-K

1 AB21
+1.8VS_VGA VDDC_9 AB23
VDDC_10 AB26
LEVEL VDDC_11
DIS@

TRANSLATION AB28
B 2 AF26 VDDC_12 AC17 B
AF27 VDD_CT_1 VDDC_13 AC20 CV54 CV55 CV56 CV57 CV58 CV59 CV60 CV61
25mA AG26 VDD_CT_2
VDD_CT_3
VDDC_14
VDDC_15
AC22

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K
AG27 AC24
+3VS_VGA +3VS_VGA VDD_CT_4 VDDC_16 AC27
VDDC_17 1 1 1 1 1 1 1 1
AD18
VDDC_18 AD21
I/O VDDC_19

DIS@

DIS@

DIS@

DIS@

DIS@

@
CV62 AF23 AD23
AF24 VDDR3_1 VDDC_20 AD26 2 2 2 2 2 2 2 2
AG23 VDDR3_2 VDDC_21 AF17
VDDR3_3 VDDC_22
1U_0402_10V6-K

1 AG24 AF20
VDDR3_4 VDDC_23 AF22
VDDC_24 AG16
DVP VDDC_25
@

AD12 AG18
2 AF11 VDDR4_1 VDDC_26
AF12 VDDR4_2 AH22
AF13 VDDR4_3 VDDC_28 AH27
30mA VDDR4_4 VDDC_29
VDDC_30
AH28
M26
+1.8VS_VGA AF15 VDDC_31 N24
AG11 VDDR4_5 VDDC_32 R18
AG13 VDDR4_6 VDDC_33 R21
CV63 AG15 VDDR4_7 VDDC_34 R23
VDDR4_8 VDDC_35 R26
VDDC_36
1U_0402_10V6-K

T17
VDDC_37 T20
1 VDDC_38 T22
VDDC_39 T24
VDDC_40
DIS@

U16
2 VDDC_41 U18
VDDC_42 U21
VDDC_43 U23
VDDC_44 U26
VDDC_45 V17
VDDC_46 V20
C C
VDDC_47 V22
VDDC_48 V24
VDDC_49 V27
VDDC_50 Y16
VDDC_51
VDDC_52
Y18
Y21
37A
VDDC_53 Y23
VDDC_54 Y26 +VGA_CORE
VDDC_55 Y28
VDDC_56
AA13 CV64 CV65 CV66 CV67 CV68 CV69 CV70
VDDCI_1 AB13
VDDCI_2

10U_0603_6.3V6-M

10U_0603_6.3V6-M

0.1U_0402_10V7-K

0.1U_0402_10V7-K
AC12
VDDCI_3

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K
AC15 1 1 1 1 1 1 1
VDDCI_4 AD13
VDDCI_5 AD16
VDDCI_6

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@
M15
VDDCI_7 M16 2 2 2 2 2 2 2
VDDCI_8 M18
VOLTAGE VDDCI_9 M23
VDDCI_10
CORE I/O

SENESE N13
ISOLATED

AF28 VDDCI_11 N15

<76> VDDC_SEN FB_VDDC VDDCI_12 N17
VDDCI_13 N20
AG28 VDDCI_14 N22
FB_VDDCI VDDCI_15 R12
VDDCI_16 R13
AH29 VDDCI_17 R16
<76> VDDC_RTN FB_GND VDDCI_18 T12
VDDCI_19 T15
VDDCI_20 V15
VDDCI_21 Y13
VDDCI_22

D D
216-0855000_A0_FCBGA962

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 XXXX
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 22 of 81
1 2 3 4 5
 5 4 3 2 1

UV1G

PART 7 0F 9

AB39 A3 UV1F
280mA
E39 GND_176 GND_1 A37 UV1D
F34 GND_177 GND_2 AA16 +0.95VS_VGA
F39 GND_178 GND_3 AA18 PART 6 0F 9
G33 GND_179 GND_4 AA2 PART 4 0F 9
G34 GND_180 GND_5 AA21 DP_VDDR DP_VDDC
H31 GND_181 GND_6 AA23 AP31 AK27
H34 GND_182 GND_7 AA26 DP_VDDC_1 AP32 VARY_BL AJ27
D D
H39 GND_183 GND_8 AA28 DP_VDDC_2 AN33 DIGON
J31 GND_184 GND_9 AA6 DP_VDDC_3 AP33 LVDS CONTROL
J34 GND_185 GND_10 AB12 AN24 DP_VDDC_4 AL33
K31 GND_186 GND_11 AB15 AP24 NC_DP_VDDR_1 DP_VDDC_5 AM33
K34 GND_187 GND_12 AB17 AP25 NC_DP_VDDR_6 DP_VDDC_6 AK33 AK35
K39 GND_188 GND_13 AB20 AP26 NC_DP_VDDR_7 DP_VDDC_7 AK34 TXCLK_UP_DPF3P AL36
L31 GND_189 GND_14 AB22 AU28 NC_DP_VDDR_8 DP_VDDC_8 AN31 TXCLK_UN_DPF3N
L34 GND_190 GND_15 AB24 AV29 NC_DP_VDDR_10 DP_VDDC_9 AJ38
M34 GND_191 GND_16 AB27 NC_DP_VDDR_12 TXOUT_U0P_DPF2P AK37
M39 GND_192 GND_17 AC11 TXOUT_U0N_DPF2N
N31 GND_193 GND_18 AC13 AP20 AP13 AH35
N34 GND_194 GND_19 AC16 AP21 NC_DP_VDDR_2 NC_DP_VDDC_1 AT13 TXOUT_U1P_DPF1P AJ36
P31 GND_195 GND_20 AC18 AP22 NC_DP_VDDR_3 NC_DP_VDDC_4 AP14 TXOUT_U1N_DPF1N
P34
P39
GND_196
GND_197
GND_21
GND_22
AC2
AC21
237mA AP23
AU18
NC_DP_VDDR_4
NC_DP_VDDR_5
NC_DP_VDDC_2
NC_DP_VDDC_3
AP15
TXOUT_U2P_DPF0P
AG38
AH37
R34 GND_198 GND_23 AC23 AV19 NC_DP_VDDR_9 TXOUT_U2N_DPF0N
T31 GND_199 GND_24 AC26 +1.8VS_VGA NC_DP_VDDR_11 DP GND AF35
T34 GND_200 GND_25 AC28 AN27 TXOUT_U3P AG36
GND_201 GND_26 DP_VSSR_1 TXOUT_U3N

LVTMDP
T39 AC6 CV71 CV72 AH34 AP27
U31 GND_202 GND_27 AD15 AJ34 DP_VDDR_13 DP_VSSR_2 AP28
GND_203 GND_28 DP_VDDR_14 DP_VSSR_3

10U_0603_6.3V6-M
U34 AD17 AF34 AW24
GND_204 GND_29 DP_VDDR_15 DP_VSSR_4

1U_0402_10V6-K
V34 AD20 1 1 AG34 AW26
V39 GND_205 GND_30 AD22 AM37 DP_VDDR_16 DP_VSSR_5 AN29 AP34
W31 GND_206 GND_31 AD24 AL38 DP_VDDR_17 DP_VSSR_6 AP29 TXCLK_LP_DPE3P AR34
GND_207 GND_32 DP_VDDR_18 DP_VSSR_7 TXCLK_LN_DPE3N

@
W34 AD27 AM32 AP30
Y34 GND_208 GND_33 AD9 2 2 DP_VDDR_19 DP_VSSR_8 AW30 AW37
Y39 GND_209 GND_34 AE2 DP_VSSR_9 AW32 TXOUT_L0P_DPE2P AU35
GND_210 GND_35 AE6 DP_VSSR_10 AN17 TXOUT_L0N_DPE2N
GND_36 AF10 DP_VSSR_11 AP16 AR37
GND_37 AF16 DP_VSSR_12 AP17 TXOUT_L1P_DPE1P AU39
GND_38 AF18 DP_VSSR_13 AW14 TXOUT_L1N_DPE1N
GND_39 AF21 DP_VSSR_14 AW16 AP35
GND GND_40 DP_VSSR_15 TXOUT_L2P_DPE0P
AG17 AN19 AR35
F15 GND_41 AG2 DP_VSSR_16 AP18 TXOUT_L2N_DPE0N
C
F17 GND_100 GND_42 AG20 DP_VSSR_17 AP19 AN36 C
F19 GND_101 GND_43 DP_VSSR_18 AW20 TXOUT_L3P AP37
F21 GND_102 AG6 CALIBRATION DP_VSSR_19 AW22 TXOUT_L3N
F23 GND_103 GND_45 AG9 DP_VSSR_20 AN34
F25 GND_104 GND_46 AH21 DP_VSSR_21 AP39
F27 GND_105 GND_47 AJ10 AW28 DP_VSSR_22 AR39
F29 GND_106 GND_48 AJ11 DPAB_CALR DP_VSSR_23 AU37
F31 GND_107 GND_49 AJ2 DP_VSSR_24 AF39 216-0855000_A0_FCBGA962
F33 GND_108 GND_50 AJ28 DP_VSSR_25 AH39
F7 GND_109 GND_51 AJ6 AW18 DP_VSSR_26 AK39
F9 GND_110 GND_52 AK11 DPCD_CALR DP_VSSR_27 AL34
G2 GND_111 GND_53 AK31 DP_VSSR_28 AV27
G6 GND_112 GND_54 AK7 DIS@ DP_VSSR_29 AR28
H9 GND_113 GND_55 AL11 RV17 1 2 150_0402_1% AM39 DP_VSSR_30 AV17
J2 GND_114 GND_56 AL14 DPEF_CALR DP_VSSR_31 AR18
J27 GND_115 GND_57 AL17 DP_VSSR_32 AN38
J6 GND_116 GND_58 AL2 DP_VSSR_33 AM35
J8 GND_117 GND_59 AL20 DP_VSSR_34 AN32
K14 GND_118 GND_60 DP_VSSR_35
K7 GND_119 AL23
L11 GND_120 GND_61 AL26
L17 GND_121 GND_62 AL32
L2 GND_122 GND_63 AL6
L22 GND_123 GND_64 AL8
L24 GND_124 GND_65 AM11
L6 GND_125 GND_66 AM31 216-0855000_A0_FCBGA962
M17 GND_126 GND_67 AM9
M22 GND_127 GND_68 AN11
M24 GND_128 GND_69 AN2
N16 GND_129 GND_70 AN30
N18 GND_130 GND_71 AN6
N2 GND_131 GND_72 AN8
N21 GND_132 GND_73 AP11
N23 GND_133 GND_74 AP7
N26 GND_134 GND_75 AP9
B B
N6 GND_135 GND_76 AR5
R15 GND_136 GND_77 B11
R17 GND_137 GND_78 B13
R2 GND_138 GND_79 B15
R20 GND_139 GND_80 B17
R22 GND_140 GND_81 B19
R24 GND_141 GND_82 B21
R27 GND_142 GND_83 B23
R6 GND_143 GND_84 B25
T11 GND_144 GND_85 B27
T13 GND_145 GND_86 B29
T16 GND_146 GND_87 B31
T18 GND_147 GND_88 B33
T21 GND_148 GND_89 B7
T23 GND_149 GND_90 B9
T26 GND_150 GND_91 C1
U15 GND_151 GND_92 C39
U17 GND_153 GND_93 E35
U2 GND_154 GND_94 E5
U20 GND_155 GND_95 F11
U22 GND_156 GND_96 F13
U24 GND_157 GND_97
U27 GND_158
U6 GND_159
V11 GND_160 AG22
V16 GND_161 GND_44
V18 GND_163
V21 GND_164
V23 GND_165
V26 GND_166
W2 GND_167
W6 GND_168
Y15 GND_169
Y17 GND_170
A
Y20 GND_171 A
Y22 GND_172 A39
Y24 GND_173 VSS_MECH_1 AW1
Y27 GND_174 VSS_MECH_2 AW39
GND_175 VSS_MECH_3

216-0855000_A0_FCBGA962 Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 XXXX
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 23 of 81
5 4 3 2 1
 1 2 3 4 5

FBA_MA[15..0] <25,26> FBB_MA[15..0] <27,28>

FBA_BA[2..0] <25,26> FBB_BA[2..0] <27,28>

<25,26> FBA_DQS[7..0] <27,28> FBB_DQS[7..0]

<25,26> FBA_DQM[7..0] <27,28> FBB_DQM[7..0]

<25,26> FBA_DQS#[7..0] <27,28> FBB_DQS#[7..0]

FBA_D[0..63] FBB_D[0..63]
<25,26> FBA_D[0..63] <27,28> FBB_D[0..63]

A A
UV1H UV1I

PART 8 0F 9 PART 9 0F 9
GDDR5/DDR3 GDDR5/DDR3
FBA_D0 C37 G24 FBA_MA0 FBB_D0 C5 P8 FBB_MA0
FBA_D1 C35 DQA0_0 MAA0_0/MAA_0 J23 FBA_MA1 FBB_D1 C3 DQB0_0 MAB0_0 T9 FBB_MA1
FBA_D2 A35 DQA0_1 MAA0_1/MAA_1 H24 FBA_MA2 FBB_D2 E3 DQB0_1 MAB0_1 P9 FBB_MA2
FBA_D3 E34 DQA0_2 MAA0_2/MAA_2 J24 FBA_MA3 FBB_D3 E1 DQB0_2 MAB0_2 N7 FBB_MA3
FBA_D4 G32 DQA0_3 MAA0_3/MAA_3 H26 FBA_MA4 FBB_D4 F1 DQB0_3 MAB0_3 N8 FBB_MA4
FBA_D5 D33 DQA0_4 MAA0_4/MAA_4 J26 FBA_MA5 FBB_D5 F3 DQB0_4 MAB0_4 N9 FBB_MA5
FBA_D6 F32 DQA0_5 MAA0_5/MAA_5 H21 FBA_MA6 FBB_D6 F5 DQB0_5 MAB0_5 U9 FBB_MA6
FBA_D7 E32 DQA0_6 MAA0_6/MAA_6 G21 FBA_MA7 FBB_D7 G4 DQB0_6 MAB0_6 U8 FBB_MA7
DQA0_7 MAA0_7/MAA_7 DQB0_7 MAB0_7

MEMORY INTERFACE A
FBA_D8 D31 H19 FBA_MA8 FBB_D8 H5 Y9 FBB_MA8
FBA_D9 F30 DQA0_8 MAA1_0/MAA_8 H20 FBA_MA9 FBB_D9 H6 DQB0_8 MAB1_0 W9 FBB_MA9
FBA_D10 C30 DQA0_9 MAA1_1/MAA_9 L13 FBA_MA10 FBB_D10 J4 DQB0_9 MAB1_1 AC8 FBB_MA10
FBA_D11 A30 DQA0_10 MAA1_2/MAA_10 G16 FBA_MA11 FBB_D11 K6 DQB0_10 MAB1_2 AC9 FBB_MA11
FBA_D12 F28 DQA0_11 MAA1_3/MAA_11 J16 FBA_MA12 FBB_D12 K5 DQB0_11 MAB1_3 AA7 FBB_MA12
FBA_D13 C28 DQA0_12 MAA1_4/MAA_12 H16 FBA_BA2 FBB_D13 L4 DQB0_12 MAB1_4 AA8 FBB_BA2
FBA_D14 A28 DQA0_13 MAA1_5/MAA_0 J17 FBA_BA0 FBB_D14 M6 DQB0_13 MAB1_5 Y8 FBB_BA0
FBA_D15 E28 DQA0_14 MAA1_6/MAA_1 H17 FBA_BA1 FBB_D15 M1 DQB0_14 MAB1_6 AA9 FBB_BA1
FBA_D16 D27 DQA0_15 MAA1_7/MAA_2 FBB_D16 M3 DQB0_15 MAB1_7

MEMORY INTERFACE B
FBA_D17 F26 DQA0_16 A32 FBA_DQM0 FBB_D17 M5 DQB0_16 H3 FBB_DQM0
FBA_D18 C26 DQA0_17 WCKA0_0/DQMA0_0 C32 FBA_DQM1 FBB_D18 N4 DQB0_17 WCKB0_0 H1 FBB_DQM1
FBA_D19 A26 DQA0_18 WCKA0B_0/DQMA0_1 D23 FBA_DQM2 FBB_D19 P6 DQB0_18 WCKB0B_0 T3 FBB_DQM2
FBA_D20 F24 DQA0_19 WCKA0_1/DQMA0_2 E22 FBA_DQM3 FBB_D20 P5 DQB0_19 WCKB0_1 T5 FBB_DQM3
FBA_D21 C24 DQA0_20 WCKA0B_1/DQMA0_3 C14 FBA_DQM4 FBB_D21 R4 DQB0_20 WCKB0B_1 AE4 FBB_DQM4
+1.5VS_VGA FBA_D22 A24 DQA0_21 WCKA1_0/DQMA1_0 A14 FBA_DQM5 +1.5VS_VGA FBB_D22 T6 DQB0_21 WCKB1_0 AF5 FBB_DQM5
FBA_D23 E24 DQA0_22 WCKA1B_0/DQMA1_1 E10 FBA_DQM6 FBB_D23 T1 DQB0_22 WCKB1B_0 AK6 FBB_DQM6
FBA_D24 C22 DQA0_23 WCKA1_1/DQMA1_2 D9 FBA_DQM7 FBB_D24 U4 DQB0_23 WCKB1_1 AK5 FBB_DQM7
FBA_D25 A22 DQA0_24 WCKA1B_1/DQMA1_3 FBB_D25 V6 DQB0_24 WCKB1B_1
FBA_D26 F22 DQA0_25 C34 FBA_DQS0 FBB_D26 V1 DQB0_25 F6 FBB_DQS0
DQA0_26 EDCA0_0/QSA0_0 DQB0_26 EDCB0_0
1

1
FBA_D27 D21 D29 FBA_DQS1 FBB_D27 V3 K3 FBB_DQS1
RV18 FBA_D28 A20 DQA0_27 EDCA0_1/QSA0_1 D25 FBA_DQS2 RV19 FBB_D28 Y6 DQB0_27 EDCB0_1 P3 FBB_DQS2
B
40.2_0402_1% FBA_D29 F20 DQA0_28 EDCA0_2/QSA0_2 E20 FBA_DQS3 40.2_0402_1% FBB_D29 Y1 DQB0_28 EDCB0_2 V5 FBB_DQS3 B
CHA@ FBA_D30 D19 DQA0_29 EDCA0_3/QSA0_3 E16 FBA_DQS4 CHB@ FBB_D30 Y3 DQB0_29 EDCB0_3 AB5 FBB_DQS4
FBA_D31 E18 DQA0_30 EDCA1_0/QSA1_0 E12 FBA_DQS5 FBB_D31 Y5 DQB0_30 EDCB1_0 AH1 FBB_DQS5
2

2
FBA_D32 C18 DQA0_31 EDCA1_1/QSA1_1 J10 FBA_DQS6 FBB_D32 AA4 DQB0_31 EDCB1_1 AJ9 FBB_DQS6
CV73 FBA_D33 A18 DQA1_0 EDCA1_2/QSA1_2 D7 FBA_DQS7 CV74 FBB_D33 AB6 DQB1_0 EDCB1_2 AM5 FBB_DQS7
FBA_D34 F18 DQA1_1 EDCA1_3/QSA1_3 FBB_D34 AB1 DQB1_1 EDCB1_3
FBA_D35 D17 DQA1_2 A34 FBA_DQS#0 FBB_D35 AB3 DQB1_2 G7 FBB_DQS#0
DQA1_3 DDBIA0_0/QSA0_0B DQB1_3 DDBIB0_0
1

1
1U_0402_10V6-K

1U_0402_10V6-K
1 FBA_D36 A16 E30 FBA_DQS#1 1 FBB_D36 AD6 K1 FBB_DQS#1
RV20 FBA_D37 F16 DQA1_4 DDBIA0_1/QSA0_1B E26 FBA_DQS#2 RV21 FBB_D37 AD1 DQB1_4 DDBIB0_1 P1 FBB_DQS#2
100_0402_5% FBA_D38 D15 DQA1_5 DDBIA0_2/QSA0_2B C20 FBA_DQS#3 100_0402_5% FBB_D38 AD3 DQB1_5 DDBIB0_2 W4 FBB_DQS#3
DQA1_6 DDBIA0_3/QSA0_3B DQB1_6 DDBIB0_3
CHA@

CHB@
CHA@ FBA_D39 E14 C16 FBA_DQS#4 CHB@ FBB_D39 AD5 AC4 FBB_DQS#4
2 FBA_D40 F14 DQA1_7 DDBIA1_0/QSA1_0B C12 FBA_DQS#5 2 FBB_D40 AF1 DQB1_7 DDBIB1_0 AH3 FBB_DQS#5
2

2
FBA_D41 D13 DQA1_8 DDBIA1_1/QSA1_1B J11 FBA_DQS#6 FBB_D41 AF3 DQB1_8 DDBIB1_1 AJ8 FBB_DQS#6
FBA_D42 F12 DQA1_9 DDBIA1_2/QSA1_2B F8 FBA_DQS#7 FBB_D42 AF6 DQB1_9 DDBIB1_2 AM3 FBB_DQS#7
FBA_D43 A12 DQA1_10 DDBIA1_3/QSA1_3B FBB_D43 AG4 DQB1_10 DDBIB1_3
FBA_D44 D11 DQA1_11 J21 FBA_ODTA0 FBB_D44 AH5 DQB1_11 T7 FBB_ODTA0
DQA1_12 ADBIA0/ODTA0 FBA_ODTA0 <25> DQB1_12 ADBIB0 FBB_ODTA0 <27>
FBA_D45 F10 G19 FBA_ODTA1 FBB_D45 AH6 W7 FBB_ODTA1
DQA1_13 ADBIA1/ODTA1 FBA_ODTA1 <26> DQB1_13 ADBIB1 FBB_ODTA1 <28>
FBA_D46 A10 FBB_D46 AJ4
+1.5VS_VGA FBA_D47 C10 DQA1_14 H27 FBA_CLKA0 +1.5VS_VGA FBB_D47 AK3 DQB1_14 L9 FBB_CLKA0
DQA1_15 CLKA0 FBA_CLKA0 <25> DQB1_15 CLKB0 FBB_CLKA0 <27>
FBA_D48 G13 G27 FBA_CLKA0# FBB_D48 AF8 L8 FBB_CLKA0#
DQA1_16 CLKA0B FBA_CLKA0# <25> DQB1_16 CLKB0B FBB_CLKA0# <27>
FBA_D49 H13 FBB_D49 AF9
FBA_D50 J13 DQA1_17 J14 FBA_CLKA1 FBB_D50 AG8 DQB1_17 AD8 FBB_CLKA1
DQA1_18 CLKA1 FBA_CLKA1 <26> DQB1_18 CLKB1 FBB_CLKA1 <28>
FBA_D51 H11 H14 FBA_CLKA1# FBB_D51 AG7 AD7 FBB_CLKA1#
DQA1_19 CLKA1B FBA_CLKA1# <26> DQB1_19 CLKB1B FBB_CLKA1# <28>
1

1
FBA_D52 G10 FBB_D52 AK9
RV22 FBA_D53 G8 DQA1_20 K23 FBA_RASA0# RV23 FBB_D53 AL7 DQB1_20 T10 FBB_RASA0#
DQA1_21 RASA0B FBA_RASA0# <25> DQB1_21 RASB0B FBB_RASA0# <27>
40.2_0402_1% FBA_D54 K9 K19 FBA_RASA1# 40.2_0402_1% FBB_D54 AM8 Y10 FBB_RASA1#
DQA1_22 RASA1B FBA_RASA1# <26> DQB1_22 RASB1B FBB_RASA1# <28>
CHA@ FBA_D55 K10 CHB@ FBB_D55 AM7
FBA_D56 G9 DQA1_23 K20 FBA_CASA0# FBB_D56 AK1 DQB1_23 W10 FBB_CASA0#
FBA_CASA0# <25> FBB_CASA0# <27>
2

2
FBA_D57 A8 DQA1_24 CASA0B K17 FBA_CASA1# FBB_D57 AL4 DQB1_24 CASB0B AA10 FBB_CASA1#
DQA1_25 CASA1B FBA_CASA1# <26> DQB1_25 CASB1B FBB_CASA1# <28>
CV75 FBA_D58 C8 CV76 FBB_D58 AM6
FBA_D59 E8 DQA1_26 K24 FBA_CSA0# FBB_D59 AM1 DQB1_26 P10 FBB_CSA0#
DQA1_27 CSA0B_0 FBA_CSA0# <25> DQB1_27 CSB0B_0 FBB_CSA0# <27>
FBA_D60 A6 K27 FBB_D60 AN4 L10
DQA1_28 CSA0B_1 DQB1_28 CSB0B_1
1

1
1U_0402_10V6-K

1U_0402_10V6-K
1 FBA_D61 C6 1 FBB_D61 AP3
RV24 FBA_D62 E6 DQA1_29 M13 FBA_CSA1# RV25 FBB_D62 AP1 DQB1_29 AD10 FBB_CSA1#
DQA1_30 CSA1B_0 FBA_CSA1# <26> DQB1_30 CSB1B_0 FBB_CSA1# <28>
C 100_0402_5% FBA_D63 A5 K16 100_0402_5% FBB_D63 AP5 AC10 C
DQA1_31 CSA1B_1 DQB1_31 CSB1B_1
CHA@

CHB@
CHA@ CHB@
2 MVREFDA L18 K21 FBA_CKEA0 2 U10 FBB_CKEA0
FBA_CKEA0 <25> FBB_CKEA0 <27>
2

2
MVREFSA L20 MVREFDA CKEA0 J20 FBA_CKEA1 MVREFDB Y12 CKEB0 AA11 FBB_CKEA1
MVREFSA CKEA1 FBA_CKEA1 <26> MVREFDB CKEB1 FBB_CKEA1 <28>
MVREFSB AA12
L27 K26 FBA_WEA0# MVREFSB N10 FBB_WEA0#
NC_MEM_CALRN0 WEA0B FBA_WEA0# <25> WEB0B FBB_WEA0# <27>
N12 L15 FBA_WEA1# AB11 FBB_WEA1#
NC_MEM_CALRN1 WEA1B FBA_WEA1# <26> WEB1B FBB_WEA1# <28>
AG12
NC_MEM_CALRN2
H23 FBA_MA13 T8 FBB_MA13
RV26 1 CHA@ 2 120_0402_1% M27 MAA0_8/MAA_13 J19 FBA_MA14 MAB0_8 W8 FBB_MA14
MEM_CALRP0 MAA1_8/MAA_14 M21 FBA_MA15 MAB1_8 U12 FBB_MA15
M12 MAA0_9/MAA_15 M20 MAB0_9 V12
AH12 NC_MEM_CALRP1 MAA1_9/NC MAB1_9
NC_MEM_CALRP2 AH11 DRAM_RST
DRAM_RST

216-0855000_A0_FCBGA962
216-0855000_A0_FCBGA962

RV27 CHB@ RV28 CHB@

FBA_RST# 1 2 1 2 DRAM_RST
<25,26,27,28> FBA_RST#
49.9_0402_1% 10_0402_5%

1
1 1
CV77 RV29 CV78
120P_0402_50V8-J 5.1K_0402_5% 68P_0402_50V8-J
CHB@ CHB@ @
2 2

2
D D

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 XXXX
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 24 of 81
1 2 3 4 5
 1 2 3 4 5

Memory Partition A - Lower 32 bits Change all VRAM footprint to MT41K256M16HA107_FBGA_96P-A39P

FBA_MA[15..0] <24,26>
UV4 S2G@ VRAM SWAP
UV3 S2G@ VRAM SWAP FBA_BA[2..0] <24,26>
+FBA_VREFD0 M8 E3 FBA_D18
+FBA_VREFC0 M8 E3 FBA_D29 +FBA_VREFC0 H1 VREFCA DQL0 F7 FBA_D23
VREFCA DQL0 VREFDQ DQL1 FBA_DQS[7..0] <24,26>
+FBA_VREFD0 H1 F7 FBA_D24 F2 FBA_D17
VREFDQ DQL1 F2 FBA_D28 FBA_MA0 N3 DQL2 F8 FBA_D22
A
FBA_MA0 N3 DQL2 F8 FBA_D27 FBA_MA1 P7 A0 DQL3 H3 FBA_D16
Group2 IN1 FBA_DQM[7..0] <24,26> A

FBA_MA1 P7 A0 DQL3 H3 FBA_D25

Group3 BOT FBA_MA2 P3 A1 DQL4 H8 FBA_D21
A1 DQL4 A2 DQL5 FBA_DQS#[7..0] <24,26>
FBA_MA2 P3 H8 FBA_D26 FBA_MA3 N2 G2 FBA_D19
FBA_MA3 N2 A2 DQL5 G2 FBA_D31 FBA_MA4 P8 A3 DQL6 H7 FBA_D20
A3 DQL6 A4 DQL7 FBA_D[0..63] <24,26>
FBA_MA4 P8 H7 FBA_D30 FBA_MA5 P2
FBA_MA5 P2 A4 DQL7 FBA_MA6 R8 A5
FBA_MA6 R8 A5 FBA_MA7 R2 A6 D7 FBA_D13
FBA_MA7 R2 A6 D7 FBA_D3 FBA_MA8 T8 A7 DQU0 C3 FBA_D10
FBA_MA8 T8 A7 DQU0 C3 FBA_D6 FBA_MA9 R3 A8 DQU1 C8 FBA_D15
FBA_MA9 R3 A8 DQU1 C8 FBA_D1 FBA_MA10 L7 A9 DQU2 C2 FBA_D9
FBA_MA10 L7 A9 DQU2 C2 FBA_D4 FBA_MA11 R7 A10/AP DQU3 A7 FBA_D14
Group1 TOP
FBA_MA11 R7 A10/AP DQU3 A7 FBA_D2
Group0 IN3 FBA_MA12 N7 A11 DQU4 A2 FBA_D8
FBA_MA12 N7 A11 DQU4 A2 FBA_D7 FBA_MA13 T3 A12/BC DQU5 B8 FBA_D12
FBA_MA13 T3 A12/BC DQU5 B8 FBA_D0 FBA_MA14 T7 A13 DQU6 A3 FBA_D11
FBA_MA14 T7 A13 DQU6 A3 FBA_D5 A14 DQU7
A14 DQU7 +1.5VS_VGA
+1.5VS_VGA
FBA_BA0 M2 B2
FBA_BA0 M2 B2 FBA_BA1 N8 BA0 VDD_1 D9
FBA_BA1 N8 BA0 VDD_1 D9 FBA_BA2 M3 BA1 VDD_2 G7
FBA_BA2 M3 BA1 VDD_2 G7 BA2 VDD_3 K2 +1.5VS_VGA +1.5VS_VGA
BA2 VDD_3 K2 VDD_4 K8
VDD_4 K8 VDD_5 N1
VDD_5 VDD_6

1
N1 FBA_CLKA0 J7 N9
FBA_CLKA0 J7 VDD_6 N9 FBA_CLKA0# K7 CK VDD_7 R1 RV30 RV31
<24> FBA_CLKA0 CK VDD_7 CK VDD_8
FBA_CLKA0# K7 R1 FBA_CKEA0 K9 R9 4.99K_0402_1% 4.99K_0402_1%
<24> FBA_CLKA0# CK VDD_8 CKE VDD_9
FBA_CKEA0 K9 R9 CHA@ CHA@
<24> FBA_CKEA0 CKE VDD_9

2
FBA_ODTA0 K1 A1 CV79 +FBA_VREFC0 CV80 +FBA_VREFD0
FBA_ODTA0 K1 A1 FBA_CSA0# L2 ODT VDDQ_1 A8
<24> FBA_ODTA0 ODT VDDQ_1 CS VDDQ_2

0.1U_0402_10V7-K

0.1U_0402_10V7-K
FBA_CSA0# L2 A8 FBA_RASA0# J3 C1
<24> FBA_CSA0# CS VDDQ_2 RAS VDDQ_3

1
FBA_RASA0# J3 C1 FBA_CASA0# K3 C9 1 1
<24> FBA_RASA0# RAS VDDQ_3 CAS VDDQ_4
FBA_CASA0# K3 C9 FBA_WEA0# L3 D2 RV32 RV33
<24> FBA_CASA0# CAS VDDQ_4 WE VDDQ_5
FBA_WEA0# L3 D2 E9 4.99K_0402_1% 4.99K_0402_1%
B <24> FBA_WEA0# WE VDDQ_5 VDDQ_6 B

CHA@

CHA@
E9 F1 CHA@ CHA@
VDDQ_6 F1 FBA_DQS2 F3 VDDQ_7 H2 2 2

2
FBA_DQS3 F3 VDDQ_7 H2 FBA_DQS1 C7 DQSL VDDQ_8 H9
Vram Swap FBA_DQS0 C7 DQSL VDDQ_8 H9 DQSU VDDQ_9
DQSU VDDQ_9
FBA_DQM2 E7 A9
FBA_DQM3 E7 A9 FBA_DQM1 D3 DML VSS_1 B3
FBA_DQM0 D3 DML VSS_1 B3 DMU VSS_2 E1
DMU VSS_2 E1 VSS_3 G8
VSS_3 G8 FBA_DQS#2 G3 VSS_4 J2
FBA_DQS#3 G3 VSS_4 J2 FBA_DQS#1 B7 DQSL VSS_5 J8
FBA_DQS#0 B7 DQSL VSS_5 J8 DQSU VSS_6 M1
DQSU VSS_6 M1 VSS_7 M9
VSS_7 M9 VSS_8 P1
VSS_8 P1 FBA_RST# T2 VSS_9 P9
FBA_RST# T2 VSS_9 P9 RESET VSS_10 T1
<24,26,27,28> FBA_RST# RESET VSS_10 VSS_11
T1 L8 T9
L8 VSS_11 T9 ZQ VSS_12
ZQ VSS_12
J1 B1
NC1 VSSQ_1
1

1
J1 B1 L1 B9
RV36 RV37 L1 NC1 VSSQ_1 B9 RV38 J9 NC2 VSSQ_2 D1
10K_0402_5% 243_0402_1% J9 NC2 VSSQ_2 D1 243_0402_1% L9 NC3 VSSQ_3 D8
@ CHA@ L9 NC3 VSSQ_3 D8 CHA@ FBA_MA15 M7 NC4 VSSQ_4 E2
FBA_MA15 M7 NC4 VSSQ_4 E2 NC5 VSSQ_5 E8
2

2
NC5 VSSQ_5 E8 VSSQ_6 F9
VSSQ_6 F9 VSSQ_7 G1
VSSQ_7 G1 VSSQ_8 G9
VSSQ_8 G9 VSSQ_9
VSSQ_9 96-BALL
96-BALL SDRAM DDR3
SDRAM DDR3 K4W4G1646D-BC1A_FBGA96
K4W4G1646D-BC1A_FBGA96

C C

FBA_CLKA0

+1.5VS_VGA UV6 SIDE +1.5VS_VGA UV7 SIDE

1
CV83 CV84 CV85 CV86 CV87 CV88 CV89 CV90 CV91 CV92 CV93 CV94 RV41
40.2_0402_1%
10U_0603_6.3V6-M

10U_0603_6.3V6-M

CHA@
1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1 1 1 1 1 1 1 1 1 1 1 1

2
CV95 CHA@
1 2
CHA@

CHA@

CHA@

CHA@

CHA@

CHA@

CHA@

CHA@

CHA@

CHA@

CHA@

CHA@

2 2 2 2 2 2 2 2 2 2 2 2 .01U_0402_16V7-K

1
RV42
40.2_0402_1%
CHA@

2
+1.5VS_VGA UV6 SIDE +1.5VS_VGA UV7 SIDE
FBA_CLKA0#
CV96 CV97 CV98 CV99 CV100 CV101 CV102 CV103 CV104 CV105
0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

1 1 1 1 1 1 1 1 1 1
CHA@

CHA@

CHA@

CHA@

CHA@

CHA@

CHA@

CHA@

CHA@

CHA@

2 2 2 2 2 2 2 2 2 2

D D

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 XXXX
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 25 of 81
1 2 3 4 5
 1 2 3 4 5

Memory Partition A - Upper 32 bits

UV5 S2G@ Vram Swap FBA_MA[15..0] <24,25>
UV6 S2G@ Vram Swap
+FBA_VREFC1 M8 E3 FBA_D51
VREFCA DQL0 FBA_BA[2..0] <24,25>
+FBA_VREFD1 H1 F7 FBA_D52 +FBA_VREFD1 M8 E3 FBA_D38
VREFDQ DQL1 F2 FBA_D48 +FBA_VREFC1 H1 VREFCA DQL0 F7 FBA_D34
A A
DQL2 VREFDQ DQL1 FBA_DQS[7..0] <24,25>
FBA_MA0 N3 F8 FBA_D53 F2 FBA_D39
FBA_MA1 P7 A0 DQL3 H3 FBA_D49
Group6 BOT FBA_MA0 N3 DQL2 F8 FBA_D36
FBA_MA2 P3 A1 DQL4 H8 FBA_D54 FBA_MA1 P7 A0 DQL3 H3 FBA_D35
Group4 IN1 FBA_DQM[7..0] <24,25>
FBA_MA3 N2 A2 DQL5 G2 FBA_D50 FBA_MA2 P3 A1 DQL4 H8 FBA_D33
A3 DQL6 A2 DQL5 FBA_DQS#[7..0] <24,25>
FBA_MA4 P8 H7 FBA_D55 FBA_MA3 N2 G2 FBA_D37
FBA_MA5 P2 A4 DQL7 FBA_MA4 P8 A3 DQL6 H7 FBA_D32
A5 A4 DQL7 FBA_D[0..63] <24,25>
FBA_MA6 R8 FBA_MA5 P2
FBA_MA7 R2 A6 D7 FBA_D61 FBA_MA6 R8 A5
FBA_MA8 T8 A7 DQU0 C3 FBA_D57 FBA_MA7 R2 A6 D7 FBA_D43
FBA_MA9 R3 A8 DQU1 C8 FBA_D63 FBA_MA8 T8 A7 DQU0 C3 FBA_D44
FBA_MA10 L7 A9 DQU2 C2 FBA_D58 FBA_MA9 R3 A8 DQU1 C8 FBA_D41
FBA_MA11 R7 A10/AP DQU3 A7 FBA_D60
Group7 IN3 FBA_MA10 L7 A9 DQU2 C2 FBA_D46
FBA_MA12 N7 A11 DQU4 A2 FBA_D56 FBA_MA11 R7 A10/AP DQU3 A7 FBA_D42
Group5 TOP
FBA_MA13 T3 A12/BC DQU5 B8 FBA_D62 FBA_MA12 N7 A11 DQU4 A2 FBA_D45
FBA_MA14 T7 A13 DQU6 A3 FBA_D59 FBA_MA13 T3 A12/BC DQU5 B8 FBA_D40
A14 DQU7 FBA_MA14 T7 A13 DQU6 A3 FBA_D47
+1.5VS_VGA A14 DQU7 +1.5VS_VGA +1.5VS_VGA
+1.5VS_VGA
FBA_BA0 M2 B2
BA0 VDD_1

1
FBA_BA1 N8 D9 FBA_BA0 M2 B2 RV43
FBA_BA2 M3 BA1 VDD_2 G7 FBA_BA1 N8 BA0 VDD_1 D9 RV44
BA2 VDD_3 K2 FBA_BA2 M3 BA1 VDD_2 G7 4.99K_0402_1% 4.99K_0402_1%
VDD_4 K8 BA2 VDD_3 K2 CHA@ CHA@
VDD_5 N1 VDD_4 K8

2
FBA_CLKA1 J7 VDD_6 N9 VDD_5 N1 CV106 +FBA_VREFC1 CV107 +FBA_VREFD1
<24> FBA_CLKA1 CK VDD_7 VDD_6
FBA_CLKA1# K7 R1 FBA_CLKA1 J7 N9
<24> FBA_CLKA1# CK VDD_8 CK VDD_7

0.1U_0402_10V7-K

0.1U_0402_10V7-K
FBA_CKEA1 K9 R9 FBA_CLKA1# K7 R1
<24> FBA_CKEA1 CKE VDD_9 CK VDD_8

1
FBA_CKEA1 K9 R9 1 1
CKE VDD_9 RV45 RV46
FBA_ODTA1 K1 A1 4.99K_0402_1% 4.99K_0402_1%
<24> FBA_ODTA1 ODT VDDQ_1

CHA@

CHA@
FBA_CSA1# L2 A8 FBA_ODTA1 K1 A1 CHA@ CHA@
<24> FBA_CSA1# CS VDDQ_2 ODT VDDQ_1 2 2
FBA_RASA1# J3 C1 FBA_CSA1# L2 A8
<24> FBA_RASA1#

2
FBA_CASA1# K3 RAS VDDQ_3 C9 FBA_RASA1# J3 CS VDDQ_2 C1
<24> FBA_CASA1# CAS VDDQ_4 RAS VDDQ_3
FBA_WEA1# L3 D2 FBA_CASA1# K3 C9
B <24> FBA_WEA1# WE VDDQ_5 CAS VDDQ_4 B
E9 FBA_WEA1# L3 D2
VDDQ_6 F1 WE VDDQ_5 E9
FBA_DQS6 F3 VDDQ_7 H2 VDDQ_6 F1
FBA_DQS7 C7 DQSL VDDQ_8 H9 FBA_DQS4 F3 VDDQ_7 H2
DQSU VDDQ_9 FBA_DQS5 C7 DQSL VDDQ_8 H9
Vram Swap DQSU VDDQ_9
Vram Swap
FBA_DQM6 E7 A9
FBA_DQM7 D3 DML VSS_1 B3 FBA_DQM4 E7 A9
DMU VSS_2 E1 FBA_DQM5 D3 DML VSS_1 B3
VSS_3 G8 DMU VSS_2 E1
FBA_DQS#6 G3 VSS_4 J2 VSS_3 G8
FBA_DQS#7 B7 DQSL VSS_5 J8 FBA_DQS#4 G3 VSS_4 J2
DQSU VSS_6 M1 FBA_DQS#5 B7 DQSL VSS_5 J8
VSS_7 M9 DQSU VSS_6 M1
VSS_8 P1 VSS_7 M9
FBA_RST# T2 VSS_9 P9 VSS_8 P1
<24,25,27,28> FBA_RST# RESET VSS_10 VSS_9
T1 FBA_RST# T2 P9
L8 VSS_11 T9 RESET VSS_10 T1
ZQ VSS_12 L8 VSS_11 T9
ZQ VSS_12
1

J1 B1
NC1 VSSQ_1

1
RV51 L1 B9 J1 B1
243_0402_1% J9 NC2 VSSQ_2 D1 RV52 L1 NC1 VSSQ_1 B9
CHA@ L9 NC3 VSSQ_3 D8 243_0402_1% J9 NC2 VSSQ_2 D1
FBA_MA15 M7 NC4 VSSQ_4 E2 CHA@ L9 NC3 VSSQ_3 D8
2

NC5 VSSQ_5 E8 FBA_MA15 M7 NC4 VSSQ_4 E2

2
VSSQ_6 F9 NC5 VSSQ_5 E8
VSSQ_7 G1 VSSQ_6 F9
VSSQ_8 G9 VSSQ_7 G1
VSSQ_9 VSSQ_8 G9
96-BALL VSSQ_9
SDRAM DDR3 96-BALL
K4W4G1646D-BC1A_FBGA96 SDRAM DDR3 FBA_CLKA1
K4W4G1646D-BC1A_FBGA96
C C

1
RV53
40.2_0402_1%
CHA@
+1.5VS_VGA UV8 SIDE +1.5VS_VGA UV9 SIDE

2
CV110 CHA@
CV111 CV112 CV113 CV114 CV115 CV116 CV117 CV118 CV119 CV120 CV121 CV122 1 2
10U_0603_6.3V6-M

10U_0603_6.3V6-M

.01U_0402_16V7-K

1
1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1 1 1 1 1 1 1 1 1 1 1 1
RV54
40.2_0402_1%
CHA@

CHA@

CHA@

CHA@

CHA@

CHA@

CHA@

CHA@

CHA@

CHA@

CHA@

CHA@

CHA@
2 2 2 2 2 2 2 2 2 2 2 2

2
FBA_CLKA1#

+1.5VS_VGA UV8 SIDE +1.5VS_VGA UV9 SIDE

CV123 CV124 CV125 CV126 CV127 CV128 CV129 CV130 CV131 CV132
0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

1 1 1 1 1 1 1 1 1 1
CHA@

CHA@

CHA@

CHA@

CHA@

CHA@

CHA@

CHA@

CHA@

CHA@

2 2 2 2 2 2 2 2 2 2

D D

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 XXXX
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 26 of 81
1 2 3 4 5
 1 2 3 4 5

Memory Partition A - Lower 32 bits

FBB_MA[15..0] <24,28>
UV8 S2G@
UV7 S2G@ Vram Swap FBB_BA[2..0] <24,28>
+FBB_VREFD0 M8 E3 FBB_D17
+FBB_VREFC0 M8 E3 FBB_D31 +FBB_VREFC0 H1 VREFCA DQL0 F7 FBB_D18
VREFCA DQL0 VREFDQ DQL1 FBB_DQS[7..0] <24,28>
+FBB_VREFD0 H1 F7 FBB_D24 F2 FBB_D22
VREFDQ DQL1 F2 FBB_D30 FBB_MA0 N3 DQL2 F8 FBB_D23
A
FBB_MA0 N3 DQL2 F8 FBB_D26 FBB_MA1 P7 A0 DQL3 H3 FBB_D16
Group2 IN1 FBB_DQM[7..0] <24,28> A

FBB_MA1 P7 A0 DQL3 H3 FBB_D28

Group3 BOT FBB_MA2 P3 A1 DQL4 H8 FBB_D20
A1 DQL4 A2 DQL5 FBB_DQS#[7..0] <24,28>
FBB_MA2 P3 H8 FBB_D25 FBB_MA3 N2 G2 FBB_D19
FBB_MA3 N2 A2 DQL5 G2 FBB_D29 FBB_MA4 P8 A3 DQL6 H7 FBB_D21
A3 DQL6 A4 DQL7 FBB_D[0..63] <24,28>
FBB_MA4 P8 H7 FBB_D27 FBB_MA5 P2
FBB_MA5 P2 A4 DQL7 FBB_MA6 R8 A5
FBB_MA6 R8 A5 FBB_MA7 R2 A6 D7 FBB_D13
FBB_MA7 R2 A6 D7 FBB_D3 FBB_MA8 T8 A7 DQU0 C3 FBB_D10
FBB_MA8 T8 A7 DQU0 C3 FBB_D5 FBB_MA9 R3 A8 DQU1 C8 FBB_D15
FBB_MA9 R3 A8 DQU1 C8 FBB_D2 FBB_MA10 L7 A9 DQU2 C2 FBB_D11
FBB_MA10 L7 A9 DQU2 C2 FBB_D4 FBB_MA11 R7 A10/AP DQU3 A7 FBB_D12
Group1 TOP
FBB_MA11 R7 A10/AP DQU3 A7 FBB_D1
Group0 IN3 FBB_MA12 N7 A11 DQU4 A2 FBB_D9
FBB_MA12 N7 A11 DQU4 A2 FBB_D7 FBB_MA13 T3 A12/BC DQU5 B8 FBB_D14
FBB_MA13 T3 A12/BC DQU5 B8 FBB_D0 FBB_MA14 T7 A13 DQU6 A3 FBB_D8
FBB_MA14 T7 A13 DQU6 A3 FBB_D6 A14 DQU7
A14 DQU7 +1.5VS_VGA
+1.5VS_VGA
FBB_BA0 M2 B2
FBB_BA0 M2 B2 FBB_BA1 N8 BA0 VDD_1 D9
FBB_BA1 N8 BA0 VDD_1 D9 FBB_BA2 M3 BA1 VDD_2 G7
FBB_BA2 M3 BA1 VDD_2 G7 BA2 VDD_3 K2 +1.5VS_VGA +1.5VS_VGA
BA2 VDD_3 K2 VDD_4 K8
VDD_4 K8 VDD_5 N1
VDD_5 VDD_6

1
N1 FBB_CLKA0 J7 N9
FBB_CLKA0 J7 VDD_6 N9 FBB_CLKA0# K7 CK VDD_7 R1 RV55 RV56
<24> FBB_CLKA0 CK VDD_7 CK VDD_8
FBB_CLKA0# K7 R1 FBB_CKEA0 K9 R9 4.99K_0402_1% 4.99K_0402_1%
<24> FBB_CLKA0# CK VDD_8 CKE VDD_9
FBB_CKEA0 K9 R9 CHB@ CHB@
<24> FBB_CKEA0 CKE VDD_9

2
FBB_ODTA0 K1 A1 CV133 +FBB_VREFC0 CV134 +FBB_VREFD0
FBB_ODTA0 K1 A1 FBB_CSA0# L2 ODT VDDQ_1 A8
<24> FBB_ODTA0 ODT VDDQ_1 CS VDDQ_2

0.1U_0402_10V7-K

0.1U_0402_10V7-K
FBB_CSA0# L2 A8 FBB_RASA0# J3 C1
<24> FBB_CSA0# CS VDDQ_2 RAS VDDQ_3

1
FBB_RASA0# J3 C1 FBB_CASA0# K3 C9 1 1
<24> FBB_RASA0# RAS VDDQ_3 CAS VDDQ_4
FBB_CASA0# K3 C9 FBB_WEA0# L3 D2 RV57 RV58
<24> FBB_CASA0# CAS VDDQ_4 WE VDDQ_5
FBB_WEA0# L3 D2 E9 4.99K_0402_1% 4.99K_0402_1%
B <24> FBB_WEA0# WE VDDQ_5 VDDQ_6 B

CHB@

CHB@
E9 F1 CHB@ CHB@
VDDQ_6 F1 FBB_DQS2 F3 VDDQ_7 H2 2 2

2
FBB_DQS3 F3 VDDQ_7 H2 FBB_DQS1 C7 DQSL VDDQ_8 H9
Vram Swap FBB_DQS0 C7 DQSL VDDQ_8 H9 DQSU VDDQ_9
DQSU VDDQ_9
FBB_DQM2 E7 A9
FBB_DQM3 E7 A9 FBB_DQM1 D3 DML VSS_1 B3
FBB_DQM0 D3 DML VSS_1 B3 DMU VSS_2 E1
DMU VSS_2 E1 VSS_3 G8
VSS_3 G8 FBB_DQS#2 G3 VSS_4 J2
FBB_DQS#3 G3 VSS_4 J2 FBB_DQS#1 B7 DQSL VSS_5 J8
FBB_DQS#0 B7 DQSL VSS_5 J8 DQSU VSS_6 M1
DQSU VSS_6 M1 VSS_7 M9
VSS_7 M9 VSS_8 P1
VSS_8 P1 FBA_RST# T2 VSS_9 P9
FBA_RST# T2 VSS_9 P9 RESET VSS_10 T1
<24,25,26,28> FBA_RST# RESET VSS_10 VSS_11
T1 L8 T9
L8 VSS_11 T9 ZQ VSS_12
ZQ VSS_12
J1 B1
NC1 VSSQ_1
1

1
J1 B1 L1 B9
RV61 RV62 L1 NC1 VSSQ_1 B9 RV63 J9 NC2 VSSQ_2 D1
10K_0402_5% 243_0402_1% J9 NC2 VSSQ_2 D1 243_0402_1% L9 NC3 VSSQ_3 D8
@ CHB@ L9 NC3 VSSQ_3 D8 CHB@ FBB_MA15 M7 NC4 VSSQ_4 E2
FBB_MA15 M7 NC4 VSSQ_4 E2 NC5 VSSQ_5 E8
2

2
NC5 VSSQ_5 E8 VSSQ_6 F9
VSSQ_6 F9 VSSQ_7 G1
VSSQ_7 G1 VSSQ_8 G9
VSSQ_8 G9 VSSQ_9
VSSQ_9 96-BALL
96-BALL SDRAM DDR3
SDRAM DDR3 K4W4G1646D-BC1A_FBGA96
K4W4G1646D-BC1A_FBGA96

C C

FBB_CLKA0

+1.5VS_VGA UV6 SIDE +1.5VS_VGA UV7 SIDE

1
CV137 CV138 CV139 CV140 CV141 CV142 CV143 CV144 CV145 CV146 CV147 CV148 RV66
40.2_0402_1%
10U_0603_6.3V6-M

10U_0603_6.3V6-M

CHB@
1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1 1 1 1 1 1 1 1 1 1 1 1

2
CV149 CHB@
1 2
CHB@

CHB@

CHB@

CHB@

CHB@

CHB@

CHB@

CHB@

CHB@

CHB@

CHB@

CHB@

2 2 2 2 2 2 2 2 2 2 2 2 .01U_0402_16V7-K

1
RV67
40.2_0402_1%
CHB@

2
+1.5VS_VGA UV6 SIDE +1.5VS_VGA UV7 SIDE
FBB_CLKA0#
CV150 CV151 CV152 CV153 CV154 CV155 CV156 CV157 CV158 CV159
0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

1 1 1 1 1 1 1 1 1 1
CHB@

CHB@

CHB@

CHB@

CHB@

CHB@

CHB@

CHB@

CHB@

CHB@

2 2 2 2 2 2 2 2 2 2

D D

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 XXXX
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 27 of 81
1 2 3 4 5
 5 4 3 2 1

Memory Partition A - Upper 32 bits

D UV9 S2G@ Vram Swap D
UV10 S2G@ Vram Swap FBB_MA[15..0] <24,27>
+FBB_VREFC1 M8 E3 FBB_D51
+FBB_VREFD1 H1 VREFCA DQL0 F7 FBB_D55 +FBB_VREFD1 M8 E3 FBB_D38
VREFDQ DQL1 VREFCA DQL0 FBB_BA[2..0] <24,27>
F2 FBB_D50 +FBB_VREFC1 H1 F7 FBB_D35
FBB_MA0 N3 DQL2 F8 FBB_D53 VREFDQ DQL1 F2 FBB_D36
FBB_MA1 P7 A0 DQL3 H3 FBB_D48
Group6 BOT FBB_MA0 N3 DQL2 F8 FBB_D33
FBB_DQS[7..0] <24,27>
FBB_MA2 P3 A1 DQL4 H8 FBB_D52 FBB_MA1 P7 A0 DQL3 H3 FBB_D37
Group4 IN1
A2 DQL5 A1 DQL4 FBB_DQM[7..0] <24,27>
FBB_MA3 N2 G2 FBB_D49 FBB_MA2 P3 H8 FBB_D32
FBB_MA4 P8 A3 DQL6 H7 FBB_D54 FBB_MA3 N2 A2 DQL5 G2 FBB_D39
A4 DQL7 A3 DQL6 FBB_DQS#[7..0] <24,27>
FBB_MA5 P2 FBB_MA4 P8 H7 FBB_D34
FBB_MA6 R8 A5 FBB_MA5 P2 A4 DQL7
A6 A5 FBB_D[0..63] <24,27>
FBB_MA7 R2 D7 FBB_D44 FBB_MA6 R8
FBB_MA8 T8 A7 DQU0 C3 FBB_D43 FBB_MA7 R2 A6 D7 FBB_D56
FBB_MA9 R3 A8 DQU1 C8 FBB_D45 FBB_MA8 T8 A7 DQU0 C3 FBB_D60
FBB_MA10 L7 A9 DQU2 C2 FBB_D42 FBB_MA9 R3 A8 DQU1 C8 FBB_D57
FBB_MA11 R7 A10/AP DQU3 A7 FBB_D46
Group5 TOP FBB_MA10 L7 A9 DQU2 C2 FBB_D62
FBB_MA12 N7 A11 DQU4 A2 FBB_D41 FBB_MA11 R7 A10/AP DQU3 A7 FBB_D59
Group7 IN3
FBB_MA13 T3 A12/BC DQU5 B8 FBB_D47 FBB_MA12 N7 A11 DQU4 A2 FBB_D63
FBB_MA14 T7 A13 DQU6 A3 FBB_D40 FBB_MA13 T3 A12/BC DQU5 B8 FBB_D58 +1.5VS_VGA +1.5VS_VGA
A14 DQU7 FBB_MA14 T7 A13 DQU6 A3 FBB_D61
+1.5VS_VGA A14 DQU7

1
+1.5VS_VGA RV68
FBB_BA0 M2 B2 RV69
FBB_BA1 N8 BA0 VDD_1 D9 FBB_BA0 M2 B2 4.99K_0402_1% 4.99K_0402_1%
FBB_BA2 M3 BA1 VDD_2 G7 FBB_BA1 N8 BA0 VDD_1 D9 CHB@ CHB@
BA2 VDD_3 K2 FBB_BA2 M3 BA1 VDD_2 G7

2
VDD_4 K8 BA2 VDD_3 K2 CV160 +FBB_VREFC1 CV161 +FBB_VREFD1
VDD_5 N1 VDD_4 K8
VDD_6 VDD_5

0.1U_0402_10V7-K

0.1U_0402_10V7-K
FBB_CLKA1 J7 N9 N1
<24> FBB_CLKA1 CK VDD_7 VDD_6

1
FBB_CLKA1# K7 R1 FBB_CLKA1 J7 N9 1 1
<24> FBB_CLKA1# CK VDD_8 CK VDD_7
FBB_CKEA1 K9 R9 FBB_CLKA1# K7 R1 RV70 RV71
<24> FBB_CKEA1 CKE VDD_9 CK VDD_8
FBB_CKEA1 K9 R9 4.99K_0402_1% 4.99K_0402_1%
CKE VDD_9

CHB@

CHB@
CHB@ CHB@
FBB_ODTA1 K1 A1 2 2
<24> FBB_ODTA1

2
C
FBB_CSA1# L2 ODT VDDQ_1 A8 FBB_ODTA1 K1 A1 C
<24> FBB_CSA1# CS VDDQ_2 ODT VDDQ_1
FBB_RASA1# J3 C1 FBB_CSA1# L2 A8
<24> FBB_RASA1# RAS VDDQ_3 CS VDDQ_2
FBB_CASA1# K3 C9 FBB_RASA1# J3 C1
<24> FBB_CASA1# CAS VDDQ_4 RAS VDDQ_3
FBB_WEA1# L3 D2 FBB_CASA1# K3 C9
<24> FBB_WEA1# WE VDDQ_5 CAS VDDQ_4
E9 FBB_WEA1# L3 D2
VDDQ_6 F1 WE VDDQ_5 E9
FBB_DQS6 F3 VDDQ_7 H2 VDDQ_6 F1
Vram Swap FBB_DQS5 C7 DQSL VDDQ_8 H9 FBB_DQS4 F3 VDDQ_7 H2
DQSU VDDQ_9 Vram Swap FBB_DQS7 C7 DQSL VDDQ_8 H9
DQSU VDDQ_9
FBB_DQM6 E7 A9
FBB_DQM5 D3 DML VSS_1 B3 FBB_DQM4 E7 A9
DMU VSS_2 E1 FBB_DQM7 D3 DML VSS_1 B3
VSS_3 G8 DMU VSS_2 E1
FBB_DQS#6 G3 VSS_4 J2 VSS_3 G8
FBB_DQS#5 B7 DQSL VSS_5 J8 FBB_DQS#4 G3 VSS_4 J2
DQSU VSS_6 M1 FBB_DQS#7 B7 DQSL VSS_5 J8
VSS_7 M9 DQSU VSS_6 M1
VSS_8 P1 VSS_7 M9
FBA_RST# T2 VSS_9 P9 VSS_8 P1
<24,25,26,27> FBA_RST# RESET VSS_10 VSS_9
T1 FBA_RST# T2 P9
L8 VSS_11 T9 RESET VSS_10 T1
ZQ VSS_12 L8 VSS_11 T9
ZQ VSS_12
1

J1 B1
NC1 VSSQ_1

1
RV76 L1 B9 J1 B1
243_0402_1% J9 NC2 VSSQ_2 D1 RV77 L1 NC1 VSSQ_1 B9
CHB@ L9 NC3 VSSQ_3 D8 243_0402_1% J9 NC2 VSSQ_2 D1
FBB_MA15 M7 NC4 VSSQ_4 E2 CHB@ L9 NC3 VSSQ_3 D8
2

NC5 VSSQ_5 E8 FBB_MA15 M7 NC4 VSSQ_4 E2

2
VSSQ_6 F9 NC5 VSSQ_5 E8
VSSQ_7 G1 VSSQ_6 F9
VSSQ_8 G9 VSSQ_7 G1
VSSQ_9 VSSQ_8 G9
96-BALL VSSQ_9 FBB_CLKA1
B B
SDRAM DDR3 96-BALL
K4W4G1646D-BC1A_FBGA96 SDRAM DDR3

1
K4W4G1646D-BC1A_FBGA96
RV78
40.2_0402_1%
CHB@

2
CV164 CHB@
+1.5VS_VGA UV8 SIDE +1.5VS_VGA UV9 SIDE 1 2

CV165 CV166 CV167 CV168 CV169 CV170 CV171 CV172 CV173 CV174 CV175 CV176 .01U_0402_16V7-K

1
10U_0603_6.3V6-M

10U_0603_6.3V6-M

RV79
1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K 40.2_0402_1%
1 1 1 1 1 1 1 1 1 1 1 1
CHB@

2
CHB@

CHB@

CHB@

CHB@

CHB@

CHB@

CHB@

CHB@

CHB@

CHB@

CHB@

CHB@

2 2 2 2 2 2 2 2 2 2 2 2 FBB_CLKA1#

+1.5VS_VGA UV8 SIDE +1.5VS_VGA UV9 SIDE

CV177 CV178 CV179 CV180 CV181 CV182 CV183 CV184 CV185 CV186
0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

1 1 1 1 1 1 1 1 1 1
CHB@

CHB@

CHB@

CHB@

CHB@

CHB@

CHB@

CHB@

CHB@

CHB@

2 2 2 2 2 2 2 2 2 2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/12/05 Deciphered Date 2014/12/05 XXXX
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 28 of 81
5 4 3 2 1
 5 4 3 2 1

+1.05VS to +0.95VS_VGA +1.5VS to +1.5VS_VGA

Rds(on) < 7.5mohm (Vgs = 4.5V)
+5VS +1.05VS +1.05VS_VGA

QV9 DIS@
Rds(on) < 7.5mohm (Vgs = 4.5V)
D
AO4430L_SO8
400 mils D

8 1
7 2 +5VS +1.5VS +1.5VGA

1
+5VALW 6 3
RV152 5 QV16 DIS@
10K_0402_5% 1 1 AO4430L_SO8
DIS@ CV163 CV187 8 1

2
4.7U_0603_6.3V6-K 0.1U_0402_10V7-K 7 2

1
RV143 DIS@ @ +5VALW 6 3
1

300_0402_5% 2 2 RV157 5

2
RV151 DIS@ 20K_0402_5% 1 1
100K_0402_5% RV141 DIS@ CV190 CV191

2
DIS@ 4.7U_0603_6.3V6-K 0.1U_0402_10V7-K

2
0_0402_5% RV154 DIS@ @
2

1
300_0402_5% 2 2

2
+0.95VS_VGA_GATE D RV150 RV156 DIS@
QV11 2 2 1 +0.95VS_VGA_EN# 100K_0402_5% RV153

1
2N7002WT1G_1N_SC-70-3 G DIS@
D
1

SB00000YY00 S 10K_0402_5% 0_0402_5%

2
+0.95VS_VGA_EN# 2 QV10 1 DIS@ DIS@

1
G 2N7002WT1G_1N_SC-70-3 CV162 +1.5VS_VGA_GATE D RV155
S SB00000YY00 0.22U_0402_10V6-K QV13 2 2 1 +1.5VS_VGA_EN#
3

DIS@ DIS@ 2N7002WT1G_1N_SC-70-3 G

D D
1

1
2 SB00000YY00 S 10K_0402_5%

3
VGA_ON 2 QV12 +1.5VS_VGA_EN# 2 QV14 1 DIS@ DIS@
G 2N7002WT1G_1N_SC-70-3 G 2N7002WT1G_1N_SC-70-3 CV188
S SB00000YY00 RV169 1 @ 2 0_0402_5% S SB00000YY00 0.22U_0402_10V6-K
<11,76> DGPU_PWROK
3

3
DIS@ DIS@ DIS@
D

1
2
VGA_ON RV168 1 2 0_0402_5% 2 QV15
G 2N7002WT1G_1N_SC-70-3
S SB00000YY00

3
JV1 @ DIS@
+1.05VS_VGA 1 2 +0.95VS_VGA
C 1 2 C
JUMP_43X118

JV3 @
1 2
+1.5VGA 1 2 +1.5VS_VGA
JUMP_43X118

JV5 @
1 2
1 2
JUMP_43X118

+3VS to +3VS_VGA

+5VALW +3VS QV6 +3VS_VGA

AO3413_SOT23-3
DIS@
JV4 @
1

3 1 1 2
RV161 1 2
B B
DIS@ JUMP_43X39
47K_0402_5%
G
2

2
2

RV162
DIS@
2

470_0402_5%
RV163
1

DIS@
10K_0402_5%
1

DGPU_PWREN# D RV164
QV7 2 2 1 DGPU_PWREN#
2N7002WT1G_1N_SC-70-3 G
1

RV165 D SB00000YY00 10K_0402_5%

1 S
3

VGA_ON 1 2 2 QV8 CV228 DIS@ DIS@

<11,20,72,76,77> VGA_ON
G 2N7002WT1G_1N_SC-70-3 DIS@
1

0_0402_5% S SB00000YY00 .01U_0402_16V7-K

3

RV166 DIS@ 2
@
100K_0402_5%
2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/12/05 Deciphered Date 2014/12/05 XXXX
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 29 of 81
5 4 3 2 1
 5 4 3 2 1

D D

BLANK
C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/09/07 Deciphered Date 2014/09/07 XXXX

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 30 of 81
5 4 3 2 1
 5 4 3 2 1

D D

BLANK
C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/09/07 Deciphered Date 2014/09/07 XXXX

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 31 of 81
5 4 3 2 1
 5 4 3 2 1

DV12 +DV33_18 AV12

20 mils 20 mils 20 mils
CW1 CW2 CW3 CW4
4.7U_0603_6.3V6-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K
1 1 1 1

1U_0402_10V6-K
D D
40 mils UW1

11 30 SD_CD#
2 2 2 2 +3VS 3V3_IN SD_CD#
18 31
+DV33_18 DV33_18 MS_INS#
AV12 10 32 RW20 2 1 10K_0402_5%
AV12 WAKE# +3VS
RW3 1 2 0_0603_5% DV12 14
DV12S
All of cap. close to chip DV12 connects with AV12, due
to DV12 need a external input. 15 SD_DATA1_R RW4 1 2 0_0402_5% SD_DATA1
SP1
12 16 SD_DATA0_MS_DATA1_R RW5 1 2 0_0402_5% SD_DATA0_MS_DATA1
+CRD_POWER Card_3V3 SP2 EMC@
+3VS +3V3_AUX 17 SD_CLK_MS_DATA0_R RW6 1 2 0_0402_5% SD_CLK_MS_DATA0 CW11 1 2 5P_0402_50V9-C
RW18 1 2 0_0402_5% +3V3_AUX 27 SP3
40 mils 40 mils +3VS 3V3aux 19 SD_CMD_MS_DATA2_R RW7 1 2 SD_CMD_MS_DATA2
CW5 CW6 CW7 CW8
375mA SP4
0_0402_5%

RW8 1 2 6.2K_0402_1% 9 20 SD_MS_DATA3_R RW9 1 2 0_0402_5% SD_MS_DATA3

Close to chip 12mils, lengths < 200mils RREF SP5
10U_0603_6.3V6-M

0.1U_0402_10V7-K

0.1U_0402_10V7-K

4.7U_0603_6.3V6-K

1 1 1 1
21 SD_DATA2_MS_CLK_R RW10 1 2 0_0402_5% SD_DATA2_MS_CLK
SP6
PCIE6_CTX_C_DRX_P 3 29 SD_WP For EMI, please close to the chip
2 2 2 2 <7> PCIE6_CTX_C_DRX_P HSIP SP7
Close to chip
PCIE6_CTX_C_DRX_N 4
<7> PCIE6_CTX_C_DRX_N HSIN
CW9 1 2 0.1U_0402_10V7-K PCIE6_CRX_C_DTX_P 7
<7> PCIE6_CRX_DTX_P HSOP
CW10 1 2 0.1U_0402_10V7-K PCIE6_CRX_C_DTX_N 8 13
<7> PCIE6_CRX_DTX_N HSON NC_1
Close to pin 11 Close to pin 27 22
C NC_2 C
CLK_PCIE_CR 5 23
<8> CLK_PCIE_CR REFCLKP NC_3
CLK_PCIE_CR# 6 24
<8> CLK_PCIE_CR# REFCLKN NC_4
25
NC_5
PLTRST#_NEAR 1 26
<10,47,9> PLTRST#_NEAR PERST# NC_6

CLKREQ_PCIE5_CR# 2
<8> CLKREQ_PCIE5_CR# CLK_REQ#

+3VS RW11 1 2 10K_0402_5% 28 33 GND

GPIO GND

RTS5227E-GRT_QFN32_4X4

+3VS
+3VS

for Edge 15''

1
+CRD_POWER @

1
@ RW12
JREAD2
40 mils ME@ RW13 100K_0402_5%
100K_0402_5%
SD_CMD_MS_DATA2 2

2
B 3 CMD B

2
4 VSS1
SD_CLK_MS_DATA0 5 VDD SD_CD#_R RW14 1 2 SD_CD# SD_WP_R RW15 1 2 SD_WP
6 CLK
VSS2
10U_0603_6.3V6-M
0.1U_0402_10V7-K

SD_DATA0_MS_DATA1 7 0_0402_5% 0_0402_5%

1 1 DAT0
CW13

SD_DATA1 8
DAT1
CW12

SD_DATA2_MS_CLK 9
SD_MS_DATA3 1 DAT2
2 2 CD/DAT3

SD_WP_R 10
SD_CD#_R 11 W/P
12 C/D
13 GND1
GND2
Close to JREAD1.
SUYIN_250312HB011M106ZL

EMC_NS@ EMC_NS@
SD_CLK_MS_DATA0 RW16 1 2 10_0402_5% CW14 1 2 10P_0402_50V8-J

RW16 and CW14reserved for EMI.

Please close to conn.

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/09/07 Deciphered Date 2014/09/07 XXXX

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 32 of 81
5 4 3 2 1
 5 4 3 2 1

D D

BLANK
(Move to sub board)
C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/09/07 Deciphered Date 2014/09/07 XXXX

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 33 of 81
5 4 3 2 1
 5 4 3 2 1

CABLE +3VALW +5VALW

JU3LC
24
G4

1
23
22 G3 R233 R234
21 G2 100K_0402_5%
G1 100K_0402_5%
USB3P4_RXN 20 @ @
<13> USB3P4_RXN 20
USB3P4_RXP 19
<13> USB3P4_RXP

2
18 19
D
EMC_NS@
DOCKING USB3P4_TXN 17 18
D
<13> USB3P4_TXN 17
R163 1 2 0_0402_5% USB3P4_TXP 16 ONEDOCK_DET#
<13> USB3P4_TXP 16 ONEDOCK_DET# <12>
15
DOCK_TX1- 14 15
<42> DOCK_TX1- 14

2
L5 EMC@ DOCK_TX1+ 13
<42> DOCK_TX1+ 13
USB20_N2_COAX 1 2 USB20_N2_COAX_CON 12 R235
1 2 DOCK_TX0- 11 12
<42> DOCK_TX0- 11 0_0402_5%
DOCK_TX0+ 10 @
<42> DOCK_TX0+ 10
USB20_P2_COAX 4 3 USB20_P2_COAX_CON 9

1
4 3 DOCK_AUX# 8 9
<42> DOCK_AUX# 8
DLW21SN900HQ2L_4P DOCK_AUX 7
<42> DOCK_AUX 7
SM070003100 6
USB20_N3 5 6
<13> USB20_N3 5
R164 1 2 0_0402_5%
DOCKNG USB20_P3 4
<13> USB20_P3 4 +5VALW
EMC_NS@ 3
USB20_N2_COAX_CON 2 3
USB20_P2_COAX_CON 1 2
SUB/B 1
ACES_50406-02071-001
ME@
1 1
C171 C172
@ @
.01U_0402_16V7-K 1U_0402_6.3VA-K
2 2

USB20_N2 R169 1 2 0_0402_5% USB20_N2_COAX

<13> USB20_N2

FFC
JU3LF
C C
1
USB_OC2# 2 1
<13> USB_OC2# 2
USB_ON# 3
<40,62> USB_ON# 3
4
EC_SMB_DA3 5 4
<21,55,62,9> EC_SMB_DA3 5
EC_SMB_CK3 6
<21,55,9> EC_SMB_CK3 6
USB20_P2 R171 1 2 0_0402_5% USB20_P2_COAX 7
<13> USB20_P2 7
DOCKDP_HPD 8 DOCKDP_HPD
<42> DOCKDP_HPD 8
DOCK_CONSUMP 9
<67> DOCK_CONSUMP 9
ONEDOCK_DET# 10
LID_SW# 11 10
<51,62> LID_SW# 11
ON/OFF# 12
<50,62> ON/OFF# 12

1
+5VALW 13
14 13 R108
15 14
15 100K_0402_5%
16
16 @
17
1. AC Capacitor place on Sub/B

2
18 17
+5VS 18 2. Need to check with MUX IC vendor
+3VS 19
20 19 whether still need AC cap between MUX IC and device.
+3VL 20
21
22 GND1
GND2

HIGHS_FC5AF201-1151H
ME@

B B
+3VS

R106 1 @ 2 100K_0402_5% DOCK_AUX#

R107 1 @ 2 100K_0402_5% DOCK_AUX

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/09/07 Deciphered Date 2014/09/07 XXXX
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 34 of 81
5 4 3 2 1
 A B C D E

+3VS

+5VS
1
RA1 +1.8V_LDO LDO 1V8 +1.65V_LDO VREF 1V65 +3V_LDO LDO 3V3 CA1
0.1U_0402_10V7-K
C3505 close Pin7
1 2 CA2 CA3 CA4 CA5 +5VS_CLASSD
2
0_0805_5%

4.7U_0603_10V6-K

4.7U_0603_10V6-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K
1 1 1 1

CA6

CA7

CA8

CA9

CA10
1 1
2 1 1 1 1 1
CA11
2 2 2 2

0.1U_0402_10V7-K

4.7U_0603_10V6-K

0.1U_0402_10V7-K

1U_0402_6.3VA-K

0.1U_0402_10V7-K
2.2U_0402_6.3V6-M
1 2 2 2 2 2 +3VS

RA28 1 2 0_0402_5% +3VS_VDDO

X5R CAP X5R CAP
1
CA12
Close to Pin13,16 0.1U_0402_10V7-K
2 CA12 close Pin2
+3VL
RA30 1 2 0_0805_5%

+3VALW
+3V_AVDD_HP RA2 1 @ 2 0_0805_5%
12/3 For PH noise

+3VS
1
UA1 RA3 2 @ 1 0_0805_5%
CA13
PCH_HDA_RST# 9 3 1U_0402_6.3VA-K
<7> PCH_HDA_RST# RESET# FILT_1.8V +1.8V_LDO 2
7
VDD_IO 2
+3VS_VDDIO C3537 close Pin24
VDDO_3.3 +3VS_VDDO
PCH_HDA_BCLK 5 18
<7> PCH_HDA_BCLK BIT_CLK DVDD_3.3 +3VS_DVDD
PCH_HDA_SYNC 8 27
<7> PCH_HDA_SYNC SYNC AVDD_3.3 +3V_LDO
29
VREF_1.65V +1.65V_LDO +3VS_DVDD +3VS
PCH_HDA_SDIN0 RA5 1 2 33_0402_5% PCH_HDA_SDIN0_R 6 28
2 <7> PCH_HDA_SDIN0 SDATA_IN AVDD_5V +5VS_AVDD 2
PCH_HDA_SDOUT 4 RA4 0_0805_5%
<7> PCH_HDA_SDOUT SDATA_OUT 1 2
<36> PC_BEEP
PC_BEEP 10
PC_BEEP
CX20751-11Z LEFT+
12 SPK_L2+
SPK_L2+ <36>
SPKR_MUTE# 39 14 SPK_L1-
SPKR_MUTE# LEFT- SPK_L1- <36> X5R CAP, Please Close Pin18
JSENSE 38 17 SPK_R2+
<36> JSENSE 37 JSENSE RIGHT+ 15 SPK_R2+ <36>
SPK_R1- 1
GPIO1/PORTC_R_MIC RIGHT- SPK_R1- <36>
EMC@ 36 35 CA14
DMIC_CLK RA7 1 2 33_0402_5% MIC_CLK_R 40 MUSIC_REQ/GPIO0/PORTC_L_MIC MICBIASC 34 1U_0402_6.3VA-K
<38> DMIC_CLK DMIC_CLK/MUSIC_REQ/GPIO0 MICBIASB +MICBIASB 2
DMIC_DATA 1
<38> DMIC_DATA DMIC_DAT/GPIO1 33 PORTB_R
PORTB_R_LINE 32 PORTB_R <36>
PORTB_L
1 2 0.1U_0402_10V7-K 11 PORTB_L_LINE PORTB_L <36>
+5VS_CLASSD CA16
CLASS-D_REF 30 EXT_MIC_A
13 PORTD_A_MIC 31 EXT_MIC_B EXT_MIC_A <36> Apple --> EXT_MIC_A, HGNDB
LPWR_5.0 PORTD_B_MIC EXT_MIC_B <36>
W= 80mils 16
RPWR_5.0 25 HGNDA
Nokia --> EXT_MIC_B, HGNDA +5VS_AVDD +5VS
1 2 1U_0402_6.3VA-K 19 HGNDA 26 HGNDA <36,54>
CA17 HGNDB RA6 0_0805_5%
20 FLY_P HGNDB HGNDB <36,54> 1 2
FLY_N 24
AVDD_HP +3V_AVDD_HP
+AVEE 21
+AVEE AVEE 23 HP_OUTR 1
41 PORTA_R 22 HP_OUTR <36>
HP indicate 1 HP_OUTL
GND PORTA_L HP_OUTL <36>
CA18 CA15
Should be 1U_0402_6.3VA-K
+3VS_VDDO 2.2U_0402_6.3V6-M 2
2 connect to CX20751-21Z_QFN40_5X5
GNDA CX20751-21Z
SA00005ZT0J Please Close Pin28
38 31
GND 1 AGND
3 3
1

RA29 DGND
21
47K_0402_5% 11
DA5
2

EC_MUTE# 1 2 SPKR_MUTE#
<62> EC_MUTE# +3VS_VDDIO
RB751V-40_SOD323-2 RA25 1 @ 2 0_0402_5%
+3VS
RA27 1 2 0_0402_5% +3VS_VDDIO
+3V_PCH

1
CA42
4.7U_0603_10V6-K
2

EMI, close to UA1 RF, close to RA7

EMC_NS@
CA42 close Pin7
RA26
PCH_HDA_BCLK_C 1 2 PCH_HDA_BCLK DMIC_CLK
1
CA41 33_0402_5%
1
CA40
W= 300mils
EMC_NS@ EMC@ EMC_NS@
22P_0402_50V8-J 150P_0402_50V8-J CA19 1 2 0.1U_0402_10V7-K
2 2

4 4
PCH_HDA_RST# PCH_HDA_SYNC PCH_HDA_SDOUT DMIC_DATA GND GNDA
1
1 1 1 CA43
CA37 CA38 CA39 RF_NS@
EMC_NS@ EMC_NS@ EMC_NS@ 47P_0402_50V8-J
22P_0402_50V8-J 22P_0402_50V8-J 22P_0402_50V8-J 2
2 2 2
Security Classification LC Future Center Secret Data Title

Issued Date 2013/09/07 Deciphered Date 2014/09/07 XXXX

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 35 of 81
A B C D E
 5 4 3 2 1

D PC Beep Speaker OUT SPK CONN. D

CA22 1 @ 2 0.1U_0402_10V7-K
Need Lenght Match ME update PN
EMC@ JSPK ME@
SPK_L1- RA8 1 2 BLM18PG221SN1D_2P SPK_L1-_CON SPK_R2+_CON 1
<35> SPK_L1- SPK_R1-_CON 2 1
EMC@
DA1 SPK_L2+ RA9 1 2 BLM18PG221SN1D_2P SPK_L2+_CON SPK_L2+_CON 3 2
EC Beep 2 <35> SPK_L2+
EMC@ SPK_L1-_CON 4 3
<62> BEEP# 4
CA24 SPK_R1- RA10 1 2 BLM18PG221SN1D_2P SPK_R1-_CON
1 1 RA11 2 1 2 PC_BEEP <35> SPK_R1- 5
EMC@
PC_BEEP <35> GND1
PCH Beep SPK_R2+ RA12 1 2 BLM18PG221SN1D_2P SPK_R2+_CON 6
3 33_0402_5% <35> SPK_R2+ GND2
0.1U_0402_10V7-K
<12> PCH_BEEP
TYCO_2041180-4
BAT54CW_SOT323-3

1
CA23 1 @ 2 0.1U_0402_10V7-K

RA13 EMC@
10K_0402_5% CA25 1 2 470P_0402_50V7-K SPK_L1-_CON
EMC@

2
CA26 1 2 470P_0402_50V7-K SPK_L2+_CON
EMC@
CA27 1 2 470P_0402_50V7-K SPK_R1-_CON
EMC@
CA28 1 2 470P_0402_50V7-K SPK_R2+_CON

EMI parts
C C

Apple --> EXT_MIC_A, HGNDB

EXT. MIC/LINE IN Nokia --> EXT_MIC_B, HGNDA

+3VS

1
EXT_MIC_A RA14 1 2 100_0402_5% CA29 1 2 2.2U_0402_6.3V6-K HGNDB
<35> EXT_MIC_A HGNDB <35,54>
RA18
EXT_MIC_B RA15 1 2 100_0402_5% CA30 1 2 2.2U_0402_6.3V6-K HGNDA 5.11K_0402_1%
<35> EXT_MIC_B HGNDA <35,54>

2
JSENSE RA20 2 1 20K_0402_1% JSENSE_CON
B Changed CA29 & CA30 from 1uF to 2.2uF/X5R <35> JSENSE JSENSE_CON <54> B

to meet Port-D(headset-Mic) THD+N <= -65 dB RA21 2 1 39.2K_0402_1%

HeadPhone/LINE OUT RB751V-40_SOD323-2

RA16 1 2 3K_0402_5% 1 2 DA6
+MICBIASB
SCS00006S00
HP_OUTL RA17 1 2 75_0402_5% HP_OUTL_CON
<35> HP_OUTL HP_OUTL_CON <54>
CA31
PORTB_L 1 RA19 2 1 2
<35> PORTB_L
100_0402_5%
4.7U_0603_10V6-K

RB751V-40_SOD323-2
RA22 1 2 3K_0402_5% 1 2 DA7
+MICBIASB

SCS00006S00
HP_OUTR RA23 1 2 75_0402_5% HP_OUTR_CON
<35> HP_OUTR HP_OUTR_CON <54>
CA32
1 RA24 2 1 2
PORTB_R
<35> PORTB_R
100_0402_5%
4.7U_0603_10V6-K
A A

CA31, CA32 change to 4.7U for Quality requirement

Security Classification LC Future Center Secret Data Title

Issued Date 2013/09/07 Deciphered Date 2014/09/07 XXXX

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 36 of 81
5 4 3 2 1
 5 4 3 2 1

D D

SATA HDD CONN. JHDD2 ME@

1
SATA_PTX_DRX_P0 C24 1 2 .01U_0402_16V7-K SATA_PTX_C_DRX_P0 2 GND1
<7> SATA_PTX_DRX_P0 A+
SATA_PTX_DRX_N0 C25 1 2 .01U_0402_16V7-K SATA_PTX_C_DRX_N0 3
<7> SATA_PTX_DRX_N0 A-
4
SATA_PRX_DTX_N0 C26 1 2 .01U_0402_16V7-K SATA_PRX_C_DTX_N0 5 GND2 +5VS
<7> SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 C27 1 2 .01U_0402_16V7-K SATA_PRX_C_DTX_P0 6 B-
<7> SATA_PRX_DTX_P0 7 B+
GND3
1 1 1 1 1
C19 C20 C21 C22 C23
@ @ @ @
8 10U_0805_10V6-K 10U_0805_10V6-K 1U_0402_10V6-K 0.1U_0402_25V6-K 1000P_0402_50V7-K
+3VS 9 VCC_3V3_1 2 2 2 2 2
DEVSLP0 10 VCC_3V3_2
<12> DEVSLP0 VCC_3V3_3
11
HDD_DETECT# 12 GND4
<62> HDD_DETECT# 13 GND5
14 GND6
+5VS 15 VCC5_1
16 VCC5_2
17 VCC5_3
18 GND7
Pin18 connect to GND for SATA Gen3 19 RESERVED
20 GND8 23
21 VCC12_1 GND9 24
22 VCC12_2 GND10
VCC12_3

C C

ACES_50812-0227P-001

SATA ODD CONN

+5VS TO +5VS_ODD
JODD ME@
1
SATA_PTX_DRX_P1 C164 ODD@1 2 .01U_0402_16V7-K SATA_PTX_C_DRX_P1 2 1
B <7> SATA_PTX_DRX_P1 2 B
<7> SATA_PTX_DRX_N1 SATA_PTX_DRX_N1 C165 ODD@1 2 .01U_0402_16V7-K SATA_PTX_C_DRX_N1 3
4 3
SATA_PRX_DTX_N1 C129 ODD@1 2 .01U_0402_16V7-K SATA_PRX_C_DTX_N1 5 4
<7> SATA_PRX_DTX_N1 SATA_PRX_DTX_P1 C130 ODD@1 2 .01U_0402_16V7-K SATA_PRX_C_DTX_P1 6 5 R154 1 @ 2 0_0805_5%
<7> SATA_PRX_DTX_P1 7 6 14
ODD_DETEC# 8 7 GND1
<7> ODD_DETEC# 8 +5VS +5VS_ODD
9 15
+5VS_ODD 10 9 GND2
80 mils U16 ODD@ 80 mils
R150 1 2 0_0402_5% ODD_DA#_R 11 10 5 1 +5VS_ODD
MCP <12> ODD_DA#
12 11 IN2 OUT
13 12 2
13 1 GND 1
C132 From PCH C131
ACES_50885-0137P-001 ODD@ 4 3 ODD_EN ODD@
IN1 EN ODD_EN <12>
1U_0402_6.3VA-K 4.7U_0603_6.3V6-K
2 G5243AT11U_SOT23-5 2

1
SA00005XJ00
R153
ODD@
100K_0402_5%

2
+5VS_ODD
For RF solution.
Close to JODD connector.
A CRF5 CRF6 A
2200P_0402_50V7-K

47P_0402_50V8-J

RF_NS@ RF_NS@
1 1

2 2
Security Classification LC Future Center Secret Data Title

Issued Date 2013/09/07 Deciphered Date 2014/09/07 XXXX

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 37 of 81
5 4 3 2 1
 5 4 3 2 1

CMOS Camera For 2D CCD

+3VS +3VS_CMOS
2DCCD@
LCDVDD Circuit R17 1 2 0_0402_5% 2W
0.4A
+LCDVDD_CON For RF solution. +5VS +5VS_CMOS For RF solution.
D +3VS For 3D CCD D

W= 60 mil U3 W= 60 mil U4 3DCCD@

5 1 +LCDVDD_CON CRF7 CRF8 5 1 +5VS_CMOS C11 CRF9 CRF10
IN2 OUT IN2 OUT
1 2 1 2
GND GND
From PCH From PCH

4.7U_0603_6.3V6-K

2200P_0402_50V7-K

47P_0402_50V8-J

4.7U_0603_6.3V6-K

2200P_0402_50V7-K

47P_0402_50V8-J
C8 4 3 PCH_ENVDD RF_NS@ RF_NS@ @ C10 4 3 PCH_CMOS_ON @ RF_NS@ RF_NS@
IN1 EN PCH_ENVDD <11> IN1 EN PCH_CMOS_ON <12>
1U_0402_6.3VA-K 1 1 1 1U_0402_6.3VA-K 1 1 1
2 G5243AT11U_SOT23-5 2 G5243AT11U_SOT23-5

1
SA00005XJ00 C9 SA00005XJ00
R18
@ 2 2 2 @ R2 2 2 2
100K_0402_5% 100K_0402_5%

2
C C

eDP CONN.
JLCD ME@
For RF solution. W= 80 mil 1
+LEDVDD 1
2
B+ 3 2
R24 BKOFF# R21 1 2 100K_0402_5% 4 3
2A 80 mil 2A 80 mil 4
1 2 C12 CRF11 CRF12 +LEDVDD R22 1 2 0_0402_5% +3VDMIC W= 40 mil 5
+3VS 5
6
+3VS_CMOS 6
1
4.7U_0805_25V6-K

2200P_0402_50V7-K

47P_0402_50V8-J

0_0805_5% RF_NS@ RF_NS@ W= 60 mil 7

+LCDVDD_CON 7
1 1 1 8 For RF solution.
R26 R25 1 2 2.2K_0402_1% +3VALW_LOGO 9 8
+3VALW 9
100K_0402_5% LOGO_LED# 10
<54,62> LOGO_LED# BKOFF# 11 10 +3VALW_LOGO
<62> BKOFF#
2

2 2 2 PCH_EDP_PWM 12 11
<11> PCH_EDP_PWM 12
13
DMIC_DATA 14 13 CRF13 CRF14
<35> DMIC_DATA 14
DMIC_CLK 15
<35> DMIC_CLK 15

2200P_0402_50V7-K

47P_0402_50V8-J
16 RF_NS@ RF_NS@
USB20_N7_CMOS 17 16
17 1 1
USB20_P7_CMOS 18
EMC_NS@ 19 18
R165 1 2 0_0402_5% CPU_EDP_AUX# C17 1 2 0.1U_0402_10V7-K CPU_EDP_AUX#_CON 20 19
<5> CPU_EDP_AUX# CPU_EDP_AUX 1 2 CPU_EDP_AUX_CON 21 20 2 2
C18 0.1U_0402_10V7-K
<5> CPU_EDP_AUX CPU_EDP_HPD 22 21
L16 EMC_3D@
USB3P3_RXN 1 2 USB3P3_RXN_CON <11> CPU_EDP_HPD 23 22
B <13> USB3P3_RXN 1 2 24 23 B
CPU_EDP_TX1- C13 1 2 0.1U_0402_10V7-K CPU_EDP_TX1-_CON 25 24
USB3P3_RXP 4 3 USB3P3_RXP_CON <5> CPU_EDP_TX1- CPU_EDP_TX1+ 1 2 CPU_EDP_TX1+_CON 26 25
C14 0.1U_0402_10V7-K
<13> USB3P3_RXP 4 3 <5> CPU_EDP_TX1+ 27 26
DLW21SN900HQ2L_4P CPU_EDP_TX0- C15 1 2 0.1U_0402_10V7-K CPU_EDP_TX0-_CON 28 27
<5> CPU_EDP_TX0- CPU_EDP_TX0+ 1 2 CPU_EDP_TX0+_CON 29 28
SM070003100 C16 0.1U_0402_10V7-K
<5> CPU_EDP_TX0+ 30 29
EMC_NS@ 31 30
R166 1 2 0_0402_5% USB3P3_RXN_CON 32 31
USB3P3_RXP_CON 33 32
34 33
For 3D CCD USB3P3_TXN_CON 35 34
USB3P3_TXP_CON 36 35
37 36 41
FW_GPIO 38 37 GND1 42
<12> FW_GPIO 39 38 GND2 43
EMC_NS@
R167 1 2 0_0402_5% 40 39 GND3 44
+5VS_CMOS W= 50 mil 40 GND4
L17 EMC_3D@ I-PEX_20474-040E-12
3DCCD@C28 1 2 0.1U_0402_10V7-K USB3P3_TXN_C 1 2 USB3P3_TXN_CON
<13> USB3P3_TXN 1 2

3DCCD@C29 1 2 0.1U_0402_10V7-K USB3P3_TXP_C 4 3 USB3P3_TXP_CON

<13> USB3P3_TXP 4 3
DLW21SN900HQ2L_4P
SM070003100

EMC_NS@
R168 1 2 0_0402_5%
ESD request
A +3VALW_LOGO CMOS USB Port 2 A

LOGO_LED#

L15 EMC_2D@
3

<13> USB20_N7 USB20_N7 1 2 USB20_N7_CMOS

D1 1 2
EMC@ Title
PESD5V0U2BT_SOT23-3 <13> USB20_P7 USB20_P7 4 3 USB20_P7_CMOS Security Classification LC Future Center Secret Data
4 3
DLW21SN900HQ2L_4P
Issued Date 2013/09/07 Deciphered Date 2014/09/07 XXXX
1

SM070003100
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 38 of 81
5 4 3 2 1
 5 4 3 2 1

D D

BLANK

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/09/07 Deciphered Date 2014/09/07 USB30 RP --> BLANK

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 39 of 81
5 4 3 2 1
 5 4 3 2 1

D D

POWER SWITCH
+5VALW +USB_VCCA

W=80mils W=80mils
U15
1 8
2 GND Vout1 7
3 VIN1 Vout2 6
USB_ON# 4 VIN2 Vout3 5 USB_OC1#
<34,62> USB_ON# EN FLG USB_OC1# <13>
1
C119 G547I2P81U_MSOP8
@ Low Active 2.5A
0.1U_0402_10V6-K
2

C C

+USB_VCCA +USB_VCCA

JUSB2 ME@
USB3P1_TXP_CON 9 1
1 StdA_SSTX+
VBUS 1
USB3P1_TXN_CON 8 + C122 C123
USB20_P0_CON 3 StdA_SSTX-
L9 EMC@ 7 D+ 150U_B2_6.3VM_R35M 470P_0402_50V7-K
USB3P1_TXP C121 1 2 0.1U_0402_10V7-K USB3P1_TXP_C 1 2 USB3P1_TXP_CON USB20_N0_CON 2 GND_DRAIN 10 2 2
<13> USB3P1_TXP 1 2 USB3P1_RXP_CON 6 D- GND_1 11
4 StdA_SSRX+ GND_2 12
USB3P1_TXN C124 1 2 0.1U_0402_10V7-K USB3P1_TXN_C 4 3 USB3P1_TXN_CON USB3P1_RXN_CON 5 GND_5 GND_3 13
<13> USB3P1_TXN 4 3 StdA_SSRX- GND_4
DLW21SN900HQ2L_4P TAITW_PUBAU1-09FNLSCNN4H0
SM070003100

L10 EMC@
USB3P1_RXP 1 2 USB3P1_RXP_CON
<13> USB3P1_RXP 1 2

USB3P1_RXN 4 3 USB3P1_RXN_CON
<13> USB3P1_RXN 4 3
DLW21SN900HQ2L_4P D7 EMC@ D8 RCLAMP0524PATCT_SLP2510P8-10-9
SM070003100 USB20_N0_CON 1 6 USB20_P0_CON

+USB_VCCA
B L11 EMC@ USB3P1_TXP_CON 9 1 USB3P1_TXP_CON B
USB20_P0 1 2 USB20_P0_CON 2 5 USB3P1_TXN_CON 8 2 USB3P1_TXN_CON
<13> USB20_P0 1 2 USB3P1_RXP_CON 7 4 USB3P1_RXP_CON
USB3P1_RXN_CON 6 5 USB3P1_RXN_CON
USB20_N0 4 3 USB20_N0_CON
<13> USB20_N0 4 3 3 4
DLW21SN900HQ2L_4P
SM070003100 CM1293A-04SO_SC-74-6
EMC@

3
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/09/07 Deciphered Date 2014/09/07 USB3 PORT1-BACK

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 40 of 81
5 4 3 2 1
 5 4 3 2 1

+5VALW +5VALW_CHGUSB

D D

U14
1 12
IN OUT 10 USB20P1
USB20_P1 3 DP_IN 11 USB20N1
<13> USB20_P1 USB20_N1 2 DP_OUT DM_IN 14
<13> USB20_N1 DM_OUT GND

9 AOU_IFG# AOU_IFG# <62>

STATUS#
4
USB_OC0# 13 ILIM_SEL
<13> USB_OC0# 5 FAULT#
AOU_EN
<62> AOU_EN EN 15 ILIM_LO R118 1 @ 2 20K_0402_1%
AOU_CTL1 6 ILIM_LO 16 ILIM_HI R120 1 2 20K_0402_1%
<62> AOU_CTL1 CLT1 ILIM_HI
7
AOU_CTL3 8 CLT2 17
<62> AOU_CTL3 CLT3 GND_Pad
TPS2546RTER_QFN16_4X4
1
C173
0.1U_0402_10V7-K
2
@

+5VALW_CHGUSB +5VALW_CHGUSB

JUSB1 ME@
C USB3P2_TXP_CON 9 C
StdA_SSTX+ 1
1 1
USB3P2_TXN_CON 8 VBUS + C126 C125
USB20_P1_CON 3 StdA_SSTX-
L12 EMC@ 7 D+ 150U_B2_6.3VM_R35M 470P_0402_50V7-K
USB3P2_TXP C36 1 2 0.1U_0402_10V7-K USB3P2_TXP_C 1 2 USB3P2_TXP_CON USB20_N1_CON 2 GND_DRAIN 10 2 2
<13> USB3P2_TXP 1 2 6 D- GND_1 11
USB3P2_RXP_CON
4 StdA_SSRX+ GND_2 12
USB3P2_TXN C37 1 2 0.1U_0402_10V7-K USB3P2_TXN_C 4 3 USB3P2_TXN_CON USB3P2_RXN_CON 5 GND_5 GND_3 13
<13> USB3P2_TXN 4 3 StdA_SSRX- GND_4
DLW21SN900HQ2L_4P TAITW_PUBAU1-09FNLSCNN4H0
SM070003100

L13 EMC@
USB3P2_RXP 1 2 USB3P2_RXP_CON
<13> USB3P2_RXP 1 2

USB3P2_RXN 4 3 USB3P2_RXN_CON
<13> USB3P2_RXN 4 3
DLW21SN900HQ2L_4P D10 RCLAMP0524PATCT_SLP2510P8-10-9
SM070003100 D9 EMC@
USB20_N1_CON 1 6 USB20_P1_CON

L14 EMC@ +5VALW_CHGUSB USB3P2_TXP_CON 9 1 USB3P2_TXP_CON

USB20P1 1 2 USB20_P1_CON USB3P2_TXN_CON 8 2 USB3P2_TXN_CON
1 2 2 5 USB3P2_RXP_CON 7 4 USB3P2_RXP_CON
USB3P2_RXN_CON 6 5 USB3P2_RXN_CON
USB20N1 4 3 USB20_N1_CON
4 3
DLW21SN900HQ2L_4P 3 4
SM070003100
B CM1293A-04SO_SC-74-6 EMC@ B

3
TI TPS2546
CLT1 CLT2 CLT3 ILIM_SEL MOD

0 0 0 X DCH OUT held low

1 1 1 1 CDP Data Connected and Port Power Mgt. Function Active

*
* 1 1 1 0 SDP2 Data Connected

* 1 1 0 X SDP1 Data Connected

A
* 0 1 0 X SDP1 Data Connected
A

1 0 0 X DCP_Short Device Forced to stay in DCP BC 1.2 charging mode

1 0 1 X DCP_Divider Device Forced to stay in DCP Divider 1 Charging Mode

Security Classification LC Future Center Secret Data Title

0 1 1 X DCP_Auto Data Disconnected and Port Power Mgt. Function Active
* Issued Date 2013/09/07 Deciphered Date 2014/09/07 USB3 PORT2-FRONT(AOU)
0 0 1 X DCP_Auto Data Disconnected and Power Wake Function Active
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014
JITR1_LA-4141P Sheet 41 of 81
5 4 3 2 1
 A B C D E F G H

+3VS +3VS_DDIMUX
RX1 0_0805_5%
1 2

+3VS_DDIMUX

MUX@ MUX@ MUX@ MUX@

CX11 CX13 CX12 CX14 +3VS_DDIMUX
0.1U_0402_10V7-K

0.1U_0402_10V7-K

.01U_0402_16V7-K

.01U_0402_16V7-K
1 1 1 1
1 1

2 2 2 2

UX1 MUX@

+3VS_DDIMUX 14 8 MUX_PEQ
28 VDD33_1 PEQ
VDD33_2 To MCP
41 5 PCH_MUX_HPD
56 VDD33_3 Out IN_HPD 11 PCH_MUX_HPD <11>
VDD33_4 IN_CA_DET
DDI1_MUX_TX0+ CX4 MUX@1 2 0.1U_0402_10V7-K DDI1_MUX_TX0+_R 3 40 DOCK_TX0+
<5> DDI1_MUX_TX0+ 2 4 IN_D0p DP_D0p 39 DOCK_TX0+ <34>
DDI1_MUX_TX0- CX3 MUX@1 0.1U_0402_10V7-K DDI1_MUX_TX0-_R DOCK_TX0-
<5> DDI1_MUX_TX0- DDI1_MUX_TX1+ 2 DDI1_MUX_TX1+_R 6 IN_D0n DP_D0n 37 DOCK_TX1+ DOCK_TX0- <34>
CX6 MUX@1 0.1U_0402_10V7-K
<5> DDI1_MUX_TX1+ DDI1_MUX_TX1- 2 DDI1_MUX_TX1-_R 7 IN_D1p DP_D1p 36 DOCK_TX1- DOCK_TX1+ <34>
CX5 MUX@1 0.1U_0402_10V7-K
<5> DDI1_MUX_TX1- 2 9 IN_D1n DP_D1n 34 DOCK_TX1- <34>
DDI1_MUX_TX2+ CX8 MUX@1 0.1U_0402_10V7-K DDI1_MUX_TX2+_R
<5> DDI1_MUX_TX2+ DDI1_MUX_TX2- 2 DDI1_MUX_TX2-_R 10 IN_D2P DP_D2p 33
CX7 MUX@1 0.1U_0402_10V7-K
<5> DDI1_MUX_TX2- 2 12 IN_D2n DP_D2n 31
DDI1_MUX_TX3+ CX10MUX@1 0.1U_0402_10V7-K DDI1_MUX_TX3+_R
<5> DDI1_MUX_TX3+ DDI1_MUX_TX3- 2 DDI1_MUX_TX3-_R 13 IN_D3p DP_D3p 30
CX9 MUX@1 0.1U_0402_10V7-K
<5> DDI1_MUX_TX3- IN_D3n DP_D3n
PCH_MUX_CLK 50 55 DOCK_AUX
<11> PCH_MUX_CLK IN_DDC_SCL DP_AUXp_SCL DOCK_AUX <34>
PCH_MUX_DAT 49 54 DOCK_AUX#
<11> PCH_MUX_DAT IN_DDC_SDA DP_AUXn_SDA DOCK_AUX# <34>
MUX_SW 45 16 H_HDMI_TXC+
1 46 SW/SDA_CTL TMDS_CLKp 15 H_HDMI_TXC- H_HDMI_TXC+ <46>
TP74
PD TMDS_CLKn H_HDMI_TXC- <46>
MUX@
PCH_MUX_AUX CX15 1 2 0.1U_0402_10V7-K PCH_MUX_AUX_C 52 19 H_HDMI_TX0+
<11> PCH_MUX_AUX PCH_MUX_AUX# 1 2 PCH_MUX_AUX#_C 51 IN_AUXp TMDS_CH0p 18 H_HDMI_TX0- H_HDMI_TX0+ <46>
CX16 0.1U_0402_10V7-K
<11> PCH_MUX_AUX# IN_AUXn TMDS_CH0n 22 H_HDMI_TX1+ H_HDMI_TX0- <46>
2 MUX_I2C_CTL_EN 38 TMDS_CH1p 21 H_HDMI_TX1- H_HDMI_TX1+ <46> 2
MUX@
I2C_CTL_EN TMDS_CH1n 25 H_HDMI_TX2+ H_HDMI_TX1- <46>
MUX_MODE 53 TMDS_CH2p 24 H_HDMI_TX2- H_HDMI_TX2+ <46>
MODE TMDS_CH2n H_HDMI_TX2- <46>
MUX@
CX2 1 2 2.2U_0402_6.3V6-K 1 48 HDMI_CLK
CEXT TMDS_SCL HDMI_CLK <46>
RX2 1 2 4.99K_0402_1% 27 47 HDMI_DAT
REXT TMDS_SDA HDMI_DAT <46>
MUX@
DOCKDP_HPD 32 20 MUX_PRE
<34> DOCKDP_HPD DP_HPD 3V, Int. PD 150K TMDS_PRE
MUX_CAD 42
DP_CA_DET 23 MUX_RT
MUX_DDCBUF 2 TMDS_RT
HDMI_HPD 17 TMDS_DDCBUF 26
<46> HDMI_HPD TMDS_HPD 5V, Int. PD 150K GND1 35
MUX_CFG0 44 GND2 43
MUX_CFG1 29 DP_CFG0/SCL_CTL GND3 57
DP_CFG1 EPAD

PS8339BQFN56GTR2-A1_QFN56_7X7

3 3

Auto Mode
DP Higher Priolity Pass Through Mode
+3VS_DDIMUX +3VS_DDIMUX +3VS_DDIMUX +3VS_DDIMUX +3VS_DDIMUX +3VS_DDIMUX +3VS_DDIMUX +3VS_DDIMUX +3VS_DDIMUX
4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%
1

1
RX19 RX17 RX16 RX11 RX14 RX9 RX8 RX6 RX3
@ @ @ MUX@ @ @ @ @ @
2

2
MUX_CFG1 MUX_CFG0 MUX_CAD MUX_SW MUX_MODE MUX_I2C_CTL_EN MUX_DDCBUF MUX_RT MUX_PRE MUX_PEQ
4.7K_0402_5%

4.7K_0402_5%

1M_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%
1

1
RX20 RX18 RX21 RX15 RX10 RX13 RX12 RX7 RX5 RX4
@ @ MUX@ MUX@ MUX@ @ MUX@ @ @ @
2

2
4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2013/09/07 Deciphered Date 2014/09/07 XXXX

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 42 of 81
A B C D E F G H
 2 1

+1.35V Defualt ON +VDD12_VDDRX

+3VS +3VS +3VS JVG1 @
1 2
1 2

4.7U_0603_6.3V6-K
RVG1 1 2 0_0603_5% +3VS_DVGA RVG2 1 2 0_0603_5% VDDA33 RVG5 1 2 0_0603_5% VDD33VGA JUMP_43X39 1 1
1 CVG46 CVG47
1 1 1 CVG51 @
CVG2 CVG4 CVG6 @ QVG1 @ 4.7U_0603_6.3V6-K 1U_0402_6.3VA-K
+3VS AO3413_SOT23-3 2 2
1U_0402_6.3VA-K 1U_0402_6.3VA-K 4.7U_0603_6.3V6-K 2
2 2 2

D
3 1

1
RVG42

G
10K_0402_5%

2
@

2
1
QVG2 CVG48

1
RVG36 D LBSS138LT1G_1N_SOT23-3 0.1U_0402_10V6-K
+VDD12_VDDRX +VDD12_VDDRX SUSP# 1 @ 22 @ @
<61,62,69,70,71,76> SUSP# 2
G
10K_0402_5% S

3
RVG3 1 2 0_0603_5% VDD12 RVG4 1 2 0_0603_5% VDDRX

1 1
SB50138002J change to SB00000QO0J.
CVG11 CVG12
2.2U_0402_6.3V6-K 2.2U_0402_6.3V6-K
B 2 2 B

UVG2
VGA_DDC_SDA +3VS
<44> VGA_DDC_SDA 1 40 VGA_DDC_SCL
VGA_SDA VGA_SCL VGA_DDC_SCL <44>
6.65K_0402_1% 1 2 RVG12 RVGA 2 39 VGA_RED
1 2 RVG10 3 RVGA RED 38 VGA_RED <44> 1 2 4.7K_0402_5%
4.99K_0402_1% REXT CSDA RVG7
VDDA33 4 REXT GNDVGA3 37 VGA_GREEN
+3VS_DVGA 5 VDDA33 GREEN 36 VGA_GREEN <44> CSCL 1 2 4.7K_0402_5%
RVG8
CVG15 1 2 0.1U_0402_10V6-K DRX0N 6 VDD33 GNDVGA2 35 VDD33VGA CVG21 1 2 0.1U_0402_10V6-K
<5> DDI2_VGA_TX0- GND1 VDD33VGA
CVG16 1 2 0.1U_0402_10V6-K DRX0P VDD12 7 34 VGA_BLUE
<5> DDI2_VGA_TX0+ VDD12_1 BLUE VGA_BLUE <44>
CVG17 1 2 0.1U_0402_10V6-K DRX1N XTLO 8 33
<5> DDI2_VGA_TX1- XTLO GNDVGA1
CVG22

CVG23

CVG24

CVG25

CVG18 1 2 0.1U_0402_10V6-K DRX1P XTLI 9 32 VGA_HSYNC

<5> DDI2_VGA_TX1+ XTLI VGA_HS VGA_HSYNC <44>
0.1U_0402_10V6-K

0.1U_0402_10V6-K

0.1U_0402_10V6-K

.01U_0402_16V7-K

CVG19 1 2 0.1U_0402_10V6-K AUXN AUXN 10 31 VGA_VSYNC

<11> PCH_VGA_AUX# AUXN VGA_VS VGA_VSYNC <44>
CVG20 1 2 0.1U_0402_10V6-K AUXP 1 1 1 1 AUXP 11 30 VGA_GPIO1
<11> PCH_VGA_AUX AUXP GPIO1 VGA_GPIO1 <44>
DP_HPD 12 29
VDDRX 13 DP_HPD TESTMODE 28 CSDA
RVG111 2 1K_0402_5% DP_HPD DRX0P 14 VDDRX CSDA 27 CSCL
<11> PCH_VGA_HPD 2 2 2 2 DRX0p CSCL +3VS
CVG26

CVG27

DRX0N 15 26 GPIO3/TSCK_O
DRX0n GPIO3/TSCK_O
0.1U_0402_10V6-K

.01U_0402_16V7-K

16 25 VDD12
GND2 VDD12_2

VGA@
1 1 DRX1P 17 24 GPIO0 1 TVG1 PAD
+3VS DRX1p GPIO0

CVG28

CVG29
DRX1N 18 23
DRX1n GND3

2
.01U_0402_16V7-K

0.1U_0402_10V6-K
RST# 19 22 GPIO2/INTRQ 1
PD# 20 RST# GPIO2/INTRQ 21 CFG TVG2 PAD RVG14
2 2 PD# CFG 1 1
1 4.7K_0402_5%
1

VGA@

CVG30 41
EPAD @
RVG13

1
0.1U_0402_10V7-K 2 2
10K_0402_5% 2 GPIO3/TSCK_O
PS8613TQFN40GTR2-A1_TQFN40_5X5
2

2
PD#
RVG15
1 4.7K_0402_5%
CVG31 @

1
1U_0402_6.3VA-K
2

I2C address, 3-state inputs:

A L: 0x50h ~ 0x6Fh (Default) A
M: 0x90h ~ 0xAFh
H: 0x30h ~ 0x4Fh

RVG16 1 2 1M_0402_5%

+3VS

YVG1

XTLI 1 4 CFG RVG9 1 @ 2 4.7K_0402_5%

OSC1 GND2
2 3 XTLO
GND1 OSC2
Initial code loading selection, internal pull down ~80k ohm
27MHZ_10PF_7V27000050
L: Loading initial code from internal MTP ROM
1 1
CVG32 CVG33 H: No initial code loading, external I2C control is expected
15P_0402_50V8-J 15P_0402_50V8-J
2 2

Security Classification LC Future Center Secret Data Title

Issued Date 2013/09/07 Deciphered Date 2014/09/07 XXXX

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 43 of 81
2 1
 5 4 3 2 1

EMC@
LT3 SM01000MC00
<43> VGA_RED R229 1 2 10_0402_1% VGA_RED_R 1 2 VGA_RED_CON
BLM15BB750SN1D

EMC@
LT2 SM01000MC00
<43> VGA_GREEN R230 1 2 10_0402_1% VGA_GREEN_R 1 2 VGA_GREEN_CON
BLM15BB750SN1D

EMC@
LT1 SM01000MC00
<43> VGA_BLUE R231 1 2 10_0402_1% VGA_BLUE_R 1 2 VGA_BLUE_CON
D BLM15BB750SN1D D

75_0402_1%

75_0402_1%

75_0402_1%
1

5P_0402_50V9-C

5P_0402_50V9-C

5P_0402_50V9-C

3P_0402_50V8-C

3P_0402_50V8-C

3P_0402_50V8-C
1 1 1 1 1 1
RT21 RT22 RT23 CT29 CT26 CT24 CT25 CT27 CT28
EMC@ EMC@ EMC@ EMC@ EMC@ EMC@
2 2 2 2 2 2

2
Please Close CRT Connector

RT34
0_0402_5%

紅紅ノBLM18BA100SN1D
1 2

+5VS_HDMI
Follow

Only for 15'

CRT Connector

1
JCRT ME@
LT4 SM01000MC00

OE#
P
VGA_HSYNC 2 4 VGA_HSYNC_1 RT20 1 2 33_0603_5% VGA_HSYNC_2 1 2 VGA_HSYNC_CON 6
<43> VGA_HSYNC A Y NBQ100505T-800Y-N_2P 1 1 11
T25

G
UT3 CT32 VGA_RED_CON 1
C SN74AHCT1G125DCKR_SC70-5 7 C

3
@ 15P_0402_50V8-J VGA_DDC_SDA_CON 12
2 VGA_GREEN_CON 2
8
+5VS_HDMI VGA_HSYNC_CON 13
VGA_BLUE_CON 3
Traslater VGA@ +5VS_HDMI 9
CT31 1 2 0.1U_0402_10V6-K VGA_VSYNC_CON 14 16
1 4 17
VGA_GPIO1_CONN T26 10
5

VGA_DDC_SCL_CON 15
LT5 SM01000MC00 5
OE#
P

VGA_VSYNC 2 4 VGA_VSYNC_1 RT27 1 2 33_0603_5% VGA_VSYNC_2 1 2 VGA_VSYNC_CON

<43> VGA_VSYNC A Y NBQ100505T-800Y-N_2P 1 SUYIN_070546HR015S21BZR
G

UT4 CT33
SN74AHCT1G125DCKR_SC70-5 For CostDown
3

@ 15P_0402_50V8-J
2

RT35
0_0402_5%
1 2

+3VS +5VS_HDMI

DT1 EMC@
VGA_RED_CON 1 6 VGA_BLUE_CON

+5VS_HDMI

1
B RT14 2 5 +5VS_HDMI B
2

QT1A
G

@ 2.2K_0402_5%
2N7002KDWH_SOT363-6

2
VGA_GREEN_CON 3 4
VGA_DDC_SCL 1 6 VGA_DDC_SCL_CON
S

<43> VGA_DDC_SCL
D

CM1293A-04SO_SC-74-6

1 2 DT2 EMC@

1
RT28 0_0402_5% VGA_VSYNC_CON 1 6 VGA_HSYNC_CON
RT13
5

+5VS_HDMI
G

QT1B 2.2K_0402_5%
@ 2 5 +5VS_HDMI
2

2N7002KDWH_SOT363-6
VGA_DDC_SDA 4 3 VGA_DDC_SDA_CON
S

<43> VGA_DDC_SDA
D

+3VS
VGA_DDC_SCL_CON 3 4 VGA_DDC_SDA_CON

CM1293A-04SO_SC-74-6

2
1 2
RT29 0_0402_5% RVG17
VGA@
4.7K_0402_5%

1
VGA@
1 2 VGA_GPIO1_CONN
<43> VGA_GPIO1
RT33 0_0402_5%

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/09/07 Deciphered Date 2014/09/07 XXXX

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 44 of 81
5 4 3 2 1
 5 4 3 2 1

D D

BLANK
C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/09/07 Deciphered Date 2014/09/07 HDMI RP --> BLANK

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 45 of 81
5 4 3 2 1
 5 4 3 2 1

+5VS U2 +5VS_HDMI
L1 EMC@
H_HDMI_TX0- 1 2 HDMI_TX0-_CON 3
<42> H_HDMI_TX0- 1 2 VOUT
1
H_HDMI_TX0+ 4 3 HDMI_TX0+_CON VIN
<42> H_HDMI_TX0+ 4 3 2
DLW21SN900HQ2L_4P GND
SM070003100
G5250Q1T73U SOT23 3P
D D

L2 EMC@
H_HDMI_TX1- 1 2 HDMI_TX1-_CON
<42> H_HDMI_TX1- 1 2

H_HDMI_TX1+ 4 3 HDMI_TX1+_CON
<42> H_HDMI_TX1+ 4 3
DLW21SN900HQ2L_4P
SM070003100

L3 EMC@ HDMI CONN.

H_HDMI_TX2- 1 2 HDMI_TX2-_CON
<42> H_HDMI_TX2- 1 2 JHDMI ME@
HDMI_HPD 19
H_HDMI_TX2+ 4 3 HDMI_TX2+_CON <42> HDMI_HPD 18 HP_DET
<42> H_HDMI_TX2+ 4 3 +5VS_HDMI +5V
17
DLW21SN900HQ2L_4P HDMI_DAT 16 DDC/CEC_GND
<42> HDMI_DAT HDMI_CLK 15 SDA
SM070003100 <42> HDMI_CLK
14 SCL
13 Reserved
L4 EMC@ HDMI_TXC-_CON 12 CEC 20
H_HDMI_TXC- 1 2 HDMI_TXC-_CON 11 CK- GND1 21
<42> H_HDMI_TXC- 1 2 CK_shield GND2
HDMI_TXC+_CON 10 22
HDMI_TX0-_CON 9 CK+ GND3 23
H_HDMI_TXC+ 4 3 HDMI_TXC+_CON 8 D0- GND4
<42> H_HDMI_TXC+ 4 3 D0_shield
HDMI_TX0+_CON 7
DLW21SN900HQ2L_4P HDMI_TX1-_CON 6 D0+
SM070003100 5 D1-
HDMI_TX1+_CON 4 D1_shield
HDMI_TX2-_CON 3 D1+
C 2 D2- C
HDMI_TX2+_CON 1 D2_shield
D2+
CONCR_099ATAC19NBLCNF

+5VS_HDMI

R224 1 2 2.2K_0402_5% HDMI_CLK

R225 1 2 2.2K_0402_5% HDMI_DAT

B B

D12 RCLAMP0524PATCT_SLP2510P8-10-9 D13 RCLAMP0524PATCT_SLP2510P8-10-9

9 1 HDMI_TX1-_CON 9 1 HDMI_TX1-_CON
+5VS_HDMI +5VS_HDMI
HDMI_HPD 8 2 HDMI_HPD HDMI_TX1+_CON 8 2 HDMI_TX1+_CON
HDMI_DAT 7 4 HDMI_DAT HDMI_TX2-_CON 7 4 HDMI_TX2-_CON
HDMI_CLK 6 5 HDMI_CLK HDMI_TX2+_CON 6 5 HDMI_TX2+_CON

EMC@ EMC@

3
D14 RCLAMP0524PATCT_SLP2510P8-10-9

HDMI_TXC-_CON 9 1 HDMI_TXC-_CON
HDMI_TXC+_CON 8 2 HDMI_TXC+_CON
HDMI_TX0-_CON 7 4 HDMI_TX0-_CON
HDMI_TX0+_CON 6 5 HDMI_TX0+_CON

A EMC@ A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/09/07 Deciphered Date 2014/09/07 XXXX

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 46 of 81
5 4 3 2 1
 5 4 3 2 1

+3VALW +3VALW_LAN

For Non-Vpro RL1

1 2

0_0603_5%
+3VM

For Vpro RL2

1 2
D VPRO@ D
0_0603_5%

UL1 NVPRO@

CLKREQ_PCIE3_LAN# 48 13 MDI_0+
<8> CLKREQ_PCIE3_LAN# 36 CLK_REQ_N MDI_PLUS0 14 MDI_0+ <48>
PLTRST#_NEAR MDI_0-
<10,32,9> PLTRST#_NEAR PE_RST_N MDI_MINUS0 MDI_0- <48>
CLK_PCIE_LAN 44 17 MDI_1+
<8> CLK_PCIE_LAN CLK_PCIE_LAN# 45 PE_CLKP MDI_PLUS1 18 MDI_1- MDI_1+ <48>
<8> CLK_PCIE_LAN# PE_CLKN MDI_MINUS1 MDI_1- <48>

PCIE
MDI
PCIE4_CRX_DTX_P CL1 1 2 0.1U_0402_10V7-K PCIE4_CRX_DTX_P_C 38 20 MDI_2+
<13> PCIE4_CRX_DTX_P PETp MDI_PLUS2 MDI_2+ <48>
PCIE4_CRX_DTX_N CL2 1 2 0.1U_0402_10V7-K PCIE4_CRX_DTX_N_C 39 21 MDI_2-
<13> PCIE4_CRX_DTX_N PETn MDI_MINUS2 MDI_2- <48>
PCIE4_CTX_C_DRX_P 41 23 MDI_3+
<13> PCIE4_CTX_C_DRX_P PCIE4_CTX_C_DRX_N 42 PERp MDI_PLUS3 24 MDI_3- MDI_3+ <48>
<13> PCIE4_CTX_C_DRX_N PERn MDI_MINUS3 MDI_3- <48> +3VALW_LAN

PCH_SML0_CLK 28 6
<9> PCH_SML0_CLK PCH_SML0_DAT 31 SMB_CLK SVR_EN_N

SMBUS
<9> PCH_SML0_DAT SMB_DATA 1 1 2
RSVD_VCC3P3_1 RL4 4.7K_0402_5%
RL18 1 2 0_0402_5% LAN_WAKE#_R 2 5
<62> LAN_WAKE# 1 2 LANPHYPC 3 LANWAKE_N VDD3P3_IN
RL17 @ 0_0402_5%
<12> PCH_LAN_WAKE# LAN_DISABLE_N 4
C VDD3P3_4 C
15 1 2 CL3
RJ45_LINKUP# 26 VDD3P3_15 19
<48> RJ45_LINKUP# 27 LED0 VDD3P3_19 29
RJ45_ACTIVITY#
<48> RJ45_ACTIVITY# 25 LED1 VDD3P3_29 1U_0402_6.3VA-K

LED
LED2
47 VCC0R9GBE
VDD0P9_47 46
+3VALW_LAN 1 32 VDD0P9_46 37
T23 1 34 JTAG_TDI VDD0P9_37
1 RL5 2 10K_0402_5% T24 33 JTAG_TDO 43

JTAG
1 RL6 2 10K_0402_5% 35 JTAG_TMS VDD0P9_43
JTAG_TCK 11
VDD0P9_11
LAN_XTALO 9 40
LAN_XTALI 10 XTAL_OUT VDD0P9_40 22
XTAL_IN VDD0P9_22 16
VDD0P9_16 8
30 VDD0P9_8
TEST_EN
12 7 VCC0R9GBE_L LL1 1 2 4.7UH_ LQH32PN4R7NN0L_30% CL4 CL5 CL6 VCC0R9GBE
RBIAS CTRL0P9
49
VSS_EPAD

0.1U_0402_10V7-K

0.1U_0402_10V7-K

22U_0805_6.3V6-M
RL7 RL8 WGI218V-SLK3C-B1_QFN48_6X6 1 @1 2
1K_0402_5% 3.01K_0402_1%

1 Close to FL1
2

2
2 2

LAN_XTALO
UL1 GBE PHY
B B

LAN_XTALI
vPro Model Non-vPro Model
YL1 25MHZ_10PF_8Y25000010

1 3 I218LM I218V
1 3
GND1 GND2
1 2 4 1
15P_0402_50V8-J

15P_0402_50V8-J

ST-1_SWG_SDV-SWG_EC062
CL7 CL8
Add vPro/Non-vPro table.
2 2

+3VALW_LAN
1

RL9
@ 10K_0402_5%
A A
2

LANPHYPC
<12> LANPHYPC

Security Classification LC Future Center Secret Data Title

When use Native function, intel recommend pull high 10K ohm
This part is un-mount in Sting.
Issued Date 2013/09/07 Deciphered Date 2014/09/07 XXXX
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 47 of 81
5 4 3 2 1
 5 4 3 2 1

TL1 EMC@

MDI_0+ 1 1:1
<47> MDI_0+ TD1+ T1/B 24 RJ45_TXD0P
TX1+

MDI_0- 2
<47> MDI_0- TD1-
23 RJ45_TXD0N
TX1-
3 22 MCT1 RL10 2 1 75_0805_5% RJ45_GND
TDCT1 T1/A TXCT1

4 21 MCT2 RL11 2 1 75_0805_5%

D 5 TDCT2 1:1 TXCT2 D
MDI_1+ T1/B
<47> MDI_1+ TD2+ 20 RJ45_TXD1P
TX2+

MDI_1- 6
<47> MDI_1- TD2- 19 RJ45_TXD1N
TX2-

T1/A

MDI_2+ 7 1:1
<47> MDI_2+ TD3+ T1/B 18 RJ45_TXD2P
TX3+
DL3 SURGE@
MDI_2- 8 MCT1 2 1
<47> MDI_2- TD3-
17 RJ45_TXD2N
TX3- LSE-200NX3216TRLF_1206-2
9 16 MCT3 RL12 2 1 75_0805_5%
TDCT3 T1/A TXCT3
DL4 SURGE@
MCT2 2 1
10 15 MCT4 RL13 2 1 75_0805_5%
MDI_3+ 11 TDCT4 1:1 TXCT4
<47> MDI_3+ TD4+ T1/B
14 RJ45_TXD3P LSE-200NX3216TRLF_1206-2
TX4+
1
PATTERN MUST BE DL5 SURGE@
CL9 MCT3 2 1
0.1U_0402_25V6-K MDI_3- 12
SHORT AND WIDE.
2 <47> MDI_3- TD4- 13 RJ45_TXD3N
TX4- LSE-200NX3216TRLF_1206-2
C T1/A DL6 SURGE@ C
MCT4 2 1
CL9 close to LAN Chip BOTHHAND_NA69LF

LSE-200NX3216TRLF_1206-2

ME will change CONN on SDV phase.

RJ-45 Conn.

DL1 RCLAMP0524PATCT_SLP2510P8-10-9 DL2 RCLAMP0524PATCT_SLP2510P8-10-9 RL16 JRJ452 ME@

1 2 9
+3VALW_LAN YellowLED+
510_0402_1% RJ45_ACTIVITY# 10
9 1 9 1 <47> RJ45_ACTIVITY# YellowLED-
MDI_0+ MDI_0+ MDI_2+ MDI_2+
MDI_0- 8 2 MDI_0- MDI_2- 8 2 MDI_2- RJ45_TXD3N 8
MDI_1+ 7 4 MDI_1+ MDI_3+ 7 4 MDI_3+ PR4-
MDI_1- 6 5 MDI_1- MDI_3- 6 5 MDI_3- RJ45_TXD3P 7
PR4+
RJ45_TXD1N 6
PR2-
RJ45_TXD2N 5
EMC@ EMC@ PR3-
3

RJ45_TXD2P 4
PR3+
B RJ45_TXD1P 3 B
PR2+ 14
RJ45_TXD0N 2 GND2
PR1- 13
RJ45_TXD0P 1 GND1
RL15 PR1+
1 2 11
+3VALW_LAN GreenLED+
510_0402_1% RJ45_LINKUP# 12
<47> RJ45_LINKUP# GreenLED-
FOX_JM3611-RS800013-7H

For RF solution.
EMC@
RJ45_GND CL10 1 2 1000P_1808_3KV7k~D LANGND
+3VALW_LAN
1 1
CL11 CL12
EMC@ EMC@
CRF15 CRF16 0.1U_0402_10V6-K .01U_0402_16V7-K
2 2
2200P_0402_50V7-K

47P_0402_50V8-J

RF_NS@ RF_NS@
1 1 LANGND

2 2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/09/07 Deciphered Date 2014/09/07 XXXX

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 48 of 81
5 4 3 2 1
 5 4 3 2 1

D
Click Pad +5VS
Track point D

1
R58 +3VS
R60
0_0603_5% 1 2

2
JCP ME@ 4.7K_0402_5%
1 +5VS JTP ME@
PM_SMB_CLK 2 1 R59 @ TP_DATA2 1
<18,19,9> PM_SMB_CLK 2 1
3 1 2 TP_RESET 2
TP_DATA2 4 3 3 2
TP_CLK2 5 4 4.7K_0402_5% 4 3
PM_SMB_DAT 6 5 5 4
<18,19,9> PM_SMB_DAT 6 5
7 TP_CLK2 6
CP_RESET# 8 7 7 6
<12> CP_RESET# CP_CLK 9 8 13 8 7
<62> CP_CLK CP_DATA 10 9 GND1 9 8
<62> CP_DATA 11 10 14 10 9
TP_REST
<12> TP_REST BYPASS_PAD 12 11 GND2 11 10 13
12 12 11 GND1 14
1 1 12 GND2

2
R61 C44 @ @ C45
4.7K_0402_5% @ 100P_0402_50V8J 100P_0402_50V8J ACES_50506-01201-AT1 JAE_FL10S012HA1
2 2

1
C C

+5VS

R63 1 2 4.7K_0402_5% TP_CLK2 TP_REST R64 1 2 0_0402_5% TP_RESET

R65 1 2 4.7K_0402_5% TP_DATA2

R66 1 @ 2 0_0402_5% BYPASS_PAD
AMD TP_REST has PU

R67 1 2 100K_0402_5% CP_RESET# R105 1 2 0_0402_5%

<11,12> CP_BYPASS

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/09/07 Deciphered Date 2014/09/07 XXXX

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 49 of 81
5 4 3 2 1
 5 4 3 2 1

D D

FAN CONN.
PWR BTN/LID SW CONN.
40mil

R68 1 2 0_0603_5% +VCC_FAN1

+5VS For 14" on board
For 15" on Sub/B
JFAN ME@
1
<62> EC_FAN_PWM 2 1
3 2
<62> EC_FAN_SPEED

簿Sub/B
4 3 6
5 4 G1 7
<62> FAN_ID 5 G2
ACES_85205-05001 ON/OFF Switch -->

惠惠惠AMD惠THERMAL絋絋PIN define
For RF solution.

+VCC_FAN1

C +3VL C
CRF17 CRF18 SW1 DEBUG@
1 3

2200P_0402_50V7-K

47P_0402_50V8-J
RF_NS@ RF_NS@

1
1 1 Power Button 2 4

NTC010-AK1G-B160T_4P R71
100K_0402_5%
2 2

2
J1
Bottom Side 1 2 ON/OFF#
ON/OFF# <34,62>
SHORT PADS
@

FingerPrint CONN.

+3VS

B
<13> USB20_P5
USB20_P5
R70 1
0_0402_5%
2 +3VS_FP 1
2
JFPB
1
ME@ Lid Switch --> 簿Sub/B B
USB20_N5 3 2
<13> USB20_N5 4 3
4
3

1 5
C52 6 5
3

D4 EMC_NS@ FPR@ 6
AZC199-02SPR7G_SOT23-3 0.1U_0402_10V6-K 7
2 GND1
1

8
GND2
1

ACES_88514-0060N-071

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/09/07 Deciphered Date 2014/09/07 XXXX

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 50 of 81
5 4 3 2 1
 5 4 3 2 1

D D

KB CONN
JKB ME@
KSI[0..7] KSI1 32 34
<62> KSI[0..7] KSI7 31 32 GND2 33
KSO[0..17] KSI6 30 31 GND1
<62> KSO[0..17] 29 30
KSO9
KSI4 28 29
KSI5 27 28
KSO0 26 27
KSI2 25 26
KSI3 24 25
KSO5 23 24
KSO1 22 23
KSI0 21 22
KSO2 20 21
KSO4 19 20
KSO7 18 19
KSO8 17 18
KSO6 16 17
KSO3 15 16
KSO12 14 15
KSO13 13 14
KSO14 12 13
KSO11 11 12
KSO10 10 11
KSO15 9 10
R111 1 2 300_0402_5% 8 9
+3VS 8
FN_LED# 7
C <11> FN_LED# F1_LED# 6 7 C
<11> F1_LED# F4_LED# 5 6
<11> F4_LED# KB_FN 4 5
<62> KB_FN 3 4
KSO16 2 3
KSO17 1 2
1
JAE_FL10S032HA1

+3VS +3VS
TOUCH PANEL CONN.

1
R217
TS@
LID_SW# 100K_0402_5%
<34,62> LID_SW#
D11

2
TS@ JTOUCH ME@
R232 @ RB521CS-30GT2RA_VMN2-2 1
0_0402_5% 1 2 TS_OFF# 2 1
1 2 3 2
<11> PCH_TSOFF# 4 3
USB20_N4_TPANEL
<13> USB20_N4_TPANEL USB20_P4_TPANEL 5 4
<13> USB20_P4_TPANEL 6 5
7 6
8 7
B 9 8 B
1 1 9
C115 C116 10
@ @ 10
0.1U_0402_10V6-K 0.1U_0402_10V6-K 11
2 2 12 GND1
GND2
ACES_50463-0104A-P01

RTC CONN.
R112
D6 JRTC ME@
1 2 1 2 1
+RTCBATT 1
2
RB751V-40_SOD323-2 1K_0603_5% 2
SCS00006S00 3
4 GND1
GND2
TE_2041180-2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/09/07 Deciphered Date 2014/09/07 XXXX

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 51 of 81
5 4 3 2 1
TYPE-B NGFF SLOT FOR WWAN/SSD
3.2H CONNECTOR
+3V_WWAN +3V_WWAN
For RF solution.
SSD Active:4.5W 1.5A PU +3VS JWWAN1 ME@
J3 @ WWAN_DET# 1 2
<12> WWAN_DET# CONFIG_3 3.3VAUX1
1 2 +3V_WWAN C57 C58 C59 C60 CRF19 CRF20 3 4 R122 1 3G@ 2 10K_0402_5%
+3VALW 1 2 GND1 3.3VAUX2 +3V_WWAN
RF_NS@ RF_NS@ 5 6
GND2 FULL_CARD_POWER_OFF#

10U_0805_10V6-K

10U_0805_10V6-K

.01U_0402_16V7-K

0.1U_0402_10V7-K

2200P_0402_50V7-K

47P_0402_50V8-J
JUMP_43X118 USB20_P4_WWAN 7 8 WWAN_DISABLE#
<13> USB20_P4_WWAN USB20_N4_WWAN 9 USB_D+ W_DISABLE# 10 WWAN_DISABLE# <12>
1 1 1 1 1 1 <13> USB20_N4_WWAN USBD- LED#
J4 @ 11
GND3 NC 12
1 2 @ @ @ @ 14
+3VS 1 2 13 NC NC
15 NC NC 16
JUMP_43X118 2 2 2 2 2 2 18
17 NC NC
20
PU +3VALW MSATA_DETECT#
19
21
NC GPIO_5 22
<62> MSATA_DETECT# CONFIG_0 GPIO_6
23 24
R32 1 3G@ 2 10K_0402_5% 25 WAKE_ON_WWAN# GPIO_7 26 GPS_DISABLE# 1
27 DPR W_DISABLE2# 28 T7
29 GND4 UIM-RFU 30 UIM_RST
31 USB3.0-TX-(Device) UIM-RESET 32 UIM_CLK
33 USB3.0-TX+(Device) UIM-CLK 34 UIM_DATA R35 1 3G@ 2 20K_0402_5% +UIM_PWR
35 GND5 UIM-DATA 36 +UIM_PWR
40mil C38 C39 +UIM_PWR
37 USB3.0-RX-(Device) UIM-PWR 38
USB3.0-RX+(Device) DEVSLP DEVSLP1 <12>

0.1U_0402_25V6-K

4.7U_0603_6.3V6-K
39 40
C61 3G@ 1 2 .01U_0402_16V7-K SATA_PRX_DTX_P2_CONN 41 GND6 GPIO_0 42
<7> SATA_PRX_DTX_P2 SATA-B+/HRX+ GPIO_1 1 1
C62 3G@ 1 2 .01U_0402_16V7-K SATA_PRX_DTX_N2_CONN 43 44
<7> SATA_PRX_DTX_N2 45 SATA-B-/HRX- GPIO_2 46 3G@ 3G@
C63 3G@ 1 2 .01U_0402_16V7-K SATA_PTX_DRX_N2_CONN 47 GND7 GPIO_3 48
<7> SATA_PTX_DRX_N2 SATA-A-/HTX- GPIO_4 2 2
C64 3G@ 1 2 .01U_0402_16V7-K SATA_PTX_DRX_P2_CONN 49 50
<7> SATA_PTX_DRX_P2 51 SATA-A+/HTX+ RESERVED3 52
53 GND8 RESERVED4 54
55 RESERVED1 RESERVED5 56
57 RESERVED2 RESERVED6 58
59 GND9 RESERVED7 60
61 ANTCTRL0 COEX3 62
63 ANTCTRL1 COEX2 64
65
67
ANTCTRL2
ANTCTRL3
COEX1
SIM_DETECT
66
68
1
T19 SIM CONN.
R33 1 3G@ 2 10K_0402_5% 69 RESET# SUSCLK 70 JSIM ME@
71 CONFIG_1 3.3VAUX3 72
73 GND10 3.3VAUX4 74 1
R34 1 3G@ 2 10K_0402_5% 75 GND11 3.3VAUX5 +UIM_PWR 2 CD
CONFIG_2 +UIM_PWR C1
3
76 77 UIM_RST 4 C5
PEG1 PEG2 5 C2
78 79 UIM_CLK 6 C6
NPTH1 NPTH2 UIM_DATA 7 C3
FOX_AS0BC21-S30BB-7H C7
8 10
9 GND1 NPTH1 11
GND2 NPTH2

PLAST_CE1S-148-H-N_7P-T

+3V_WLAN

TYPE-A NGFF SLOT FOR WLAN +3VALW R236 1 @ 2 0_0805_5% +3V_WLAN

3.2H CONNECTOR R237 1 @ 2 0_0805_5%

+3V_WLAN
+3VS
JWLBT ME@
1 2
USB20_P6 3 GND1 3.3VAUX1 4
<13> USB20_P6 USB20_N6 5 USB_D+ 3.3VAUX2 6
1. softstart (RC) will check on EVT PCB <13> USB20_N6 7 USB_D- LED#1
2. if AOAC enable +3V_WLAN always ON GND2 NC 8
9 NC NC 10
if AOAC disable +3V_WLAN is same as +3VS 11 NC NC 12
13 NC NC 14
16
15 NC LED#2
17 18
+3VALW +3V_WLAN 19 MLDIR_SENSE GND16 20 1 R151 2 0_0402_5% BT_ON_R
21 DP_ML3N DP_AUXN 22 @
Q9 23 DP_ML3P DP_AUXP 24
AO3413_SOT23-3 25 GND3 GND13 26 1
J2 @ R152 2 0_0402_5% EC_TX_R
27 DP_ML2N DP_ML1N
S

3 1 +3VWLAN 1 2 28 @
1 2 29 DP_ML2P DP_ML1P 30
1 1 JUMP_43X79 31 GND4 GND14 32
33 DP_HPD DP_ML0N 34
G
2

C93 C94 PCIE3_CTX_C_DRX_P 35 GND5 DP_ML0P 36

<13> PCIE3_CTX_C_DRX_P PCIE3_CTX_C_DRX_N 37 PETP0 GND15 38 CL_RST_WLAN#
0.1U_0402_10V7-K .01U_0402_16V7-K 1
2@ 2@ <13> PCIE3_CTX_C_DRX_N 39 PETN0 RESERVED1 40 CL_RST_WLAN# <9>
C96 CL_DATA_WLAN
PCIE3_CRX_DTX_P 41 GND6 RESERVED2 42 CL_CLK_WLAN CL_DATA_WLAN <9>
@
<13> PCIE3_CRX_DTX_P PCIE3_CRX_DTX_N 43 PERP0 RESERVED3 44 CL_CLK_WLAN <9>
4.7U_0603_10V6-K
2 <13> PCIE3_CRX_DTX_N 45 PERN0 COEX3 46
R92
1 2 CLK_PCIE_WLAN 47 GND7 COEX2 48
<62> AOAC_ON# <8> CLK_PCIE_WLAN 49 REFCLKP0 COEX1 50
CLK_PCIE_WLAN# SUSCLK_32K
<8> CLK_PCIE_WLAN# 51 REFCLKN0 SUSCLK 52 PLTRST#_FAR SUSCLK_32K <10>
10K_0402_5%
CLKREQ_PCIE2_WLAN# 53 GND8 PERST0# 54 BT_ON_R PLTRST#_FAR <10,56,62>
1 <8> CLKREQ_PCIE2_WLAN#
C65 EC_WLAN_WAKE# 55 CLKREQ0# RESERVED/W_DISABLE#2 56 RF_OFF#
To EC <62> EC_WLAN_WAKE# 57 PEWAKE0# W_DISABLE#1 58 RF_OFF# <12>
.01U_0402_16V7-K 59 GND9 I2C_DATA 60
2 61 PETP1 I2C_CLK 62 R90 1 2 100_0402_1% EC_RX
EC_RX <62>
63 PETN1 I2C_ALERT# 64 EC_TX_R R89 1 2 100_0402_1% EC_TX
65 GND10 RESERVED4 66 EC_TX <62>
67 PERP1 PERST1# 68
For RF solution. 69 PERN1 CLKREQ1# 70
71 GND11 PEWAKE1#

1
72
73 REFCLKP1 3.3VAUX4 74
+3V_WLAN 75 REFCLKN1 3.3VAUX5 R91
GND12 100K_0402_5%
CRF21 CRF22 77 76

2
RF_NS@ RF_NS@ 79 PEG1 PEG2 78 BT_ON_R R239 1 2 1K_0402_5%
NPTH1 NPTH2 BT_ON <11>
2200P_0402_50V7-K

47P_0402_50V8-J

1 1 TYCO_2199230-8

2 2

Security Classification LC Future Center Secret Data Title

Issued Date 2013/09/07 Deciphered Date 2014/09/07 WWAN/WLAN NGFF CONN.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 52 of 81
 5 4 3 2 1

D D

BLANK

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/09/07 Deciphered Date 2014/09/07 XXXX

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 53 of 81
5 4 3 2 1
 5 4 3 2 1

D D

For Edge 15'' Audio board CONNECTOR

+3VALW

1
R238

1K_0402_5%
FFC

2
JAUF ME@
12 14
LOGO_LED# 11 12 GND2 13
<38,62> LOGO_LED# 10 11 GND1
C JSENSE_CON 9 10 C
<36> JSENSE_CON HP_OUTR_CON 8 9
<36> HP_OUTR_CON HP_OUTL_CON 7 8
<36> HP_OUTL_CON 6 7
HGNDA
<35,36> HGNDA 5 6
4 5
HGNDB 3 4
<35,36> HGNDB 2 3
1 2
1
ACES_50506-01201-001

GNDA

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/09/07 Deciphered Date 2014/09/07 SUB-AUDIO JACK CONN.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 54 of 81
5 4 3 2 1
Thermal Sensor
Thermal Sensor
placed near by VRAM
U1
+3VS

1 10 EC_SMB_CK3
VDD SMCLK EC_SMB_CK3 <21,34,62,9>
REMOTE1+ 2 9 EC_SMB_DA3
DP1 SMDATA EC_SMB_DA3 <21,34,62,9>
1
C1 REMOTE1- 3 8
DN1 ALERT#
0.1U_0402_10V6-K REMOTE2+ 4 7 R3 1 @ 2 10K_0402_5%
2 DP2 THERM# +3VS
REMOTE2- 5 6
DN2 GND

F75303M_MSOP10

Address 1001_101xb
Internal pull up 1.2K to 1.5V
R for initial thermal shutdown temp

Close to U1 Close to +VCC_CORE Close JDIMM1&JDIMM2

REMOTE1+ REMOTE2+ REMOTE2+/-:
REMOTE1+ REMOTE2+ Trace width/space:10/10 mil
1 1 1 1
Trace length:<8"

1
C C
C2 C3 C4 @ 2 Q1 C5 @ 2 Q2
2200P_0402_50V7-K 2200P_0402_50V7-K 100P_0402_50V8-J B S TR TTC4116FU NPN SC-70-3 100P_0402_50V8-J B S TR TTC4116FU NPN SC-70-3
2 2 2 E SB000010U00 2 E SB000010U00

3
REMOTE1- REMOTE2-
REMOTE1- REMOTE2-

Security Classification LC Future Center Secret Data Title

Issued Date 2013/09/07 Deciphered Date 2014/09/07 XXXX

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 55 of 81
 A B C D E

APS G-Sensor +3VALW +3VALW_GS

W=40 mils RG1 1 @ 2 0_0402_5%

1 1

D
3 1 +3VALW_GS

1 QG1 1 1
CG1 AO3413_SOT23-3 CG3

G
2
@ @ CG2 10U_0603_6.3V6-M
0.1U_0402_10V6-K .01U_0402_16V7-K @
2 2 2

RG4
1 2
<62> EC_GS_ON#
100K_0402_5% 1
CG4
.01U_0402_16V7-K
2

RG5 1 2 100K_0402_5% UGSEN1

GS_SELFTEST 2 12 VOUTX RG6 1 2 56K_0402_5% GS_VOUTX

<62> GS_SELFTEST ST VoutX 10 VOUTY 1 2 56K_0402_5% GS_VOUTY GS_VOUTX <62>
RG7
+3VALW_GS VoutY 8 GS_VOUTY <62>
2 VoutZ 2
1 1 1 1
14
15 VDD_1 CG5 CG6 CG7 CG8
VDD_2 0.1U_0402_10V7-K 0.1U_0402_10V7-K 0.1U_0402_10V7-K 0.1U_0402_10V7-K
1 1 2 2 2 2
1
CG9 CG10 NC1 4
10U_0603_6.3V6-M 0.1U_0402_10V7-K 3 NC2 9
2 2 5 GND1 NC3 11
6 GND2 NC4 13
7 GND3 NC5 16
GND4 NC6

APS_GND LIS34ALTR_LGA16_4X4
Please close G-senser SA000037F0J

JAPS1 @
1 2
1 2
JUMP_43X39
APS_GND

3 3

TPM IC
+3VS

1 1
1

C50
TPM@ C51 @
TPM@ R69 0.1U_0402_10V6-K 10U_0603_6.3V6-M
UTPM1 10K_0402_5% 2 2
1 24
2

2 NC_1 VPS_1 10
3 NC_2 VPS_2
7 NC_3 28 LPC_PD#
PP LPCPD# 27 SERIRQ LPC_PD# <10>
6 SERIRQ 26 LPC_AD0 SERIRQ <12,62>
9 NC_4 LAD0 23 LPC_AD1 LPC_AD0 <62,9>
VNC_1 LAD1 22 LPC_AD1 <62,9>
LPC_FRAME#
4 LFRAME# 20 LPC_FRAME# <62,9>
LPC_AD2
11 GND_1 LAD2 17 LPC_AD3 LPC_AD2 <62,9> For EMI
18 GND_2 LAD3 LPC_AD3 <62,9>
EMC_NS@
GND_3 25 R219 EMC_NS@
5 NC_11 21 CLK_PCI_TPM CLK_PCI_TPM 1 2 C169 1 2 10P_0402_50V8-J
8 NC_5 LCLK 19 CLK_PCI_TPM <8>
12 VNC_2 NC_10 15 CLKRUN# 10_0402_5%
13 NC_6 NC_9 CLKRUN# <10>
14 NC_7 16 PLTRST#_FAR
NC_8 LRESET# PLTRST#_FAR <10,52,62>
ST33ZP24AR28PVSP_TSSOP28
4 4
SA00005C010
TPM@

Security Classification LC Future Center Secret Data Title

Issued Date 2013/09/07 Deciphered Date 2014/09/07 XXXX

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 56 of 81
A B C D E
 5 4 3 2 1

D D

BLANK

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/09/07 Deciphered Date 2014/09/07 XXXX

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 57 of 81
5 4 3 2 1
 5 4 3 2 1

D D

BLANK

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/09/07 Deciphered Date 2014/09/07 XXXX

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 58 of 81

5 4 3 2 1
BLANK

Security Classification LC Future Center Secret Data Title

Issued Date 2013/09/07 Deciphered Date 2014/09/07 XXXX

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 59 of 81
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/09/07 Deciphered Date 2014/09/07 XXXX

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 60 of 81
5 4 3 2 1
 +5VALW VIN 5V and 3.3V (VBIAS=5V), IMAX(per channel)=6A, Rds=18mohm +5VS
U11 J5 @
1 14 +5VS_LS 1 2
2 VIN1_1 VOUT1_2 13 1 2
VIN1_2 VOUT1_1 JUMP_43X118
1 1
SUSP# 3 12 C71 1 2 1000P_0402_25V7-K
Load Switch @ C69
1U_0402_6.3VA-K
<43,62,69,70,71,76> SUSP#
4
ON1 CT1
11
@ C70
0.1U_0402_10V7-K
+5VALW To +5VS 2 +5VALW
SUSP# 5
VBIAS GND
10 C72 1 2 100P_0402_50V8-J
2

+3VALW To +3VS +3VALW

6
ON2 CT2
9 J6 @
+3VS

7 VIN2_1 VOUT2_2 8 +3VS_LS 1 2

VIN2_2 VOUT2_1 1 2
1 15 JUMP_43X118 1
GPAD
@ C73 TPS22966DPUR_WSON14_2X3 @ C74
1U_0402_6.3VA-K 0.1U_0402_10V7-K
2 2

+5VS, C159 --> 1.5ms

+3VS, C160 --> 2.5ms

+3VALW +3V_PCH
+3VALW To +3V_PCH R11 0_0805_5% +5VALW To +5V_DDR
1 2

80 mils 80 mils
J7 @ +5VALW +5V_DDR
0.271 A

D
3 1 1 2 @
1 2 R23
Q6 JUMP_43X39 1 2
AO3413_SOT23-3

G
2
@
0_0402_5%
1
C68 +5VALW +5V_DDR

2
@ U7
R7 4.7U_0603_10V6-K 5 1 +5V_DDR
10K_0402_5% 2 IN2 OUT
@ 1 2 1
GND C42

1
PCH_PWR_EN# C43 4 3 4.7U_0603_10V6-K
<62> PCH_PWR_EN# IN1 EN SYSON <62,69>
1U_0402_6.3VA-K
2 G5243AT11U_SOT23-5 2
1 SA00005XJ00
1 C66
If support Deep and Mirror, .01U_0402_16V7-K
R96 @
R96 need to set MIRROR@ @ 2
100K_0402_5%
2

+3VALW to +3VM +3VALW +3VM

+5VALW R10 1 2 0_0402_5%

J8 @
1

3 1 1 2
R226 Q10 1 2
+3VL @ @ JUMP_43X39
47K_0402_5% AO3413_SOT23-3
G
2
2

For SPI ROM/LAN VPRO

2

R227
@
1

10K_0402_5%
If support SBA and Mirror, R228
1

R228 need to set MIRROR@ @

10K_0402_5% VM_PWRON#
2

D
1

Q11 1
VM_PWRON 2 @ C170
<62,78> VM_PWRON
G 2N7002WT1G_1N_SC-70-3 @
S SB00000YY00 .01U_0402_16V7-K
3

Security Classification LC Future Center Secret Data Title

Issued Date 2013/09/07 Deciphered Date 2014/09/07 XXXX

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 61 of 81
 5 4 3 2 1

+3VL

1 RE1 2 PECI
Vcc 3.3V +/- 5%
<5> H_PECI
43_0402_5% RE3 100K +/- 1%

2
1 RE3 Board ID RE7 VAD_BID min V AD_BID typ VAD_BID max Phase
@
CE1 +3VL 100K_0402_1%
47P_0402_50V8-J All capacitors close to EC 0 0K +/- 5% 0 V 0 V 0 V Pre-SDV

1
2
+3VL CE4 CE5 CE8 CE6 CE9 CE10 Board_ID
1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V SDV
Intel recommend 2 18K +/- 5% 0.436 V 0.503 V 0.538 V FVT

2
0.1U_0402_25V6-K

0.1U_0402_25V6-K

0.1U_0402_25V6-K

0.1U_0402_25V6-K

0.1U_0402_25V6-K

0.1U_0402_25V6-K
RE7
1 1 1 1
@
1
@
1
4.7K_0402_1%
3 33K +/- 5% 0.712 V 0.819 V 0.875 V SIT
Close to EC +3VS +3VL_AVCC
4 4.7K +/- 5% 0.141 V 0.148 V 0.155 V SVT
D D
CE7

1
1 2 +VCOREVCC 2 2 2 2 2 2
5 24K +/- 5% 0.612 V 0.638 V 0.664 V
0.1U_0402_25V6-K
+3VL

114
121
127
12

11

26
50
92

74
RE4 minimum trace width 12 mil

3
1 2 WRST# UE1
1

VSTBY1
VSTBY2
VSTBY3
VSTBY4
VSTBY5
VCC

AVCC
VBAT

VSTBY(PLL)
VCORE
100K_0402_5%
CE11
1.05VS_PGOOD_R 1 2 1.05VS_PGOOD 1.05VS_PGOOD <10,14,70>
1U_0402_10V6-K RE40 0_0402_5%
2

KBRST# 4 24 LOGO_LED# +3VL +3VL_AVCC

<12> KBRST# KBRST#/GPB6 PWM0/GPA0 LOGO_LED# <38,54>
SERIRQ 5 25 AOU_IFG#
<12,56> SERIRQ SERIRQ/GPM6 PWM1/GPA1 AOU_IFG# <41>
LPC_FRAME# 6 28 VM_PWRON LE1
+3VALW <56,9> LPC_FRAME# LFRAME#/GPM5 PWM2/GPA2 VM_PWRON <61,78>
LPC_AD3 7 29 1.05VS_PGOOD_R 1 2 +3VL_AVCC
<56,9> LPC_AD3 8 LAD3/GPM3 PWM3/GPA3 30
LPC_AD2 PWM GS_SELFTEST
<56,9> LPC_AD2 LAD2/GPM2 PWM4/GPA4 GS_SELFTEST <56>
LPC_AD1 9 31 EC_FAN_PWM BLM18PG121SN1D_2P
<56,9> LPC_AD1 LAD1/GPM1 PWM5/GPA5 EC_FAN_PWM <50>
RE15 1 2 100K_0402_5% HDD_DETECT# LPC_AD0 10 32 BEEP# 1 1
<56,9> LPC_AD0 13 LAD0/GPM0 PWM6/SSCK/GPA6 34 BEEP# <36>
CLK_PCI_EC LPC VCCST_PG_EC
+3VALW <8> CLK_PCI_EC LPCCLK/GPM4 PWM7/RIG1#/GPA7 VCCST_PG_EC <14>
WRST# 14 120 CE2 CE3
HDD_DETECT# 15 WRST# TMRI0/GPC4 124 SUSP# 0.1U_0402_25V6-K 1000P_0402_50V7-K
<37> HDD_DETECT# ECSMI#/GPD4 TMRI1/GPC6 SUSP# <43,61,69,70,71,76> 2 2
RPE1 EC_RX 16
<52> EC_RX PWUREQ#/BBO/SMCLK2ALT/GPC7
1 8 MSATA_DETECT# EC_TX 17 66 GPU_VR_HOT# GPU_VR_HOT# <21,76> LE2
2 7 <52> EC_TX 22 LPCPD#/GPE6 ADC0/GPI0 67 1 2
AOU_IFG# PLTRST#_FAR GS_VOUTY GS_VOUTY <56> EC_AGND
<10,52,56> PLTRST#_FAR LPCRST#/GPD2 ADC1/GPI1
3 6 KB_FN EC_SCI# 23 68 BATT_TEMP BATT_TEMP <66,67>
4 5 <7> EC_SCI# 126 ECSCI#/GPD3 ADC2/GPI2 69
EC_WLAN_WAKE# VGA_AC_DC# ADC Board_ID BLM18PG121SN1D_2P
<21> VGA_AC_DC# GA20/GPB5 ADC3/GPI3 70 FAN_ID
10K_0804_8P4R_5% IT8586E/AX ADC4/GPI4
ADC5/DCD1#/GPI5
71
72
ADP_I
GS_VOUTX
FAN_ID <50>
ADP_I <67>
GS_VOUTX <56>
1
RPE2
8 KSO1
<51> KSI[0..7]
KSI[0..7] KSI0 58
KSI0/STB#
LQFP-128L ADC6/DSR1#/GPI6
ADC7/CTS1#/GPI7
73 ADP_ID ADP_ID <65> +5VALW

2 7 KSO2 KSI1 59 78 SUSWARN# SUSWARN# <10>

3 6 FAN_ID KSO[0..17] KSI2 60 KSI1/AFD# DAC2/TACH0B/GPJ2 79 MAINPWON_EC USB_ON# RE2 1 2 10K_0402_5%
<51> KSO[0..17] KSI2/INIT# DAC3/TACH1B/GPJ3 MAINPWON_EC <65,66,68>
4 5 LAN_WAKE# KSI3 61 DAC 80 H_PROCHOT_EC
KSI4 62 KSI3/SLIN# DAC4/DCD0#/GPJ4 81 ENBKL
C ENBKL <11> C
10K_0804_8P4R_5% KSI5 63 KSI4 DAC5/RIG0#/GPJ5
+3VS KSI6 64 KSI5 85 AOU_EN +5VS
KSI6 PS2CLK0/TMB0/CEC/GPF0 AOU_EN <41>
RPE3 KSI7 65 86 PBTN_OUT#
1 8 36 KSI7 PS2DAT0/TMB1/GPF1 87 PBTN_OUT# <10> 1 2
LPC_FRAME# KSO0 PCH_SLP_SUS# PCH_SLP_SUS# <10> CP_CLK RE5 4.7K_0402_5%
+3VL 2 7 EC_FAN_SPEED KSO1 37 KSO0/PD0 GPF2 88 SUSACK# CP_DATA RE6 1 2 4.7K_0402_5%
KSO1/PD1 Int. K/B PS2 GPF3 SUSACK# <10>
3 6 KSO2 38 89 CP_CLK
4 5 LID_SW# KSO3 39 KSO2/PD2 Matrix PS2CLK2/GPF4 90 CP_DATA
CP_CLK <49>
KSO3/PD3 PS2DAT2/GPF5 CP_DATA <49>
KSO4 40 +3VS
10K_0804_8P4R_5% KSO5 41 KSO4/PD4 96 EC_DPWROK
KSO5/PD5 EXTERNAL SERIAL FLASH GPH3/ID3 EC_DPWROK <10>
KSO6 42 97 PCH_PWR_EN# EC_FAN_PWM RE8 1 @ 2 10K_0402_5%
43 KSO6/PD6 GPH4/ID4 98 PCH_PWR_EN# <61>
KSO7 ACOFF
KSO7/PD7 GPH5/ID5 ACOFF <67>
RPE4 KSO8 44 99 PCH_PWROK GPU_VR_HOT# RE9 1 2 10K_0402_5%
KSO8/ACK# GPH6/ID6 PCH_PWROK <10>
1 8 SUSP# KSO9 45
2 7 KSO10 46 KSO9/BUSY 101 FSCE#
KSO10/PE NC1 FSCE# <9>
3 6 KSO11 51
KSO11/ERR# NC2
102 SPI_FMOSI#
SPI_FMOSI# <9> Un-stuff if not necessary.
4 5 SYSON KSO12 52 SPI Flash ROM 103 SPI_FMISO
KSO12/SLCT NC3 SPI_FMISO <9>
KSO13 53 105 SPI_FSCK
KSO13 NC4 SPI_FSCK <9>
100K_0804_8P4R_5% KSO14 54
KSO15 55 KSO14
@ KSO16 56 KSO15 108 ACIN
CE14 2 1 0.1U_0402_25V6-K KSO17 57 KSO16/SMOSI/GPC3 AC_IN# 109 LID_SW#
KSO17/SMISO/GPC5 UART LID_SW# LID_SW# <34,51>
For EMC
ON/OFF# 110 82 PCH_SYSPWROK
<34,50> ON/OFF# PWRSW# EGAD/GPE1 PCH_SYSPWROK <10>
111 SM Bus 83 EC_ON EC_ON <68>
EC_SMB_CK1 115 XLP_OUT EGCS#/GPE2 84 AOU_CTL1
+3VL <66,67> EC_SMB_CK1 SMCLK1/GPC1 EGCLK/GPE3 AOU_CTL1 <41>
EC_SMB_DA1 116
<66,67> EC_SMB_DA1 SMDAT1/GPC2
RPE5 PECI 117 GPIO 77 PM_SLP_S5#
SMCLK2/PECI/GPF6 GPJ1 PM_SLP_S5# <10>
1 8 EC_SMB_CK1 ADAPTER_ID_ON# 118 100 EC_MUTE#
+3VS <65> ADAPTER_ID_ON# SMDAT2/PECIRQT#/GPF7 SSCE0#/GPG2 EC_MUTE# <35>
2 7 EC_SMB_DA1 EC_SMB_CK3 94 106 EC_GS_ON#
3 6 <21,34,55,9> EC_SMB_CK3 95 CRX1/SIN1/SMCLK3/GPH1/ID1 SSCE1#/GPG0 104 EC_GS_ON# <56>
EC_SMB_DA3 ME_FLASH
<21,34,55,9> EC_SMB_DA3 CTX1/SOUT1/GPH2/SMDAT3/ID2 DSR0#/GPG6 ME_FLASH <7>
4 5 EC_SMB_CK3 107 SYSON
DTR1#/SBUSY/GPG1/ID7 SYSON <61,69>
119 BKOFF#
+3VS CRX0/GPC0 123 BKOFF# <38>
2.2K_0804_8P4R_5% AOAC_ON#
CTX0/TMA0/GPB2 AOAC_ON# <52>
+3VL 112 18 PM_SLP_S3# PM_SLP_S3# <10>
RE27 1 2 2.2K_0402_5% EC_SMB_DA3 LAN_WAKE# 125 VSTBY0 RI1#/GPD0 21 PM_SLP_S4#
<47> LAN_WAKE# GPE4 RI2#/GPD1 PM_SLP_S4# <10>
WAKE UP 76 PM_SLP_A# PM_SLP_A# <10>
B TACH2/GPJ0 48 AOU_CTL3 B
TACH1A/TMA1/GPD7 47 AOU_CTL3 <41> +3VL
EC_FAN_SPEED EC_FAN_SPEED <50>
USB_ON# 33 TACH0A/GPD6 19 EC_WLAN_WAKE# MIRROR@
<34,40> USB_ON# GINT/CTS0#/GPD5 L80HLAT/BAO/GPE0 EC_WLAN_WAKE# <52>
MSATA_DETECT# 35 GPIO 20 KB_FN
<52> MSATA_DETECT# RTS1#/GPE5 L80LLAT/GPE7 KB_FN <51>
EC_RSMRST# 93 EC_ON RE39 1 2 10K_0402_5%
<10> EC_RSMRST# CLKRUN#/GPH0/ID0

EC_WAKE# 2
Please don't place any PU Resistor on GPG[7:2] +3VL
<12> EC_WAKE#
AC_PRESENT 128 CK32KE/GPJ7
Clock (Reserve hardware strapping)
<10> AC_PRESENT CK32K/GPJ6 MIRROR@
EC_MUTE# RE31 1 2 10K_0402_5%

RE32 1 @ 2 10K_0402_5%
AVSS
VSS1

VSS2
VSS3
VSS4
VSS5
VSS6

1. Version CX : Don't Support Mirror Code

IT8586E-AX_LQFP128_14X14 IT8586E/FX LQFP Version DX/EX/FX : Support Mirror Code
1

27
49
91
113
122

75

SA00005W940
2. For Mirror Code
EC_AGND
"H" --> Enable
"L" --> Disable (Default)
*

AC IN, need to confirm the pin is High or Low active while pulg ACIN
+3VL
For factory EC flash
ACIN RE33 1 2 10K_0402_5%
1 EC_SMB_CK1 RE34 1 2 0_0402_5%
ACPRN <67>
IT1 @1 EC_SMB_DA1
PROCHOT# IT2 @1 DEV1 @ 2 1 RB751V-40_SOD323-2
For ESD (EC asserts PROCHOT# signal by driving high, IT3
IT4
@1
@1
A A
EMC_NS@ the level shifter must invert it and drive the processor side PROCHOT# low.) IT5 @ CE12 1 2 100P_0402_50V8-J
CE13 1 2 220P_0402_50V7-K PLTRST#_FAR

1 KSI7
For EMI IT6 @1 KSI6
EMC_NS@ RE38 EMC_NS@ VR_HOT# IT7 @1 WRST#
CE15 1 2 10P_0402_50V8-J 1 2 CLK_PCI_EC <5,67,73> VR_HOT# IT8 @
1

D
1
10_0402_5% H_PROCHOT_EC 2 CE17
CE16 2 1 100P_0402_50V8-J BATT_TEMP G Title

璶璶ECADC pin
QE1 S 47P_0402_50V8-J
Security Classification LC Future Center Secret Data
3

2N7002WT1G_1N_SC-70-3 2
BATT_TEMP Issued Date 2013/09/07 Deciphered Date 2014/09/07 XXXX
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 62 of 81
5 4 3 2 1
 5 4 3 2 1

Screw Hole D

H20 H8 H17 H25 H16 H15 H23 H24 H14 H9

@ @ @ @ @ @ @ @ @ @

1
PAD_C6P0D2P3 PAD_C6P0D2P3 PAD_C6P0D2P3 PAD_C6P0D2P3 PAD_C6P0D2P3 PAD_C6P0D2P3 PAD_C6P0D2P3 PAD_C6P0D2P3 PAD_C6P0D2P3 PAD_C6P0D2P3

H18 H13 H11 H12 H10

@ @ @ @ @

1
PAD_C6P0D2P3 PAD_C6P0D2P3 PAD_C6P0D2P3 PAD_C6P0D2P3 PAD_C6P0D2P3

H28

1 @
C C

PAD_C3P5D2P3

H19 H22 H27

@ @ @
1

1
PAD_shapeT6P0X8P5CB6P0D2P3 PAD_SHAPET6P0X8P5CB6P0D2P3 PAD_shapeT6P0X8P5CB6P0D2P3
H5 H6 H7 H1 H2 H3 H4

@ @ @ @ @ @ @
1

1
PAD_C6P0D3P15 PAD_C6P0D3P15 PAD_C6P0D3P15 PAD_C6P0D3P15 PAD_C6P0D3P15 PAD_C6P0D3P15 PAD_C6P0D3P15

H26 H21

Center Zero
B @ @ B
1

PAD_O2P3X2P8D2P3X2P8N PAD_C2P3D2P3N

PCB Fedical Mark PAD

FD1 FD2 FD3 FD4 FD5 FD6
1

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/09/07 Deciphered Date 2014/09/07 XXXX

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 63 of 81
5 4 3 2 1
 5 4 3 2 1

D D

BLANK

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/09/07 Deciphered Date 2014/09/07 XXXX

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 64 of 81
5 4 3 2 1
 5 4 3 2 1

PD1
RB751V-40
PD2
1SS355 PR1 PR3 1 2
100K_0402_1% 10K_0402_1%
VSYSTEM
<62,66,68> MAINPWON_EC 2 1 1 2 1 2
1 2
B+ PRT2A
PD3

2
D RB751V-40 D

3
E
PQ1
+3VALW 2
B PR5
MMBT3906_SOT23-3 750K_0402_1% 0_0402_5%

1
C
UMA@

1
2
VSYSTEM Charger VGA 5VALW
PR6 0109@LNV

1
750_0402_1% C
PQ4 2 2 1 2 1 2 1

1
MMBT3904_SOT23-3 B

1
PD5 @ E 2 PRT1 PRT2 PRT3

3
RB751V-40 PR271 540_0402NEW_30% 540_0402NEW_30% 540_0402NEW_30%
1M_0402_5% PC3 DIS@
1U_0603_25V7K

2
1

2N7002KDWH 2N SOT363-6

2
2

6
D 2 1 2 1 2 1

PQ43A
@ PR270 2 ADAPTER_ID_ON
G PRT6 PRT5 PRT4

2N7002KDWH 2N SOT363-6
0_0402_5%
S 540_0402NEW_30% 540_0402NEW_30% 540_0402NEW_30%

1
1

3
D
PR4 CPU 1.35VS 3VALW

PQ43B
10K_0402_1% PR272 5 ADAPTER_ID_ON# <62>
1 2 1M_0402_5% G
ADP_ID <62>
S

4
2
1
680P_0402_50V7-K

0.1U_0402_6.3V A/D

1
1
1
PC2

PC1

C PD19 C
AZ5425-01F_DFN1006P2E2 Thermal protection
2

2
PRT1 place to closed PQ25 with PU7

2
PRT2 place to closed PQ39 with PU14
PL1 PRT3 place to closed PQ29 with PU8
EMC@ MURATA BLM18KG300TN1D
PRT4 place to closed PQ28 with PU8
1 2
PRT5 place to closed PQ31 with PU9
JDCIN
APDIN PF1
PL11
MURATA BLM18KG300TN1D
VSYSTEM
1 7A_32V_0437007.WR EMC@ PRT6 place to closed PQ34 with PU13
1 2 APDIN2 1 1 2
2 3
3 4
4 0210@GCM request
5
8 5 6
9 GND1 6 7
GND2 7 EMC@ EMC@ EMC@ EMC@
1

1
ACES_50271-00701-001 PC4 PC5 PC6 PC7
1000P_0402_50V7-K

100P_0402_50V8-J

100P_0402_50V8J

1000P_0402_50V7-K
ME@
2

B B

+CHGRTC RTCVREF
@ PD8
RB751V-40 @ PR20 @ PR21
+RTCBATT 560_0603_5% 560_0603_5%
1 2 1 2 1 2
<10,50>
3.3V
1

@ PC13
10U_0603_6.3V
2

1 2 +3VLP
PD9
RB751V-40

RTC Battery

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/05 Deciphered Date 2014/12/31 DCIN / Vin Detector

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 65 of 81
5 4 3 2 1
 5 4 3 2 1

PRT8 under CPU botten side :

CPU thermal protection at 93 +-3 degree C
Recovery at 56 +-3 degree C

D VL D
+3VLP +3VALW
0226@thermal request

47K_0402_1%
12.7K_0402_1%
PC15

@ PR26

@ PR35
0.1U_0603_16V7K

2
PR25
16.5K_0402_1%

2
PU2

2
0226@thermal request 1 8 NTC_V_1
VCC TMSNS1
PR39 2 7 OTP_N_002 2 1
@ 0_0402_5% GND RHYST1
<62,65,68> MAINPWON_EC 1 2 OTP_N_003 3 6 PR30
OT1 TMSNS2

1
20K_0402_1%
4 5 PRT8
OT2 RHYST2
0226@thermal request 100K_0402_1%_NCP15WF104F03RC
G718TM1U_SOT23-8

2
C C

0210@GCM request

PL2 EMC@
MURATA BLM18KG300TN1D

1 2
VMB2 VMB
PF2 PL21 EMC@
JBATT2 12A_32V_0501012.WRS MURATA BLM18KG300TN1D
1 2 1
1 2 1 2 BATT+
2 3 EC_SMCA
3 4 EC_SMDA
4 5
5 EMC@ EMC@
1

2
6
6 7 PC16 PC14
7 8 2 1000P_0402_50V 0.01U_0402_25V

1
G1
2

9
G2
PESD5V0U2BT_SOT23-3

10
G3
1

11
G4 PR28
@ PD10

PR27
ME@ 100_0402_1%
1

100_0402_1%
2

SUYIN_200082GR007M211ZR

B B

EC_SMB_CK1 <62,67>

EC_SMB_DA1 <62,67>

PR40
100K_0402_1%
2 1
+3VALW

1 2 A/D
BATT_TEMP <62,67>
PR41
2

10K_0402_1%

@ PD11
PESD5V0U2BT_SOT23-3
1

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/05 Deciphered Date 2014/12/31 BATTERY CONN/OTP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 66 of 81
5 4 3 2 1
 5 4 3 2 1

D D
PQ20 PQ21
VSYSTEM SIS406DN-T1-GE3_PAK1212-8-5 P2 SIS406DN-T1-GE3_PAK1212-8-5 P3 PL3 EMC@ PR83
3 3 1UH_PCMB053T-1R0MS_20% 0.01_1206_1%
2 2
5 1 1 5 1 2 1 4
B+
2 3
EMC@ EMC@

10U_0805_25V6-K

10U_0805_25V6-K
1

2
PC33
1

1
PC31

PC32
PC30 PR84 0.022U_0402_25V

1
4.7_0603_5%
470P_0402_50V 2

SIS406DN-T1-GE3_PAK1212-8-5
PC34

2
0.1U_0402_25V7K

5
2 1
PQ23

PQ22
2N7002WT1G 1008@Nick BQ24780_BATDRV 4

1
S

D
3 1 PC35

1
2
3
1U_0603_25V7-K PC36

499K_0402_1%

0.01U_0603_50V7K
2

1
0.1U_0402_25V7K 2

PR85
G
2

1
PR89

PC37
2 1 2 1 10_0402_1%

1
PR88 1

2
PR86 PR87 VSYSTEM B+ 10_0402_1%
1M_0402_5% 1M_0402_5%

2
PD20 PR90
RB751V-40 1K_0402_1%

2
2

2
RB751V-40
PD18

RB751V-40
PD15
1 2
DOCK_CONSUMP <34>
1 2
1 2
B+
C @ PC38 EMC@RF_NS@ RF@ C

10U_0805_25V6K

10U_0805_25V6K
1

1
100P_0402_50V8-J

2200P_0402_25V7-K

47P_0402_50V8-J
PR274 VSYSTEM
2N7002WT1G

1 1
4.02K_0603_1%

4.02K_0603_1%

68P_0402_50V8-J
1

1
@ 0_0402_5% D

PC41

PC42
PC238

PC239
PC40
1

ACN
ACP
1 2 2
PQ44

<62> ACOFF
PR91

PR92

2
2
S 2 2

432K_0603_1%
3
2

5
PR93 BQ24780_VDD
2

1
PR273

PR94
10_1206_5%
2

10K_0402_1% PC44 PC43

ACN
ACP
1 2 1U_0603_25V 2.2U_0603_25V6M

1
2 1 28 24 1 2
1

2
PR95 64.9K_0603_1% VCC REGN 4 PQ24
1 2 6 PR96 PC46 SIS412DN-T1-GE3
ACDET 2.2_0603_5% 0.047U_0603_25V
PC45 0.1U_0402_25V7K 25 BST_CHG1 2 2 1
BTST PR97

3
2
1
BQ24780RUYR_QFN24_4X4 PL4 0.01_1206_1%
3 26 DH_CHG 4.7UH_PCMB104T-4R7MS
CMSRC HIDRV 1 2 CHG 1 4 BATT+
4
@ PR98 10K_0402_1% ACDRV 2 3

5
2 1 27 LX_CHG
+3VALW PHASE EMC@

2
<62> ACPRN

3.3_0603_5%
@ PR99 1 2 0_0402_5% 5
ACOK

PR101
@ PR100 1 2 0_0402_5% 11

10U_0805_25V6-K

10U_0805_25V6-K
<62,66> EC_SMB_DA1 SDA PU7 23 DL_CHG 4
LODRV

2
@ PR102 1 2 0_0402_5% 12 22
<62,66> EC_SMB_CK1 SCL GND PQ25 EMC@

PC47

PC48
1
1000P_0402_50V7K
SIS412DN-T1-GE3

3
2
1

1
@ PR103 1 2 0_0402_5% 7 29
<62> ADP_I IADP PAD

PC49
2

1
@ PR104 1 2 0_0402_5% 8 18 BQ24780_BATDRV
IDCHG BATDRV PC50
@ PR105 1 2 0_0402_5% 9 0.1U_0402_25V7K PC51

2
@ PR106 10K_0402_1% PMON 17
B BATSRC 0.1U_0402_25V7K B
2 1
PC52

PC53

PC54

+3VALW PR107 10_0603_5%

20 2 1 SRP
1 2 10 SRP
<5,62,73> VR_HOT#

1
PROCHOT#
2

@ PR108 13 PC55
100P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J

0_0402_5% CMPIN
0.1U_0402_25V7K
BATPRES#

2
TB_STAT#

14 PR109 10_0603_5%
1

CMPOUT 19 2 1 SRN
21 SRN
ILIM
2

@ PR110
16

15

0_0402_5%

PR113 PR111
1

316K_0402_1% 18.2K_0402_1%
1 2 1 2
+3VALW BATT_TEMP <62,66>
0102@Nick
1
1

PR117
PC56 100K_0402_1%
0.1U_0402_25V6
2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/05 Deciphered Date 2014/12/31 CHARGER

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 67 of 81
5 4 3 2 1
 5 4 3 2 1

PJ2
2 1
+3VALWP 2 1 +3VALW
@ JUMP_43X118

D D
PJ3
2 1
+5VALWP 2 1 +5VALW
@ JUMP_43X118
VL +3VL

4.7U_0603_10V6-M

0_0603_5%
4.7U_0603_10V
0_0603_5%
1

2
3V5V_VIN

19.6K_0402_1%

17.8K_0402_1%

2
PC57 1 1
0.1U_0402_25V7K

1
PJ4
3V5V_VIN

1
3V5V_VIN

PR121
RF_NS@ EMC@ EMC@

1
2 2

PC58

PR119

PC59
2 1

47P_0402_50V8-J
B+

1
2 1

2200P_0402_25V

10U_0805_25V6-K

10U_0805_25V6-K
EMC@ EMC@ RF_NS@

PC66
@ JUMP_43X118 @

0.1U_0402_25V6
1

CS2 2

1
PC69

PC70

PC67
PR118

PR120
@
10U_0805_25V6-K

10U_0805_25V6-K

47P_0402_50V8-J
0.1U_0603_25V7K

CS1 2
1

1
+3VALW
PC63

PC65

PC68
PC64
EMC@ +3VLP
2200P_0402_25V7-K
PC60

PC62

2
2
PC61 @ PR141 2
2

2
5
2
0.1U_0402_25V6

100K_0402_1%

12

13
5

3
PQ26
SIS412DN-T1-GE3

VIN

CS2

CS1

LDO5

LDO3
1
21
7 GND 4
PGOOD PQ27
4 16 UG_5V SIS412DN-T1-GE3
UG_3V 10 UGATE1 PR122 PC72
C C
PC71 PR123 UGATE2 2.2_0603_5% 0.1U_0603_25V7K
PU8

3
2
1
0.1U_0603_25V7K 2.2_0603_5% 17 BST_5V 1 2 1 2
1 2 1 2 BST_3V 9 BOOT1 PL5
+5VALWP
1
2
3

PL6 BOOT2 2.2UH_PCMB063T-2R2MS_20%

+3VALWP 2.2UH_PCMB063T-2R2MS_20%
PHASE1
18 LX_5V 1 2
1 2 LX_3V 8
PHASE2

5
RT6585BGQW_WQFN20_3x3 15 LG_5V

220U_B2_6.3VM_R25M
EMC_NS@ LGATE1 EMC_NS@ EMC@EMC@
2

2
LG_3V 11
EMC@EMC@ PR124 LGATE2 14 PR125

2200P_0402_25V7-K
220U_B2_6.3VM_R25M

0.1U_0603_25V7K
4.7_0603_5% BYP1 4.7_0603_5%

VCLK
0.1U_0603_25V7K

EN2

EN1
FB2

FB1
2200P_0402_25V7-K

1
+

PC78

PC79
4
1

1
1

PC75
4
0.1U_0402_25V6

20

19

2
2

2
PC73

PC76

PC74

@ PC77

PR126

51.1_0402_1%
PQ29
EMC_NS@

2
2
13K_0402_1% PQ28 SIS472DN-T1-GE3 2
2

1
2 SIS472DN-T1-GE3 PC80 PR127
EMC_NS@
1

3
2
1
2

PR233
680P_0402_50V 30K_0402_1%
1

1
2
3

1
PC81

FB_5V

0.1U_0402_25V6
@ PC82
680P_0402_50V
1

2
FB_3V

PR129
2.2K_0402_1%
2

1 2 0224@PWR
B 3VALW <62> EC_ON B

1
TDC: 8A PR128
5VALW
20K_0402_1%
OCP: 11A 1 2 PR130 TDC: 8A
<62,65,66> MAINPWON_EC
1

FSW: 475KHz 19.6K_0402_1%

OCP: 11A

2
1

PD17
RB751V-40
PC83
0.1U_0402_25V6
Fsw: 400KHz
2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/05 Deciphered Date 2014/12/31 3VALW/5VALW

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 68 of 81
5 4 3 2 1
 A B C D

PJ5
2 1
2 1
@ JUMP_43X118

PJ6 +1.35V
+1.35VP 2 1
2 1
1
@ JUMP_43X118 1

+1.35VP PJ7
2 1
PJ8 +0.675VSP 2 1 +0.675VS
B+

1
2 1 B+_1.35V
2 1 PC84 @ JUMP_43X39
@ JUMP_43X79 RF_NS@ RF@ EMC@ EMC@ 10U_0603_6.3V6M

2200P_0402_25V
68P_0402_50V8J

0.1U_0402_25V6

2
10U_0805_25V6-K

10U_0805_25V6-K
47P_0402_50V8-J
1

1
PC85

PC86

PC88

PC89

PC87
PC90
@ PR131
100K_0402_1%

2
2 2 1
+3VALW

+0.675VSP
PR132

162K_0402_1%
100K_0402_1% +0.675VSP

+1.35VP
1 2

PR133

10U_0603_6.3V6M

0.1U_0402_6.3V7-K
2

1
PC92

PC93
5

14

11

13

19

20

2
PQ30

PGND

VID

CS

VLDOIN

VTT
SIS412DN-T1-GE3 PR134 21
2.2_0603_5% PAD
4 1 2 1 2 18 1
BOOT VTTGND
PC91
0.22U_0603_25V7K DH_1.35V 17
UGATE VTTSNS
2 +0.675VSP
PL7

1
2
3
2
1UH_PCMC063T-1R0MN_+-20% 2

PU9 3 VTTREF_0.675V
1 2 LX_1.35V 16 GND
RT8231AGQW
+1.35VP PHASE
4 VTTREF_0.675V
EMC@EMC@ EMC_NS@ VTTREF
2

PR136

5
2200P_0402_25V7-K

PR135 DL_1.35V 15 5.1_0603_5%

LGATE +0.675VS
1

4.7_0603_5% 12 2 1
470P_0402_50V7K
330U_D2_2V_R9M
0.1U_0402_25V6

1 VDD +5VALW
TDC: 1.5A

1
PGOOD
1
1

+
PC94

PC95

PC96

@ PC97

PQ31 5 1 PC98

TON
1

SIS472DN-T1-GE3 VDDQ 0.033U_0402_16V7K

FB

S5

S3

2
PR137 4 PC99
2

2 2 8.06K_0402_1% 1U_0402_10VA-K

10
2
EMC_NS@
2

PC100

2 TON_1.35V

S5_1.35V

S3_1.35V
1
2
3

680P_0402_50V7K PR139
1
1

100K_0402_1%
PR138 1 2 +3VALW
10K_0402_1%
@ PR162

887K_0402_1%
0_0402_5% SM_PG_CTRL <18>
2

PR140
1 2
1.35V FB_1.35V
TDC: 7.4A
OCP: 9.3A

1
B+_1.35V SUSP# <43,61,62,70,71,76>
Fsw: 285KHz@20V @ PR142
0_0402_5%
1 2

276KHz@9V 1 2 @ PR144
<61,62> SYSON 0_0402_5%

1
3 3

@ PC102

2
0.1U_0402_6.3V7-K

2
1
@PC101
@ PR143
0.1U_0402_16V

2
47K_0402_5%

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/05 Deciphered Date 2014/12/31 +1.35V/+0.675VS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 69 of 81
A B C D
 5 4 3 2 1

D D

PR145
@ 0_0402_5%
1 2
<43,61,62,69,71,76> SUSP#

1
PR146
1M_0402_5% PC103
0.1U_0402_16V

2
1
B+ PJ9
2 1 8 1 @ PR147 PC104
2 1 IN EN 0_0603_5% 0.1U_0603_25V PL8
EMC@

10U_0805_25V

0.1U_0402_25V
@ JUMP_43X79 6 BS_1.05VS 1 2 1 2 0.68UH_PCMB063T-R68MS_+-20%
1 BS

1
PC105
+1.05VS_VCCPP

PC106
9 10 SW_1.05VS 1 2
GND LX
2

2
PU10 4 FB_1.05VS
3 FB
C ILMT +3VALW C

2
7
+3VS BYP EMC_NS@
@ PR149 SYX198DQNC PR148 EMC@EMC@

2200P_0402_25V
22U_0805_6.3V6-M

22U_0805_6.3V6-M

22U_0805_6.3V6-M

22U_0805_6.3V6-M

0.1U_0402_25V
0_0402_5% 2 4.7_0603_5% 1 1 1 1
PG

1
PC113

PC112
1 2 5
+1.05VS

1
LDO

PC108

PC109

PC110

PC111
4.7U_0402_6.3V
TDC: 7A

2
1
2 2 2 2

PC107
2 1

4.7U_0402_6.3V
EMC_NS@ OCP: 8A

2
Fsw: 560KHz

PC114
PR150 PC115

2
2

100K_0402_5%
@ PR151 680P_0402_50V

1
0_0402_5%
PR152
@ 0_0402_5%
1

1 2
<10,14,62> 1.05VS_PGOOD

2
PC116

1
330P_0402_50V

1
B PR262 PR153 B
10K_0402_1%
1K_0402_1%

2
+1.05VS_VCCPP PJ10 +1.05VS
2 1
2 1

1
PR154 @ JUMP_43X118
13.3K_0402_1%

2
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/05 Deciphered Date 2014/12/31 +1.05VS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 70 of 81
5 4 3 2 1
 5 4 3 2 1

D D

@ PR155
0_0402_5%
<43,61,62,69,70,76> SUSP# 1 2

1
PR156
1M_0402_5% PC117
0.1U_0402_16V

2
1
B+ PJ11
2 1 8 1 @ PR157 PC118
2 1 IN EN 0_0603_5% 0.1U_0603_25V7K PL9
EMC@

10U_0805_25V

0.1U_0402_25V
@ JUMP_43X79 6 BS_1.5VSP 1 2 1 2 0.68UH_PCMB063T-R68MS_+-20%
1 BS

1
+1.5VSP
PC119

PC120
9 10 SW_1.5VSP 1 2
GND LX
2

2
PU11 4 FB_1.5VSP
3 FB
C ILMT +3VALW C

2
7
+3VS BYP EMC_NS@ EMC@EMC@
@ PR159 SYX198DQNC PR158

2200P_0402_25V
22U_0805_6.3V6-M

22U_0805_6.3V6-M

22U_0805_6.3V6-M

22U_0805_6.3V6-M

0.1U_0402_25V6
0_0402_5% 2 4.7_0603_5% 1 1 1 1
PG

1
PC128

PC121
1 2 5

1
LDO

PC124

PC125

PC126

PC127
4.7U_0402_6.3V6-M
+1.5VS

2
TDC: 5.6A

1
2 2 2 2

PC123
4.7U_0402_6.3V6-M
2 1
EMC_NS@

2
OCP: 8A

2
PC122
PR160 PC129

2
2

100K_0402_5% 680P_0402_50V Fsw: 650KHz

1
@ PR161
0_0402_5%

2
PC130
1

330P_0402_50V

1
2

1
PR163
PR261
30.1K_0402_1%
B 1K_0402_1% B

2
1
PR164
+1.5VSP PJ12 +1.5VS
20K_0402_1% 2 1
2 1
@ JUMP_43X118

2
PJ20
2 1
2 1
@ JUMP_43X118

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/05 Deciphered Date 2014/12/31 +1.5VS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 71 of 81
5 4 3 2 1
 5 4 3 2 1

D D

PL10 DIS@

4
PJ13 1UH_PH041H-1R0MS_20%
2 1 VIN_+1.8VSP 10 1 1.8VSP_LX 1 2
+5VALW

PG
2 1 PVIN2 LX1 +1.8VSP
DIS_EMC_NS@

2
@ JUMP_43X79 9 2
PVIN1 LX2

1
C
PR165 C

1
PC131 PC132 8 3 4.7_0603_5%
10U_0603_10V 10U_0603_10V SVIN1 LX3 PR166 PC133
DIS_EMC@

2
DIS@ DIS@ DIS@ PU12 20K_0402_1% 22P_0402_50V
DIS_EMC_NS@

2 1

22U_0805_6.3VAM

22U_0805_6.3VAM

0.1U_0402_25V6
RT8068AZQW DIS@ DIS@

1
5 6 PC134

GND
EN FB

DIS@ PC135

DIS@ PC136

PC138
DIS@ PR167

NC
<11,20,29,76,77> VGA_ON 22K_0402_1% 680P_0402_50V

2
1 2 EN_1.8VSP

11

7
+1.8VS_VGA
TDC: 1.3A

2
1 2

1
@ PR168
Fsw: 1MHz

1
1M_0402_5% PC139
PD21 0.22U_0402_10V6-K

2
RB751V-40 DIS@ PR169

1
DIS@ 10K_0402_1%
DIS@

2
B B

PJ14
+1.8VSP 2 1 +1.8VS_VGA
2 1

@ JUMP_43X39

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/05 Deciphered Date 2014/12/31 +1.8VS_VGA
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 72 of 81
5 4 3 2 1
 5 4 3 2 1

Place close
to inductor

PC140

1
560P_0402_50V7-K

1
1 2 PR171

1
PR170 75K_0402_1% PRT9
D 26.7K_0402_1% PR172 220K +-5% NCP15WM224J03RC 0402 D
165K_0402_1%

2
1 2 1 2

2
PC142
PC141
470P_0402_50V7-K 1000P_0402_50V7-K
1 2
SWN <74>
PR173
46.4K_0603_1%
TSENSE

CSCOMP
PC143
1000P_0402_50V

2
PC144 Place close

1
2.2U_0603_10V7-K
to MOSFET

1
PC145

1
PR176 330P_0402_50V7-K PC146 PR174

81101_PVCC
49.9_0402_1% 10P_0402_50V8-J 16.9K_0402_1% PR175

CSCOMP
1 2 1 2 1 2 100K_0402_1%

CSSUM

2
2

CSREF

1
CSREF <74>

1
1 2 1 2 PR180
PR179 20K_0402_1% PRT10
PR177 PR178 18K_0402_1% 100K_0402_1%_NCP15WF104F03RC

21

20

19

18

17

16

15
1K_0402_1% 7.5K_0402_1%

2
ILIM

IOUT

CSSUM

CSREF
CSCOMP

IMAX

PVCC
2
PR181
C 22 69.8K_0402_1% C
ROSC 14 2 1
23 VBOOT
COMP 13 TSENSE 1 2
24 TSENSE
<16> VSSSENSE FB 12 81101_LGPC147 0.01U_0402_25V
25 LG 81101_LG <74>
DIFFOUT PU13
2

PC148 NCP81101MNTXG PGND 11

1000P_0402_50V7-K 26
VSN 10 81101_PH
1

27 SW 81101_PH <74>
<14> VCCSENSE VSP 9 81101_HG
HG 81101_HG <74>
1 2 81101_PVCC 28
+5VS VCC 8 1 2 1 2

VR_HOT#

VR_RDY
BST

ENABLE

ALERT#
@ PR184

VRMP
SCLK
2_0603_5% 29 PR185 PC149

SDIO
GND

2
PC150 2.2_0603_5% 0.22U_0603_25V7K
1 2 2.2U_0603_10V7-K
+5VALW

7
PR193
@ PR217 2_0603_5%
0_0402_5% PR186

VR_SVID_DAT_1

VR_SVID_ALRT#_1

VR_SVID_CLK_1
1 2 1K_0402_1%
2 1

VRHOT#
CPU_B+

VRRDY
@ PR187
0_0402_5%
1 2
<14> VR_ON
CPU_GND

1
1
B PC152 B
PC151 .01U_0402_25V7-K

2
+1.05VS_VCCST 0.1U_0402_6.3V7-K

2
<12>
2

PR189 @ PR188 PR190 PC153

130_0402_1% 75_0402_1% 54.9_0402_1% 0.1U_0402_6.3V7-K +1.05VS_VCCST
1
1

@ PR191 VRHOT#
0_0402_5%

2
1 2 VR_SVID_DAT_1
<14> VR_SVID_DAT
@ PR194 PR192 @ PR222
0_0402_5% 10K_0402_1% 0_0402_5%
1 2 VR_SVID_ALRT#_1
<14> VR_SVID_ALRT#
@ PR195 @ PR226
1

1
0_0402_5% 0_0402_5%
1 2 VR_SVID_CLK_1 1 2 VRRDY VR_HOT#
<14> VR_SVID_CLK <14> VGATE

<5,62,67> VR_HOT#

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/05 Deciphered Date 2014/12/31

+CPU_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 73 of 81
5 4 3 2 1
 5 4 3 2 1

0210@GCM request
PL19EMC@
CPU_B+ MURATA BLM18KG300TN1D

1 2
B+
RF_NS@ EMC@ EMC@ PL20EMC@

2200P_0402_50V7K
47P_0402_50V8-J

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6K
1 MURATA BLM18KG300TN1D

1
PC243

PC158

68U_25V_M_R0.36

68U_25V_M_R0.36

68U_25V_M_R0.36
1 1 1
1 2

1
+ + +

PC154

PC155

PC156

@ PC246

PC157

PC159

PC160

PC161
2
D 2 D

2
2 2 2

5
4 PQ33
<73> 81101_HG
TPCA8065-H

3
2
1
PL12 +VCC_CORE
.22UH 20% PCMB104T-R22MS0R825
1 4
<73> 81101_PH
EMC_NS@EMC_NS@

220P_0402_50V7K
68P_0402_50V8J
2 3

PC162

PC163
1

1
EMC_NS@

4.7_0603_5%
V1N_CPU

2
5

PR197
C C
@ PQ35
TPCA8057-H

1
2 1
4 4 CSREF <73>

1SNUB_CPU1
<73> 81101_LG
PR198
PQ34 EMC_NS@ 10_0402_1%

680P_0402_50V7K
TPCA8057-H
+VCC_CORE
3
2
1

3
2
1
TDC: 10A

PC164
SWN <73> MAX: 32A
OCP: 42A

2
FSW: 560KHz@20V
670KHz@9V

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/05 Deciphered Date 2014/12/31
+CPU_CORE2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 74 of 81
5 4 3 2 1
 5 4 3 2 1

Based on PDDG rev 0.7 Table 5-1.

D D

+VCC_CORE

1 1 1 1 1
PC165 PC166 PC167 PC168 PC169
22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM
2 2 2 2 2

1 1 1 1 1
PC170 PC171 PC172 PC173 PC174
22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM
2 2 2 2 2
C C

1 1 1 1 1
PC175 PC176 PC177 PC178 PC179
22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM
2 2 2 2 2

1 1 1 1
PC180 PC181 PC182 PC183
22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM
2 2 2 2

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/05 Deciphered Date 2014/12/31
PROCESSOR DECOUPLING
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 75 of 81
5 4 3 2 1
 5 4 3 2 1

ISL62771 Schematic for FT3 solution 0210@GCM request

PL18 DIS_EMC@
+5VS +5VS MURATA BLM18KG300TN1D
PR199
<43,61,62,69,70,71> SUSP# @ 0_0402_5% +VGA_B+ 1 2

2
1 2
@ PR200 @ PR201 PL13 DIS_EMC@ B+
@ PR202 0_0603_5% 0_0603_5% MURATA BLM18KG300TN1D
0_0402_5% DIS_RF_NS@ DIS_EMC@ DIS_EMC@

DIS@

DIS@
5
<11,20,29,72,77> VGA_ON 1 2 1 2

2200P_0402_50V7K

10U_0805_25V6K

10U_0805_25V6K
47P_0402_50V8-J

0.1U_0402_25V6
1

1
PC244
VDD_62771

PC188
1

1
PC187

PC189

PC190
PC186

2
1

1
+3VS_VGA 0.1U_0402_25V6 PC184 PC185 2
DIS@ 1U_0402_10V 1U_0402_10V 4 PQ36

2
D DIS@ DIS@ TPCA8065-H D

2
DIS@

2
+VGA_CORE

25

26
PR203 PL14 DIS@

3
2
1
10K_0402_1% 0.36UH 20% PDME064T-R36MS1R405

VDDP
VDD
DIS@
1 4

1
@ PR212 8
0_0402_5% ENABLE 2 3

5
1 2 PG_VDD 20 @ PR205
<11,29> DGPU_PWROK
35 PGOOD 0_0603_5% DIS_EMC_NS@ DIS@ DIS_EMC@

2
PGOOD_NB

PR206
21 1 2 1 2 PR207 3.65K_0402_1%

0.1U_0402_25V6
330U_D2_2VM_R9M

330U_D2_2VM_R9M
<20,21> PLT_RST_VGA# BOOT1
@ PR204 1 2 0_0402_5% 9 VSUM+ 1 2 1 1
<21> SVI2_SVC PWROK
@ PR213 1 2 0_0402_5% 3 PC191 DIS@
<21> SVI2_SVD

1
1 2 5 SVC 22 4 + +

PC193

PC198

PC192
@ PR208 0_0402_5% 0.22U_0603_25V
SVD UGATE1

4.7_0603_5%
SVTP@ PAD 1 @ PR209 1 2 0_0402_5% 7 ISEN1 1 2
DIS_EMC_NS@

1
@ PR210 0_0402_5% @ PR214 1 2 0_0402_5% 4 SVT PQ37
+1.8VS_VGA 2 <21,62> GPU_VR_HOT#

2
2
1 6 VR_HOT_L 23 TPCA8057-H PR211 10K_0402_1% 2 2

1
VDDIO PHASE1

PC196
DIS@ DIS@

DIS@

DIS@
3
2
1
@ PR253 0_0402_5% 0210@Nick 1 2PC195 DIS@
+3VS_VGA

1
1 2 PR216 150P_0402_50V8-J 24 PC194

2
22K_0402_1% LGATE1 0.22U_0603_25V

680P_0402_50V
DIS@ 1 2 1 2 19 @ PR220 DIS@ DIS@
+VGA_CORE PC199 PR218 DIS@ PC197 DIS@ COMP 0_0603_5% PC200 PR215 1_0402_1%
<22> VDDC_SEN 1
470P_0402_50V 2 1 2 150P_0402_50V8-J 30 1 2 1 2 VSUM- 1 2
DIS@ 499_0402_1% 1 2 BOOT2 DIS@
1

0224@PWR @ PR219 0.22U_0603_25V7-K

2

PR263 1 2 32.4K_0402_1% 18 29
@ PR221 10_0402_1% PC201 FB UGATE2
1

0_0402_5% DIS@ DIS@ PR223 DIS@ 1 2 1 2 @ 680P_0402_50V7-K

PC202 820_0402_1% 28
2

330P_0402_50V7-K @ PR224 2.7K_0402_1% PHASE2 +VGA_B+

1

16
1

VSEN 27
PC203 DIS@ LGATE2
330P_0402_50V7-K 17 DIS_RF_NS@ DIS_EMC@ DIS_EMC@

DIS@

DIS@
2
2

RTN PU14 DIS@

2200P_0402_50V7K

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
5
@ PR225 PC204 ISL62771HRTZ_TQFN40_5X5
PR264 1000P_0402_25V7-K

47P_0402_50V8-J
0_0402_5% 1
2

1
PC245

PC205

PC207

PC208
10_0402_1% DIS@

PC206
DIS@
1

36 31 VDD_62771

2
C COMP_NB BOOT_NB 4 PQ38 2 C
<22> VDDC_RTN PR229 TPCA8065-H
@ 10K_0402_1% 32 PR268 DIS@
UGATE_NB 10K_0402_1%
1 2 37 DIS@

3
2
1
FB_NB 33 1 2 PL15 DIS@
PHASE_NB 0.36UH 20% PDME064T-R36MS1R405 +VGA_CORE

34 1 2 1 4
38 LGATE_NB
VSEN_NB PR267 2 3

5
10K_0402_1%

2
PR227
PR228 3.65K_0402_1%
DIS@ DIS_EMC_NS@ VSUM+ 1 2 DIS_EMC@

DIS@

DIS@
VSUM+ 14 13 ISEN1 DIS@

0.1U_0402_25V6
330U_D2_2VM_R9M

330U_D2_2VM_R9M
ISUMP ISEN1
1 1 VGA
DIS@
PR234

4.7_0603_5%
12 ISEN2 4 ISEN2 1 2

1
TDC: 31A

1
15 ISEN2 + +

PC212

PC209

PC214
PR230 10K_0402_1%
DIS_EMC_NS@
1

2
ISUMN PQ39 DIS@
OCP: 48A

1
DIS@
PR235

TPCA8057-H

2
2 2
Fsw: 300KHz
2.61K_0402_1%

PC213
DIS@ PC211

3
2
1

1
1

0224@PWR 40 0.22U_0603_25V

2
ISUMP_NB
PC216
DIS@

PC217
DIS@

@ PC215

DIS@
2

11K_0402_1%

@ PR231

680P_0402_50V7K
1 39 PR232 1_0402_1%
1

ISUMN_NB
PR236
DIS@

DIS@ VSUM- 1 2
2

1
0.1U_0402_25V7K

PR266 100K_0402_1% DIS@

2
2
CLOSE
DIS@
PRT11

82N_0402_50V

330P_0402_50V

1 1 2
2

2 NTC_NB
@ PR237

11
NTC
0_0402_5%

1
1

649_0402_1%

10
2

IMON
10K_0402_NTC

2
1

IMON_NB

27.4K_0402_1%
PR239

DIS@

PRT12
DIS@
TP
PL14

100_0402_1%

1
2

41

1001@Nick
DIS@
PR265

DIS@
PC219

DIS@
PR240

470K_0402NEW_3%
1

VSUM-

2
2
2

100K_0402_1%

0.1U_0402_25V

130K_0402

PC218
1

B B
0.1U_0402_25V6
1

DIS@ BOTTOM PAD

DIS@
PR238

CONNECT TO GND
1

Through 8 VIAs
10.7K_0402_1%
2

CLOSE PQ36

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/05 Deciphered Date 2014/12/31 +VGA_CORE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 76 of 81
5 4 3 2 1
 5 4 3 2 1

D D

PL16 @
1UH_PH041H-1R0MS_20%

4
PJ16
2 1 VIN_+0.95VSP 10 1 0.95V_LX 1 2
+5VALW

PG
2 1 PVIN2 LX1 +0.95VSP

2
C
@ JUMP_43X79 9 2 EMC_NS@ C
PVIN1 LX2

1
PR241

1
22P_0402_50V
PC222 @
PC220 PC221 8 3 4.7_0603_5%
10U_0603_10V 10U_0603_10V SVIN1 LX3 PR242
EMC_NS@

1
@ @ @ PU15 5.9K_0402_1%

22U_0805_6.3VAM

22U_0805_6.3VAM

0.1U_0402_25V6
RT8068AZQW @
EMC_NS@

2
2

PC227
5 6

GND
EN FB

@ PC224

@ PC225
@ PR243 PC223

NC
<11,20,29,72,76> VGA_ON 22K_0402_1% 680P_0402_50V

2
1 2 EN_0.95V

11

7
+0.95VS_VGA

2
TDC: 2.2A

1
@ PR244

1
1M_0402_5% PC228
@ 0.22U_0402_10V6-K Fsw: 1MHz

2
PR245

1
10K_0402_1%
@

2
B B

PJ17
2 1
+0.95VSP 2 1 +0.95VS_VGA
@ JUMP_43X79

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/05 Deciphered Date 2014/12/31
+0.95VS_VGA
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 77 of 81
5 4 3 2 1
 5 4 3 2 1

D D

0_0402_5%
PR269
1 2
PCH_APWROK <10>
VPRO@

PL17 VPRO@
1UH_PH041H-1R0MS_20%

4
PJ18
2 1 VIN_+1.05VMP 10 1 SBA_LX 1 2
+5VALW

PG
2 1 PVIN2 LX1 +1.05VMP

2
C C

22P_0402_50V
4.7_0603_5%
@ JUMP_43X79 9 2
PVIN1 LX2

1
7.5K_0402_1%

VPRO@
1
@ PR246

PC231
VPRO@
PC229 PC230 8 3
SVIN1 LX3

22U_0805_6.3VAM

22U_0805_6.3VAM
PR247
10U_0603_10V 10U_0603_10V

1
680P_0402_50V7K

0.1U_0402_25V6
VPRO@ VPRO@ VPRO@ PU16

VPRO@ PC233

VPRO@ PC234

VPRO@ PC236
RT8068AZQW

2
2

1
5 6

GND
EN FB

@ PC232
NC

2
1 2 EN_SBA

11

7
<61,62> VM_PWRON

0.1U_0402_10V7K
PR248
+1.05VM

2
1M_0402_5%

VPRO@
0_0402_5%
TDC: 1A

1
@ PR249

PC237
VPRO@

1
10K_0402_1%
Fsw: 1MHz

PR250

VPRO@
1

2
B B

PJ19
2 1
+1.05VMP 2 1 +1.05VM
@ JUMP_43X39

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/05 Deciphered Date 2014/12/31
+1.05VM
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 78 of 81
5 4 3 2 1
 5 4 3 2 1

POWER PIR (Product Improve Record)

AILE1 NM-A151 SCHEMATIC CHANGE LIST
REVISION CHANGE: 0.1
GERBER-OUT DATE: 2013/01/16
NO DATE PAGE MODIFICATION LIST PURPOSE
---------------------------------------------------------------------------------------------------------------------

D D

+5VALW
RICHTEK +5VALW
RT6585BGQW RICHTEK
+3VALW RT8068AZQW +0.95VS_VGA
Switch Mode Switch Mode
B+ EC_ON EN1
Adaptor in FOR System VREG5 VL VGA_ON EN
EN2
SW VREG3 +3VL

+1.35V
RICHTEK RICHTEK
RT8231AGQW RT8068AZQW +1.8VS_VGA
Switch Mode +0.675VS Switch Mode
SYSON S5
FOR DDR3L VGA_ON EN
C S3 C

SM_PG_CTRL

RICHTEK
B+ TI Silergy RT8068AZQW +1.05VM
+1.5VS Switch Mode
BQ24780RUYR SY198D VM_PWRON
EN
Battery Charger Switch Mode
SUSP# EN
Switch Mode
SMBus

Silergy +1.05VS
SY198DMode
Switch
SUSP# EN PGOOD 1.05VS_PGOOD

B B

ON SEMI
NCP81101MNTXG +VCC_CORE
PWM_VID VIDs Switch Mode
Battery B+ FOR CPU VDDC
PGOOD VGATE
VR_ON EN
SW

Intersil +VGA_CORE
ISL62771HRTZ
Switch Mode
FOR GPU Core
VGA_ON EN PGOOD DGPU_PWROK

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/05 Deciphered Date 2014/12/31 PWR-PIR

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 79 of 81
5 4 3 2 1
 5 4 3 2 1

HW PIR (Product Improve Record)

AIVE1 NM-AXXX SCHEMATIC CHANGE LIST
REVISION CHANGE: 0.1
GERBER-OUT DATE: 2013/10/15
NO DATE PAGE MODIFICATION LIST PURPOSE
---------------------------------------------------------------------------------------------------------------------

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/09/07 Deciphered Date 2014/09/07 XXXX

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 80 of 81
5 4 3 2 1
 5 4 3 2 1

Gordon SDV LOGIC SCHEMATICS NMA-221

1.COVER PAGE 36.HP/MIC JACK/Speaker
VER 0.1
2.BLOCK DIAGRAM 37.SATA HDD/ODD CONN. Nov/13/2013
D D

3.NOTE LIST 38.eDP/CMOS CONN.

4.VGA NOTE 39.USB30 RP --> BLANK
5.BDW_DDI/EDP/XDP 40.USB3 PORT1-BACK 71.+1.5VS(SYX198DQNC)
6.BDW_DDR3L INT 41.USB3 PORT2-FRONT(AOU) 72.+1.8VS_VGA(RT8068A)
7.BDW_RTC/HDA/SATA/PCIe/JTAG 42.MUX IC 73.+VCC_CORE(NCP81101MNTXG)
8.BDW_CLOCK/PM 43.DP TO VGA 74.+VCC_CORE2
9.BDW_LPC/SPI/SM BUS 44.VGA CONN. 75.PROCESSOR DECOUPLING
10.BDW_SYS PM 45.HDMI RP --> BLANK 76.+VGA_CORE(ISL62771)
11.BDW_eDP SBAND/DDPx 46.HDMI CONN. 77.+0.95VS_VGA(RT8068A)
C
12.BDW_GPIO/SIO 47.GBE LAN PHY 78.+1.05VM(RT8068A) C

13.BDW_PCIE/USB BUS 48.RJ45 CONN. 79.PWR-PIR

14.BDW (Power) 49.CP/TPOINTCONN. 80.HW PIR
15.BDW (Power2) 50.PBTN/LID/FP/FAN CONN.
16.BDW (VSS) 51.KB/RTC/TOUCH PAN CONN.
17.BDW (OTHER) 52.WWAN/WLAN NGFF CONN.
18.DDR3L DIMM1 53.SUB CONN. --> BLANK
19.DDR3L DIMM2 54.SUB-AUDIO JACK CONN.
20.Opal & Jet PCIE 55.THERMAL SENSOR
21.Opal & Jet GPIO 56.G SENSOR/TPM
B
22.Opal & Jet Core Power 57.BLANK B

23.Opal & Jet DP Power/GND 58.BLANK

24.Opal & Jet MEM Interface 59.BLANK
25.Opal & Jet DDR3 VRAM U 60.BLANK
26.Opal & Jet DDR3 VRAM L 61.DC V TO VS/ V-PCH/VM
27.Opal 22 TO 24 VRAM U2 62.EC_IT8586E/FX
28.Opal 23 TO 25 VRAM L2 63.PLM/SCREW HOLE
29.Opal & Jet swich power 64.BLANK
30.BLANK 65.DCIN / Vin Detector
31.BLANK 66.BATTERY CONN/OTP
A A

32.CARDREADER IC/CONN. 67.CHARGER(BQ24780)

33.DP RP --> BLANK 68.3V/5VALW(RT6585B)
34.DOCKING/ DCIN CONN 69.+1.35V/+0.675V(RT8231A) Security Classification LC Future Center Secret Data Title

35.CX20751 70.+1.05VS(SYX198DQNC) Issued Date 2013/09/07 Deciphered Date 2014/09/07

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
COVER PAGE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AITE1_NM-A221
Date: Thursday, November 06, 2014 Sheet 81 of 81
5 4 3 2 1