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Evaluates: MAX17330 MAX17330 Evaluation Kit: General Description Quick Start
Evaluates: MAX17330 MAX17330 Evaluation Kit: General Description Quick Start
Evaluates: MAX17330 MAX17330 Evaluation Kit: General Description Quick Start
+ SOURCE/LOAD –
ALRT
SYSP SYSN
SCL GND
SDA
USB MICRO B PC
CONNECTOR
MAX17330X2EVKIT
PKWK
J2
ALRTWK
BATTP BATTN
RT2+
RT1+ RT-
CELL
● The Registers tab allows the user to view and modify be recalled and viewed from the IC.
common fuel gauge registers one at a time. ● If SBS Mode is enabled on the IC, the SBS tab is
● The Commands tab allows for special operations displayed to show the SBS Memory Map.
such as initializing the fuel gauge logging and perform- ● The I2C Traffic Log tab maintains a log of any special
ing fuel gauge reset. communication with the IC.
● The Configuration tab allows the user to modify the All tabs are described in more detail in the following sec-
NVMemory registers one at a time, but any changes tions.
here are not written to NVMemory.
● The Authentication tab allows the user to send and ModelGauge m5 Tab
verify the SHA commands. The ModelGauge m5 tab in Figure 4 displays the impor-
tant output information read from the IC. Information is
● The History tab allows all of the history information to
grouped by function and each is detailed separately.
Authentication Tab the IC, enter the known secret value for the IC connected
The Authentication tab in Figure 10 allows full evaluation to GUI. Click Clear Secret to reset the key values in the
of the SHA-256 security feature. Each group box of the IC to 0. Please note that is not possible to clear secret
Authentication tab is described in detail in the following if the secret is locked. Click Lock Secret to perma-
sections. nently lock the secret value for the IC. Secret Changes
Remaining shows the remaining chances to update the
SHA Challenge/ROM ID SHA Secret value.
The 160-bit SHA-256 Challenge message consists of ten
16-bit Challenges. To manually enter the challenge mes- Authentication Result
sage, click the hex value field of each challenge number This group box provides four methods to perform authen-
and edit the value in the text box. Click the Randomize tication evaluation. When the authentication process
Challenge button to create a random challenge message. begins, the IC will calculate MAC based on the challenge
and stored secret value. The GUI, which represents
SHA Secret the host-side processor, will also calculate based on
The 160-bit SHA-256 Secret key consists of ten 16-bit Challenge and known secret. If the SHA Secret is entered
Secret values. Unless the secret is specifically pro- correctly matching the programmed secret state in the IC,
grammed by Maxim Integrated for the customer, the the authentication should succeed given any challenge
default key value is 0. To prepare for authentication with using any of the four methods. Compute MAC with ROM
ID will compute MAC results based on chip ROM ID that istics change. This column of memory will be updated by
is specific to the chip. Compute MAC without ROM ID the IC through usage cycles as the IC observes changes
would not involve ROM ID into computation, which means to the battery capacity, observed MaxMin voltages,
the MAC result for every chip given the same challenge currents, temperatures, and any battery faults. The
and secret should be the same. Compute Next Secret updates are saved to nonvolatile memory and can be
commands will not only compute authentication result, read over I2C.
but also update the secret value [Secret0–Secret9]
In the Read History group box, click the Read Battery
to [MAC6–MAC15]. If there are no Secret Changes
History button to initiate the nonvolatile history recall pro-
Remaining displayed in the SHA Secret group or the
cess. Once the process is initiated, it takes a while to load
Secret is locked, the Secret will not update.
the nonvolatile history from the IC. Click the Read Battery
History Tab History and Save to File to save the nonvolatile history
The History tab visualizes all nonvolatile update history to a .csv file in addition to initiate the nonvolatile history
on the 0x1Ax column of the nonvolatile memory map. recall process. After the recall process is finished, enter in
Figure 11 shows the History Tab. This column of nonvola- the page number or select + or – sign to browse through
tile memory features the Fibonacci Saving mechanism to the nonvolatile history at the Display History Data tool.
help the IC efficiently learn and adapt to battery character- The detailed information of the specific page selected will
be displayed in the Logging History section.
Charger configuration continues on Step 4 and Step 5, Step 5 configures the HeatLim (Package Power rating) of
as shown in Figure 14. In Step 4, Step-Charging may the FET in mW, the FET Temperature limit in °C, and the
be enabled, and the voltage and current for each battery FETTheta, which is used to approximate the FET temper-
state may be set. These parameters are based on room ature when the second thermistor (TH2) is used. The FET
temperature, and if JEITA Charging is enabled, the cur- temperature is calculated with the equation FETTemp =
rents will scale relative to the maximum charging current DieTemp + (TH2 - DieTemp) x FETTheta.
for that temperature.
From Step 6 to Step 7, the user can edit the Internal Self- tion of current consumption by lowering the rate of ADC
Discharge Detection and Discharge protection param- sampling. Enabling Deepship mode will open the FETs
eters. See Figure 15 and Figure 16. The parameters and shut-down any protection functionality during ship-
include detailed protection configurations, thresholds, and ping and storage conditions. In Step 8, check the Battery
timings. Step 8 configures permanent fail and some addi- Out option to allow the communication stop shutdown
tional FET control options. In Step 9, choose the power feature. Check Pushbutton Wakeup to allow wakeup
mode for the IC. Enabling hibernate mode allows reduc- MAX17330 using the ALRT pin.
Step 11 sets up the temperature measurement functions of the IC. Select the thermistors and their usage in the drop-
down list, and the thermistor coefficients in this step. If there is a special thermistor requirement, look for the NTC model
with the closest Beta value in the drop-down list, or enter the value in the Beta field.
From Step 12 to Step 20, follow the step description the final configuration is decided, choose the third option
to fill out all the application-specific information. Unless Write New Configuration to Non-volatile Memory.
needed, leave options from step 12 to step 18 as default. It is recommended to check Save New Configuration
In Step 20, the GUI updates the IC based on previous Settings to .INI file. This allows the resulting configura-
configuration steps. See Figure 18. The non volatile con- tion in previous steps to be recorded in a Complete.INI
figuration memory can only be updated 7 times. Users file. When the configuration wizard is closed, the previous
can choose to only update RAM by selecting the second configurations will not be remembered. Click the Update
option. This is a good method to evaluate previous settings IC button to execute the changes and save the file. Click
without updating the nonvolatile memory. In this mode, if the Close button to exit the configuration wizard without
the IC is power cycled, the configuration will be lost. If doing anything.
Hardware Connection Guideline the BATTP pin to rise above the absolute maximum
When evaluating the MAX17330 EV kit with high current rating of 6V, damaging the IC permanently. Figures 20
or evaluating protection functionality, use real batter- and 21 shows good examples of battery connection using
ies instead of power supplies. When connecting bat- soldered connections, battery connectors, and its corre-
teries, use a soldered connection instead of jumper sponding BATT voltage waveform during switching event.
cables. During protector switching event, the impedance Figures 22 and 23 show bad examples of battery connec-
(inductance) of the lab jumper cables and power supply tion using lab jumper wires and their corresponding BATT
can cause an overshoot on battery voltage. This volt- voltage waveform.
age spike could potentially cause the voltage across
Figure 20. Good hardware connection example (Use real batteries and soldered connections)
CH1 LOW
3.86V
CH1 MAX
4.78V
CH4 HIGH
4.19A
CH4 LOW
210mA
4µs/div
Figure 21. BATT voltage and battery current waveform at overcurrent protection event with good connection
Figure 22. Bad hardware connection example (using lab jumper cable)
CH1 LOW
3.64V
CH1 MAX
5.88V
CH4 HIGH
4.21A
CH4 LOW
230mA
4µs/div
Figure 23. BATT voltage and battery current waveform at overcurrent protection event with bad connection
C0402C105K8PAC;
2 C1, C4, C7, C26 — 4 KEMET;YAGEO 1UF CAP; SMT (0402); 1UF; 10%; 10V; X5R; CERAMIC
CC0402KRX5R6BB105
GRM155R71E104KE14;
C2, C12-C15,
C1005X7R1E104K050BB; MURATA;TDK;
3 C21, C22, C24, — 20 0.1UF CAP; SMT (0402); 0.1UF; 10%; 25V; X7R; CERAMIC
TMK105B7104KVH; TAIYO YUDEN;TDK
C25, C28-C38
CGJ2B3X7R1E104K050BB
C1005X5R1E474K050;
4 C3 — 1 TDK;MURATA 0.47UF CAP; SMT (0402); 0.47UF; 10%; 25V; X5R; CERAMIC
GRT155R61E474KE01
5 C5 — 1 C0402H102J5GAC KEMET 1000PF CAP; SMT (0402); 1000PF; 5%; 50V; C0G; CERAMIC
6 C6, C9 — 2 GRM155R71A104JA01 MURATA 0.1UF CAP; SMT (0402); 0.1UF; 5%; 10V; X7R; CERAMIC
7 C11 — 1 GRM155R71H223KA12 MURATA 0.022UF CAP; SMT (0402); 0.022UF; 10%; 50V; X7R; CERAMIC
ZRB15XR61A475ME01;
CL05A475MP5NRN; MURATA;SAMSUNG;
8 C20, C23, C27 — 3 4.7UF CAP; SMT (0402); 4.7UF; 20%; 10V; X5R; CERAMIC
GRM155R61A475MEAA; MURATA;TDK
C1005X5R1A475M050BC
FAIRCHILD
14 D8 — 1 RB751S40 RB751S40 DIODE; SCH; SMT (SOD-523F); PIV=40V; IF=0.03A
SEMICONDUCTOR
DIODES INCORPORATED;
ST MICROELECTRONICS;
2N7002;2N7002; TRAN; ; NCH; SOT-23; PD-(0.33W); IC-(0.5A); VCEO-(60V);
21 Q1 — 1 ON SEMICONDUCTOR; 2N7002
2N7002;2N7002 -55 DEGC TO +150 DEGC
MICRO COMMERCIAL
COMPONENTS
ERJ-2RKF27R0X; PANASONIC;
25 R2, R9 — 2 RC0402FR-0727RL; YAGEO PHICOMP; 27 RES; SMT (0402); 27; 1%; +/-100PPM/DEGC; 0.0630W
CRCW040227R0FK VISHAY DALE
26 R5 — 1 KRL1220E-M-R010-F SUSUMU CO LTD. 0.01 RES; SMT (0805); 0.01; 1%; +/-50PPM/DEGC; 0.5W
RC0402FR-071KL; YAGEO;
27 R6, R16, R34 — 3 1K RES; SMT (0402); 1K; 1%; +/-100PPM/DEGC; 0.0630W
MCR01MZPF1001 ROHM SEMICONDUCTOR
CRCW04024K02FK;
VISHAY;
35 R18 — 1 ERJ-2RKF4021; 4.02K RES; SMT (0402); 4.02K; 1%; +/-100PPM/DEGC; 0.0630W
PANASONIC;YAGEO
RC0402FR-074K02L
36 R26 — 1 RC0805JR-070RL YAGEO PHYCOMP 0 RES; SMT (0805); 0; 5%; JUMPER; 0.1250W
CRCW040212K0FK; VISHAY DALE;
37 R33 — 1 12K RES; SMT (0402); 12K; 1%; +/-100PPM/DEGC; 0.0630W
MCR01MZPF1202 ROHM SEMICONDUCTOR
R35, R36,
38 — 4 ERJ-2GE0R00 PANASONIC 0 RES; SMT (0402); 0; JUMPER; JUMPER; 0.1000W
R38, R39
GRM1555C1E102JA01;
53 C16-C18 DNP 0 MURATA;TDK 1000PF CAP; SMT (0402); 1000PF; 5%; 25V; C0G; CERAMIC
C1005C0G1E102J050BA
54 F1 DNP 0 SFR-0405A DEXERIALS SFR-0405A IC; PROT; SELF CONTROL PROTECTOR; SMT ;
58 R20 DNP 0 CRCW040210K0JN VISHAY DALE 10K RES; SMT (0402); 10K; 5%; +/-200PPM/DEGC; 0.0630W
59 R24 DNP 0 RC0805JR-070RL YAGEO PHYCOMP 0 RES; SMT (0805); 0; 5%; JUMPER; 0.1250W
60 C8, C10 DNP 0 N/A N/A OPEN CAPACITOR; SMT (0402); OPEN; FORMFACTOR
61 R3, R4 DNP 0 N/A N/A OPEN RESISTOR; 0402; OPEN; FORMFACTOR
TOTAL 106
0402 0402
S1
EVQ-Q2K03W
1 3
R6
2 4
1K VUSB
0402
10V
C26
MAX17330 Evaluation Kit
1UF
0402
DRN3 U4
1
TP MAX13253ATB+
2
3
Q3 3.3V LDO VDD
D1
D2
FDPC4044 U5 10 T1 EN 4
8 6 MAX8511EXK33+ T1
D5 TGM-040P3RL
S1 S2
CLK 2
7 5 3P3V 5 1 C A 8 8 1 1 8 T2
OUT IN
S1 S2
HICLK 3
MBR0520
10V 7 7 2 2 6 FAULT
10V 4 N.C. 3
C11 R46 SHDN
C1 C9 6 6 3 3 SPRD 5
0.022UF GND
G1
G2
470 1UF 0.1UF D6 C27
2
0402 0402 0402 C A 5 5 4 4 4.7UF EP PGND GND
1
4
0402
9
7
MBR0520 10V
11
A
DS1
K
LTST-C190GKT
DRN56
DNI TP DNI DNI
Q6
Q5 SMT (0805)
NDS8410 8 8 NDS8410 R24
3 7 7 3
2 6 6 2
1 5 5 1
D
D
0
G S
G S
25V 25V 25V 25V
C28 C29 C30 C31
MAX17330 EV Kit Schematic Diagram
4
4
R3 R4 0.1UF 0.1UF 0.1UF 0.1UF
0402 0402 0402 0402
OPEN OPEN
C8 C10 U6
OPEN OPEN MAX8511EXK33+ L2
N/A
600
VUSB 1 5 VCC33D 1 2 25V VCC33D 25V 25V 25V
R26 IN OUT
2
L3
DNI 0402
600
BATTP F1 DS2 1 2 VUSB
A
SFR-0405A R5 DIS SYSP TP
BATTP 1 3 CSN CSP CHG TP SYSP LTST-C190GKT C24 D8
2
0.01 0.1UF VUSB I2CPU C A 3P3V
K
TP C14 25V
SMT (0805) 0.1UF
25V RB751S40
2
0402
1 S 0402 U2 25V
4
9
12
37
64
20
31
42
56
KRL1220E-M-R010-F C38
2
G 25V
R36 FT2232HL R41 C37 0.1UF R42 R43
SG4 0 R40 0.1UF
SCL1 0402
0402 4.7K 4.7K 0402 5K 5K
10K R7 D SPARK GAP
VPLL
VPHY
2N7002 0402 TP DNI
VCCIO
VCCIO
VCCIO
VCCIO
VCORE
VCORE
VCORE
3
3
14
3
Q2 1K C15 R35 0 0402 MAX14937AWE+
2N7002 50 16 R39 PBC04DAAN
1
0.1UF J1 VREGIN ADBUS0 ADBUS0
D 0402 VDDA VDDB
DNI 0402 10118193-0001LF 0 1 1 2 2
L1 0 0402 ADBUS1 17 ADBUS1 5 I/OA1 I/OB1 12 SDA
3 3 4 4 SDA
G 1 25V 600 49 18 6 11 SCL 5 5 6 6 SCL
1 VCC_USB 1 2 VUSB VREGOUT ADBUS2 0402 I/OA2 I/OB2
VBUS 7 8
S R18 7 8
25V ADBUS3 19
DNI D- 2 SDA1
C20 C21 25V 10V 21 2 10
2
R20 3 ADBUS4 IC IC
4.02K SYSN D+ 4.7UF 0.1UF C22 C23 TP
10K 0402 0402 0.1UF 4.7UF ADBUS5 22 8 IC IC 15
ID 4
R15 10V 0402 0402 23
0402 5 ADBUS6 GNDA GNDA NC NC GNDB GNDB
2K GND
R2 ADBUS7 24
1
7
4
9
USB_DM
13
16
R1 S6 S5 S4 S3 S2 S1
R14 ACBUS0 26 TP
9
8
7
6
10 27 0402 GND
11
10
SYSP
C
100 S2 7 27 U3
0402 U1 DM ACBUS1
C
EVQ-Q2K03W USB_DP R9
MAX17330X22+ 8 DP ACBUS2 28
D10
C5
D7
1000PF 1 3
27 0402 ACBUS3 29
I2CPU
A
J2 0402 R33
RB520G-30
A
R17 B2 C2 2 4 6 30
RB520G-30
PEC03SAAN PFAIL CHG 50V REF ACBUS4
100
RT2+ 1206 C3 12K 0402 ACBUS5 32
3 1 DIS R34
B1 C4 1M R10 VCC33D 14 33
25V CP PCKP TP RESET# ACBUS6
C2
TP
2
ALRT 1K 0402 ACBUS7 34 DGND
2
0.1UF
0402 C1 BATT R8 38
B4 ALRT 1 S BDBUS0
RT2 ALRT/PIO G Q4 39
B3 BDBUS1
10K ZVC/TH2 150 0402 BSS223PW
R12 150
TP BDBUS2 40
C5 SDA SDA D
SDA
0402 BDBUS3 41
B5 SCL SCL
SCL
3
RT+ DNI BDBUS4 43
A1 R13
C
C
C
TH 150 DNI
DNI 25V TP 44
0402 25V BDBUS5
0402
A5 25V
2
2
2
REG C18 D4
10V D3 D2 C17 45
CSP A3 A4CSN C16 BDBUS6
RT1 C6 CSP CSN 5.6V 1000PF 5.6V
1000PF 5.6V 1000PF
R11
46
A
A
A
0.1UF 25V 0402 63 BDBUS7
10K GND 0402 0402 EECS
365
0402 C3
0.47UF 62 EECLK BCBUS0 48
SG1
SG2
SG3
SPARK GAP
SPARK GAP
SPARK GAP
A2
0402
A
61 EEDATA BCBUS1 52
1
1
1
BCBUS2 53
D1
RT-
K
BCBUS3 54
BCBUS4 55
LTST-C190CKT
R37 BCBUS5 57
1M 2 OSCI
C
Y1 0402 BCBUS6 58
12MHZ
D9 BCBUS7 59
5.6V MISC1 1 3 3 OSCO
60
A
2 4 PWREN#
C40 C39
27PF 13 TEST SUSPEND# 36
27PF
AK67421-1-R
0402
0402
BATTN
MOUNTING HOLE 50V
50V
01-AK674211R5P4P-08
AGND
GND
GND
GND
GND
GND
GND
GND
GND
MH4
MH1 MH2 MH3 1
1 1 1
11
1
5
CABLES
10
15
25
35
47
51
MTHOLE
MTHOLE MTHOLE MTHOLE
Evaluates: MAX17330
Maxim Integrated │ 28
MAX17330 Evaluation Kit Evaluates: MAX17330
1.0”
1.0”
1.0”
1.0”
1.0”
1.0”
Revision History
REVISION REVISION PAGES
DESCRIPTION
NUMBER DATE CHANGED
0 4/21 Initial release —
For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. © 2021 Maxim Integrated Products, Inc. │ 35