MODULE 4:

Memory Subsystem

Dr. Gayathri Sivakumar

Assistant Professor(SG-I)
School of Electronics
VIT, Chennai
 Module 4: Memory Subsystem
• Semiconductor memories,
• Memory cells - SRAM and DRAM cells,
• Internal Organization of a memory chip,
• Organization of a memory unit,
• Cache memory unit - Concept of cache memory,
• Mapping methods, Organization of a cache memory unit,
• Fetch and write mechanisms,
• Memory management unit - Concept of virtual memory,
• Address translation.
 Module flow diagram
M4

M1 M2

M3
 Gain knowledge on the
Module 4: organization of semiconductor
Memory memories, different types of
Subsystem memories, Memory hierarchy.
Understand the concept of Cache
memory and Virtual memory.
Ability to understand memory
mapping schemes used in
computer architectures.
Memory hierarchy design
Lower level of memory Consideration
1. Decreasing cost per bit
2. Increasing capacity
3. Increasing access time
4. Decreasing frequency of
access of the memory by the
processor

Higher level of memory Inclusion

means the lower level memory data
is always a subset of the higher level
memory data.

Locality of reference
means CPU perform the operation
on the reusable memory space.
L1: Introduction to Memory
 Introduction

 Memory is one of the most important functional units of a computer.

• Used to store both instructions and data.
• Stores as bits (0’s and 1’s), usually organized in terms of bytes.

 How are the data stored in memory accessed?

• Every memory location has a unique address.
• A memory is said to be byte addressable if every byte of data has a
unique address.
• Some memory systems are word addressable also (every addressed
locations consists of multiple bytes, say, 32 bits or 4 bytes).
 Connection Between Process and Memory

• The processor uses the address

lines to specify the memory
location involved in a data
transfer operation, and uses the
data lines to transfer the data.
• Control lines carry the command
indicating a Read or a Write
operation and whether a byte or a
word is to be transferred.
• The control lines also provide the
necessary timing information and
are used by the memory to
indicate when it has completed
the requested operation.
 An Example Memory Module
• n address lines :The maximum number of
memory locations that can be accessed is 2n. MEMORY (2n
n-Bit Address m-bit Data
Bus
addressable
Bus
• m data lines : The number of bits stored in memory
every addressable location is m. locations)

• The RD/WR’ control line selects the

RD/WR CS’
memory for reading or writing (1: read, 0: ’
write).
The memory size is specified
• The chip select line (CS’) when active (=0) as 2n x m
will enable the chip; otherwise, the data bus
is in the high impedance state.
Semiconductor Memories
 Classification of Memory Systems

A. Volatile versus Non-volatile Memory : –

 A volatile memory system is one where the stored data is lost when the power is switched
off.
• Examples: CMOS static memory, CMOS dynamic memory.
• Dynamic memory in addition requires periodic refreshing.

 A non-volatile memory system is one where the stored data is retained even when the
power is switched off.
• Examples: Read-only memory, Magnetic disk, CDROM/DVD, Flash memory,
Resistive memory.
 Cont..

B. Random-access versus Direct/Sequential access: –

 A memory is said to be random-access when the read/write time is independent of the

memory location being accessed.
• Examples: CMOS memory (RAM and ROM).

 A memory is said to be sequential access when the stored data can only be accessed
sequentially in a particular order.
• Examples: Magnetic tape, Punched paper tape.

 A memory is said to be direct or semi-random access when part of the access is sequential
and part is random.
• Example: Magnetic disk. • We can directly go to a track acer which access will be
sequential.
 Cont..

C. Read-only versus Random-access: –

 Read-only Memory (ROM) is one where data once stored in permanent or semi-
permanent.
• Data written (programmed) during manufacture or in the laboratory.
• Examples: ROM, PROM, EPROM, EEPROM.

 Random Access Memory (RAM) is one where data access time is the same
independent of the location (address).
• Used in main / cache memory systems.
• Example: Static RAM (SRAM) à data once written are retained as long as
power is on.
• Example: Dynamic RAM (DRAM) à requires periodic refresh
 Access Time, Latency and Bandwidth

 Terminologies used to measure speed of the memory system.

a) Memory Access Time: Time between initiation of an operation (Read or Write) and
completion of that operation. Otherwise, it’s the time required to access one operand from the
memory. It is denoted as tavg.

b) Latency: Initial delay from the initiation of an operation to the time the first data is
available.

c) Bandwidth: Maximum speed of data transfer in bytes per second.

 In modern memory organizations, every read request reads a block of words into some
high-speed registers (LATENCY), from where data are supplied to the processor one by
one (ACCESS TIME).
 Design Issue of Memory System

µProc
• The most important issue is to 60%/yr.
1000 (2X/1.5yr)
bridge the processor-memory CPU

gap that has been widening “Moore’s Law”

with every passing year. Processor-Memory
– Advancements in 100 PerformanceGap: (grows

Performance
memory technology are unable 50% / year)
to cope with faster 10 DRAM
advancements in processor DRAM
9%/yr.
technology. (2X/10yr)
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A gap between memory and Processor
 Some important questions?

 How to make the memory system work faster?

 How to increase the data transfer rate between CPU and memory?
 How to address the ever increasing storage needs of applications?

Some possible solutions:

 Cache Memory: to increase the effective speed of the memory system.

 Virtual Memory: to increase the effective size of the memory system