A

MICRO PROJECT REPORT

ON

“Build a 4-bit parity generator and parity checker

circuit.”
Submitted by

Sr. No. Name of Student Roll No.

01 Ajay Gurubasu Shivsharan CM2127
Under the guidance of
V.D.Nalawade

Academic Year
2021-2022

DEPARTMENT OF COMPUTER TECHNOLOGY

Loknete Hon. Hanmantrao Patil Charitable Trust’s
ADARSH INSTITUTE OF TECHNOLOGY (POLYTECHNIC), VITA, DIST-SANGLI

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 Loknete Hon. Hanmantrao Patil Charitable Trust’s
Adarsh Institute of Technology (Polytechnic), Vita

CERTIFICATE
This is to certify that the micro project report entitled

“Build a 4-bit parity generator and parity checker

circuit.”
Sr. No. Name of Student Roll No.
01 Ajay Gurubasu Shivsharan CM2127

For Third Semester of Diploma in Computer Technology of course Digital Techniques (22320) for
academic year 2021-22 as per MSBTE, Mumbai curriculum of ‘I’ scheme.

DIPLOMA OF ENGINEERING
(COMPUTER TECHNOLOGY)

SUBMITTED TO
MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION MUMBAI
ACADEMIC YEAR 2021-22

Project Guide H.O.D. Principal

Mr. V.D.Nalawade Prof.A.A.Vankudre Dr. D.K.Mahadik

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 ACKNOWLEDGEMENT

I express my sincere gratitude to Mr. V.D.Nalawade Department of Computer Technology, for his/her
stimulating guidance, continuous encouragement and supervision throughout the course of present
work.

I would like to place on record my deep sense of gratitude to Prof.A.A.Vankudre HOD-Department of

Computer Technology, for his generous guidance, help and useful suggestions.

I am extremely thankful to Principal Prof.D.K.Mahadik for this motivation and providing me

infrastructural facilities to work in, without which this work would not have been possible.

I would like to express my gratitude to all my colleagues for their support, co-operation and fruitful
discussions on diverse seminar topics and technical help.

Name of Student Sign

1 Ajay Gurubasu Shivsharan
.

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 Index

Sr. No. Content Page No.

1.0 Rationale 5

2.0 Course Outcomes Addressed 5

3.0 Literature Review 5

4.0 Actual Methodology Followed 6

5.0 Actual Resources Used 6

6.0 Outputs of the Micro Project 7

7.0 Skill Developed / learning out of this Micro Project 7

8.0 Applications of this Micro Project 8

9.0 Area of Future Improvement 8

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1.0 Rationale
The parity generator is the method to chek the error present while transmitting data from the
transmitter node to the receiver node. Parity generator is of two types they are odd parity
generator and the even parity generator. The reversible logic gates are used in the generation
of the parity generator and for the parity checker. This is done using the reversible logic gates
since the reversible logic gates are non- information loss gates. This parity generating technique
is the most efficient technique and is one of the most widely used in the error detection
techniques for the data transmission. This generation and the checking of the parity of the bits
are performed by the method of the reversible logic gate makes the data transmission much
easier than the conventional methods. This use of the reversible logic gates reduces the loss of
information, delay and the number of gates used. Reversible logic enables the circuit to
perform the retival of the information easily by using the garbage values in the reversible gates.

2.0 Course Outcomes Addressed

a) To build simple 4-bit parity generator and parity checker circuit.

b) To check functionality 4-bit parity generator and parity checker circuit.

3.0 Literature Review

https://www.electronicshub.org/parity-generator-and-parity-check/

It is combinational circuit that accepts an n-1 bit stream data and generates the additional bit
that is to be transmitted with the bit stream. This additional or extra bit is termed as a parity
bit.In even parity bit scheme, the parity bit is ‘0’ if there are even number of 1s in the data
stream and the parity bit is ‘1’ if there are odd number of 1s in the data stream.In odd parity bit
scheme, the parity bit is ‘1’ if there are even number of 1s in the data stream and the parity bit
is ‘0’ if there are odd number of 1s in the data stream. Let us discuss both even and odd parity
generators.

https://www.scribd.com/doc/27815630/10-Parity-Checker-Circuit

An even parity bit checker will produce an error (“1”) if the number of bits in the entire group
of digits including the parity bit is not an even number.Example: For the following group of
digits 10111 the error output would be a “0”; for 10101, the error output would be a “1”.

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4.0 Actual Methodology Followed
Write step wise procedure of how the work was done, including which team done the work and
how the data was analyzed (If any) ) Even and odd Parity Generators are implemented in this
sub-section according to the proposed LTEx Methodology. As an example of four-bit even parity
generator, the inputs i.e.A3 and A2 are Ex-O Red at the third clock zone to generate the
intermediary output as Bloc diagram. The EXO Red output of A3 and A2is further EX-O Red with
A1 at the second level and the second intermittent output is finally Ex-O Red with A0 to
produce P _even as demonstrated in QCA Layouts of LTEx even Parity Generators generated
using LTEx Methodology: (a) 4-bit. The QCA layout of four bit parity generator consumes0.09
µm2 effective area, employs 78 quantum cells and is indicating the O-Cost as 78 and

P even with QCA clock delay of .Higher orders of even parity generator can alsobe generated
implementing the proposed LTEx methodology. The eight-bit even parity generator of Fig. 6b
QCA Layouts of LTEx even Parity Generators generated using LTEx Methodology:(b) 8-bit
requires (8-1) =7 two-input LTEx module. Similarly, the 16-bit and 32-bit even LTEx parity
generators need (16-1) =15 and (32-1) =31 two input LTEx module respectively as
demonstrated in Fig. 6b-d. In general for the design of n-bit even parity generators, the
requirement is (n-1)cascaded two-input LTEx modules.

5.0 Actual Resources Used

Sr. No. Name of Resource/ Specifications Quantity Remark

Material

1 Voltage Regulator 7805 1 Regulated Power Supply

2 LED Red Colour 1 For indication

3 IC 74266 XNOR gate 1 For check Logical Equality

4 Battery 9V 1 To Power Supply Purpose

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6.0 Outputs of the Micro Project
Circuit Diagram

7.0 Skill Developed / learning out of this Micro Project

Working

The parity generating technique is one of the most widely used error detection techniques for
the data transmission. In digital systems, when binary data is transmitted and processed , data
may be subjected to noise so that such noise can alter 0s (of data bits) to 1s and 1s to 0s Hence,
parity bit is added to the word containing data in order to make number of 1s either even or
odd.Thus it is used to detect errors , during the transmission of binary data .The message
containing the data bits along with parity bit is transmitted from transmitter node to receiver
node.

Advantages

• The advantage is that errors on a noisy line can be caught quickly and only the errant
word has to be re-transmitted.

• However, because a parity check cannot detect all errors, you have to use a higher-level
error detection mechanism, like CRC.
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8.0 Applications of this Micro Project
• One important application of the use of an Exclusive-OR gate is to generate parity.

• Parity is used to detect errors in transmitted data caused by noise or other disturbances.

• A parity bit is an extra bit that is added to a data word and can be either odd or even
parity.

• In an even parity system, the sum of all the bits (including the parity bit) is an even
number

• In an odd parity system the sum of all the bits must be an odd number.

• The circuit that creates the parity bit at the transmitter is called the parity generator.

• The circuit that determines if the received data is correct is the parity checker.

• Parity is good for detecting a single bit error only

9.0 Area of Future Improvement

Conclusion

In this application note, we implemented two variants of a binary parity generator and Checker
to be used as an error detection technique for data transmission. A parity bit is added to the
transmitted data to make the number of 1s either even or odd. This bit is used to detect errors
during the transmission of binary data. Several commercial IC’s can be replaced with Dialog
Green PAKs so that the application size and cost can be reduced. The two variants show how
the data input method can be either parallel or serial.