PART A – Micro Project Proposal

Title of Micro Project: build a 4-bit parity generator & parity checker circuit.

1.0 Brief Introduction: A parity bit is used for the purpose of detecting errors during the
transmission of binary information . The circuit that generates that parity bit in the
transmitter is called parity generator. The circuit that checks the parity in the receiver is
called a parity checker

2.0 Aim of the Micro Project

This Micro Project aims at:

1. To design and realize the Parity checker circuit.

2. To design and verify the truth table of a three bit odd parity generator and checker.

3.0 Intended Course Outcomes

a) To build simple 4-bit parity generator and parity checker circuit.

b) To check functionality 4-bit parity generator and parity checker circuit.

4.0 Literature Review

“A Review on Reversible Logic Gates and their Implementation”, International Journal of

Emerging Technology and Advanced Engineering in this paper the Reversible logic is one
of the most vital issue at present time and it has different areas for its application, those
are low power CMOS, quantum computing, nanotechnology, cryptography, optical
computing, DNA computing, digital signal processing (DSP), quantum dot cellular
automata, communication, computer graphics. It is not possible to realize quantum
computing without implementation of High Speed Time Efficient Reversible ALU Based
Logic Gate Structure on Vertex Family 73 reversible logic.

The main purposes of designing reversible logic are to decrease quantum cost, depth of
the circuits and the number of garbage outputs. This paper provides the basic reversible
logic gates, which in designing of more complex system having reversible circuits as a
primitive component and which can execute more complicated operations using
quantum computers. The reversible circuits form the basic building block of quantum
computers as all quantum operations are reversible. This paper presents the data
relating to the primitive reversible gates which are available in literature and helps
researches in designing higher complex computing circuits using reversible gates.

5.0 Proposed Methodology

Even and odd Parity Generators are implemented in this sub-section according to the
proposed LTEx Methodology. As an example of four-bit even parity generator, the inputs
i.e.A3 and A2 are Ex-O Red at the third clock zone to generate the intermediary output
as Bloc diagram. The EXO Red output of A3 and A2is further EX-O Red with A1 at the
second level and the second intermittent output is finally Ex-O Red with A0 to produce
P_even as demonstrated in QCA Layouts of LTEx even Parity Generators generated using
LTEx Methodology: (a) 4-bit. The QCA layout of four bit parity generator consumes0.09
µm2 effective area, employs 78 quantum cells and is indicating the O-Cost as 78 and
generates P_even with QCA clock delay of .Higher orders of even parity generator can
also be generated implementing the proposed LTEx methodology. The eight-bit even
parity generator of Fig. 6b QCA Layouts of LTEx even Parity Generators generated using
LTEx Methodology:(b) 8-bit requires (8-1) =7 two-input LTEx module .Similarly, the 16-
bit and 32-bit even LTEx parity generators need (16-1) =15 and (32-1) =31 two input LTEx
module respectively as demonstrated in Fig. 6b-d. In general for the design of n-bit even
parity generators, the requirement is (n-1)cascaded two-input LTEx modules.

6.0 Resources Required

Sr.
Name of Resource/ Material Specifications Quantity Remark
No.
Regulated Power
1 Voltage Regulator 7805 1
supply
2 LED Red colour 1 For Indication
To Check Logical
3 IC 74266 XNOR Gate 1
Equality
To Power Supply
4 Battery 9V 1
Purpose

7.0 Action Plan

Name of
Sr. Planned Planned
Details of activity Responsible Team
No. start date Finish date
Members
1 Project Proposal 29/9/2021 31/9/2021 Aarti Aandrao
Pawalkar
Aarti Aandrao
2 Data Collection & Analysis 7/10/2021 10/10/2021 Pawalkar
Preparation of Prototype/ Aarti Aandrao
3 19/10/2021 26/10/2021 Pawalkar
Model
4 Preparation of Report 1/11/2021 5/11/2021
Aarti Aandrao
Pawalkar
Aarti Aandrao
5 Presentation & Submission 17/11/2021 17/11/2021 Pawalkar