High Performance,

Narrow-Band Transceiver IC
Data Sheet ADF7021-V
FEATURES On-chip fractional-N PLL
High performance, low power, narrow-band transceiver On-chip, 7-bit ADC and temperature sensor
Enhanced performance ADF7021-N with external VCO Fully automatic frequency control (AFC) loop
Frequency bands using external VCO: 80 MHz to 960 MHz Digital received signal strength indication (RSSI)
Improved adjacent channel power (ACP) and adjacent Integrated Tx/Rx switch
channel rejection (ACR) compared with the ADF7021-N Leakage current in power-down mode: 0.1 μA
Programmable IF filter bandwidths: 9 kHz, 13.5 kHz, APPLICATIONS
and 18.5 kHz
Narrow-band, short-range device (SRD) standards
Modulation schemes: 2FSK, 3FSK, 4FSK, MSK
ETSI EN 300 220
Spectral shaping: Gaussian and raised cosine filtering
500 mW output power capability in 869 MHz g3 subband
Data rates: 0.05 kbps to 24 kbps
with external PA
Power supply: 2.3 V to 3.6 V
High performance receiver rejection, blocking, and
Programmable output power: −16 dBm to +13 dBm
adjacent channel power (ACP)
in 63 steps
FCC Part 90 (meets Emission Mask D requirements)
Automatic power amplifier (PA) ramp control
FCC Part 95
Receiver sensitivity
ARIB STD-T67
−125 dBm at 250 bps, 2FSK
Wireless metering
−122 dBm at 1 kbps, 2FSK
Narrow-band wireless telemetry
Patent pending, on-chip image rejection calibration

FUNCTIONAL BLOCK DIAGRAM

RSET CE CREG[1:4] MUXOUT

TEMP
MUX 7-BIT ADC
RLNA SENSOR
LDO[1:4] TEST MUX

2FSK
LNA 3FSK CLOCK TxRxCLK
RFIN RSSI/ 4FSK AND DATA Tx/Rx TxRxDATA
IF FILTER LOG AMP RECOVERY CONTROL
RFIN DEMODULATOR
SWD

GAIN

AGC
CONTROL SLE

SERIAL SDATA
ADF7021-V AFC
PORT SREAD
CONTROL SCLK
PA RAMP

2FSK GAUSSIAN/
Σ-∆ 3FSK
RFOUT ÷1/÷2 DIV P N/N + 1 RAISED COSINE
MODULATOR 4FSK FILTER
MOD CONTROL
÷2

3FSK
BUFFER ENCODING
CP PFD
CLK
DIV R OSC
DIV
08635-001

L2 CPOUT OSC1 OSC2 CLKOUT

Figure 1.

Rev. B Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
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Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
ADF7021-V* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017

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Application Notes Systems that Promote Energy Efficiency
• AN-0987: Designing a Wireless Transceiver System to • Smart Metering Technology Promotes Energy Efficiency
Meet the Wireless M-Bus Standard for a Greener World
• AN-1182: Understanding and Optimizing the AFC Loop on • The Use of Short Range Wireless in a Multi-Metering
the ADF7021 for Minimum Preamble System
• AN-1258: Image Rejection Calibration on the ADF7021, • Understand Wireless Short-Range Devices for Global
ADF7021-N, and ADF7021-V License-Free Systems
• AN-1285: ADF7021-N Radio Performance for Wireless • Wireless Short Range Devices and Narrowband
Meter-Bus (WM-Bus), Mode N Communications
• AN-1389: Recommended Rework Procedure for the Lead • Wireless Technologies for Smart Meters: Focus on Water
Frame Chip Scale Package (LFCSP) Metering
• AN-771: ADSP-BF533 EZ-KIT Lite and ADF70xx Interface
DESIGN RESOURCES
• AN-772: A Design and Manufacturing Guide for the Lead
Frame Chip Scale Package (LFCSP) • ADF7021-V Material Declaration
• AN-852: Using the Test DAC on the ADF702x to • PCN-PDN Information
Implement Functions Such as Analog FM DEMOD, SNR • Quality And Reliability
Measurement, FEC Decoding, and PSK/4FSK
• Symbols and Footprints
Demodulation
• AN-859: RF Port Impedance Data, Matching, and External
Component Selection for the ADF7020-1, ADF7021, and
DISCUSSIONS
ADF7021-N View all ADF7021-V EngineerZone Discussions.
• AN-915: CDR Operation for ADF7020, ADF7020-1,
ADF7021, and ADF7025 SAMPLE AND BUY
Data Sheet Visit the product page to see pricing options.
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Data Sheet ADF7021-V
REVISION HISTORY
9/14—Rev. A to Rev. B 8/12—Rev. 0 to Rev. A
Changes to Table 8 ..........................................................................16 Changes to Figure 6 ........................................................................ 15
Change to RSSI Formula (Converting to dBm) Section ............30 Updated Outline Dimensions........................................................ 60
Change to Postdemodulator Filter Setup Section .......................33 Changes to Ordering Guide ........................................................... 60
Change to When to Use Fine Calibration Section ......................38
Change to Battery Voltage/ADCIN/Temperature Sensor 4/10—Revision 0: Initial Version
Readback Section ............................................................................44
Change to Register 4—Demodulator Setup Register Section .......50
Change to Register 7—Readback Setup Register Section..............53
Change to Register 4—AFC Register Section ................................56

Rev. B | Page 3 of 66





 37 MUXOUT
42 CPOUT
41 CREG3
48 CVCO
47 GND1

39 OSC1
38 OSC2
40 VDD3
45 GND

43 VDD
46 L1

44 L2
VCOIN 1 36 CLKOUT
CREG1 2 35 TxRxCLK
VDD1 3 34 TxRxDATA
RFOUT 4 33 SWD
RFGND 5 32 VDD2
RFIN6
ADF7021-V 31 CREG2
RFIN7 TOP VIEW 30 ADCIN
(Not to Scale)
RLNA 8 29 GND2
VDD4 9 28 SCLK
RSET 10 27 SREAD
CREG4 11 26 SDATA
GND4 12 25 SLE
13
14
15
16
17
18
19
20
21
22
23
24
FILT_Q
FILT_Q
FILT_I
FILT_I
MIX_I
MIX_I
MIX_Q
MIX_Q

GND4

GND4

CE
TEST_A
NOTES

08635-011
1. THE EXPOSED PADDLE MUST BE CONNECTED
TO THE GROUND PLANE.
 –80 16
RF FREQ = 460MHz PA_BIAS = 11µA
12
–90 TCXO = 19.2MHz
8 PA_BIAS = 9µA
4
–100

RF OUTPUT POWER (dBm)

PHASE NOISE (dBc/Hz)

–110 –4 PA_BIAS = 5µA

PA_BIAS = 7µA
–8
ICP = 0.3mA
–120 –12
ICP = 0.9mA
–16
–130 –20
–24
–140
–28

–150 –32
–36
–160 –40

08635-077

08635-012
1 10 100 1k 10k 100k 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60
FREQUENCY OFFSET (kHz) PA SETTING

–60 20
RF FREQ = 868MHz
–70 TCXO = 19.2MHz
0
–80
OUTPUT POWER (dBm)
PHASE NOISE (dBc/Hz)

–90
–20
ICP = 0.3mA
–100
ICP = 0.9mA
–110 ICP = 1.5mA –40
ICP = 2.1mA
–120
–60
–130

–140
–80
–150

–160 –100
08635-078

08635-013
1 10 100 1k 10k 300 800 1300 1800 2300 2800
FREQUENCY OFFSET (kHz) FREQUENCY (MHz)

20 10
DEMODULATION = GFSK FCC PART 90 DATA RATE = 9.6kbps
EMISSION MASK D DATA = PRBS9
10 DATA RATE = 2.4kbps 0
fDEV = 1.2kHz fDEV = 2.4kHz
0 RF FREQ = 470MHz RF FREQ = 868MHz
IFBW = 4kHz –10
OUTPUT POWER (dBm)

OUTPUT POWER (dBm)

–10
–20 2FSK
–20
–30
–30
GFSK
–40
–40
–50
–50

–60 –60

–70 –70

–80 –80
08635-014
0

10,000

15,000

20,000

25,000
5000
–5000
–25,000

–20,000

–15,000

–10,000

867.97 867.98 867.99 868.00 868.01 868.02 868.03

FREQUENCY (MHz)
08635-079

FREQUENCY OFFSET FROM CARRIER (Hz)

 10
DATA RATE = 9.6kbps RAMP RATE: TRACE = MAX HOLD
10 CW ONLY PA ON/OFF RATE = 3Hz
0 DATA = PRBS9
256 CODES/BIT PA ON/OFF CYCLES = 10,000
fDEV = 2.4kHz 128 CODES/BIT VDD = 3.0V
RF FREQ = 868MHz 0 64 CODES/BIT
–10 32 CODES/BIT

OUTPUT POWER (dBm)

OUTPUT POWER (dBm)

–20 –10

–30 –20
2FSK
–40
–30
–50
–40
RC2FSK
–60

–50
–70

–80 –60

08635-015

08635-018
867.97 867.98 867.99 868.00 868.01 868.02 868.03 –100 –50 0 50 100
FREQUENCY (MHz) FREQUENCY OFFSET (kHz)

10
DATA RATE = 9.6kbps
0 DATA = PRBS9
fDEV = 2.4kHz
RF FREQ = 868MHz
–10
OUTPUT POWER (dBm)

–20

–30
3FSK
–40

–50

–60 RC3FSK

–70

–80
08635-016

867.97 867.98 867.99 868.00 868.01 868.02 868.03

FREQUENCY (MHz)

10
DATA RATE = 9.6kbps
0 DATA = PRBS9
fDEV = 2.4kHz
–10 RF FREQ = 868MHz
OUTPUT POWER (dBm)

–20

–30
4FSK
–40

–50

–60 RC4FSK

–70

–80

–90
08635-017

867.94 867.96 867.98 868.00 868.02 868.04 868.06

FREQUENCY (MHz)
 0.6 –20
DATA RATE = 1.2kbps
fDEV = 2.4Hz RSSI
RF FREQ = 868MHz READBACK LEVEL
0.5 –40
IFBW = 9kHz
–40°C, 2.3V
–40°C, 3V –60

RSSI LEVEL (dBm)

0.4
BIT ERROR RATE

–40°C, 3.6V
+25°C, 2.3V
+25°C, 3V
0.3 +25°C, 3.6V –80
+85°C, 2.3V
+85°C, 3V
0.2 +85°C, 3.6V –100
ACTUAL RF INPUT LEVEL

0.1 –120

–140

08635-023
0

08635-021
–130 –125 –120 –115 –110 –105 –122.5 –112.5 –102.5 –92.5 –82.5 –72.5 –62.5 –52.5 –42.5
RF INPUT POWER (dBm) RF INPUT POWER (dBm)

0.6 80
DATA RATE = 1.2kbps
fDEV = 2.4Hz 70
0.5 RF FREQ = 460MHz
IFBW = 9kHz 60

0.4 50
BIT ERROR RATE

BLOCKING (dB)

–40°C, 2.3V 40
0.3 –40°C, 3V
–40°C, 3.6V
30
+25°C, 2.3V
+25°C, 3V
0.2 +25°C, 3.6V 20
+85°C, 2.3V CALIBRATED
+85°C, 3V 10 UNCALIBRATED
0.1 +85°C, 3.6V
0

0 –10
08635-022

–130 –125 –120 –115 –110 –105

459.70

459.85

459.95

460.00

460.05

460.10

460.15
459.75

459.80

459.90

RF INPUT POWER (dBm)

08635-080
BLOCKER FREQUENCY (MHz)

100 2.5
0
90 +90°C
–2.5
80 –5.0
–7.5
70
–10.0
ATTENUATION (dB)

–12.5
BLOCKING (dB)

60
–15.0
50
–17.5
–40°C
40 –20.0
–22.5
30
–25.0
20 –27.5
10 –30.0
–32.5
0 –35.0
–10 –37.5
08635-024

08635-025

–20 –15 –10 –5 0 5 10 15 20 90 92 94 96 98 100 102 104 106 108 110

FREQUENCY OFFSET (MHz) IF FREQUENCY (kHz)
 –100 –70
RF FREQ = 860MHz 2FSK MODULATION
–102 2FSK MODULATION DATA RATE = 9.6kbps
DATA RATE = 9.6kbps fDEV = 4kHz
–80 HIGH MIXER
IFBW = 12.5kHz
IFBW = 25kHz LINEARITY
–104 VDD = 3.0V DEMOD = CORRELATOR
SENSITIVITY @ BER = 10–3
SENSITIVITY POINT (dBm)

TEMPERATURE = 25°C IP3 = –5dBm

–106 –90

SENSITIVITY (dBm)
–108
–100 IP3 = –9dBm
–110 DISCRIMINATOR BANDWIDTH = IP3 = –3dBm
2× FSK FREQUENCY DEVIATION
–112 IP3 = –20dBm
–110
DEFAULT IP3 = –13.5dBm
–114 MIXER
–120 LINEARITY IP3 = –24dBm
–116
DISCRIMINATOR BANDWIDTH =
1× FSK FREQUENCY DEVIATION
–118 –130

08635-026
0 0.2 0.4 0.6 0.8 1.0 1.2 3, 72 10, 72 30, 72

08635-028
(LOW GAIN MODE) (MEDIUM GAIN MODE) (HIGH GAIN MODE)
MODULATION INDEX
LNA GAIN, FILTER GAIN

–1

THRESHOLD DETECTION
–2

VITERBI DETECTION
–3
LOG BER

–4

–5
3FSK MODULATION
VDD = 3.0V, TEMP = 25°C
DATA RATE = 9.6kbps
–6 fDEV = 2.4kHz
RF FREQ = 868MHz
IFBW = 18.75kHz
–7
08635-027

–120 –118 –116 –114 –112 –110 –108 –106 –104 –102 –100
INPUT POWER (dBm)
 VDD

CLKOUT
ENABLE BIT

OSC1 DIVIDER ÷2 CLKOUT

1 TO 15

08635-031
OSC1 OSC2
08635-030

CP2 CP1


CHARGE VCO
PUMP OUT
08635-032


  
    
 

VDD
 
    
  REGULATOR_READY (DEFAULT)

FILTER_CAL_COMPLETE
DIGITAL_LOCK_DETECT
RSSI_READY
MUX CONTROL MUXOUT
Tx_Rx

LOGIC_ZERO
TRISTATE

 LOGIC_ONE
  

08635-034
GND

REFERENCE IN

÷R PFD/
CHARGE VCO
PUMP

÷N

THIRD-ORDER
Σ-Δ MODULATOR
08635-033

FRACTIONAL_N INTEGER_N
Data Sheet ADF7021-V

TRANSMITTER
1 2 3 4 ... 8 ... 16
RF OUTPUT STAGE
DATA BITS
The power amplifier (PA) of the ADF7021-V is based on a
single-ended, controlled current, open-drain amplifier that has PA RAMP 0
(NO RAMP)
been designed to deliver up to 13 dBm into a 50 Ω load at a
PA RAMP 1
maximum frequency of 960 MHz. (256 CODES PER BIT)
PA RAMP 2
The PA output current and, consequently, the output power (128 CODES PER BIT)
are programmable over a wide range. The PA configuration is PA RAMP 3
(64 CODES PER BIT)
shown in Figure 38. The output power is set using Register 2,
PA RAMP 4
Bits[DB18:DB13]. (32 CODES PER BIT)
REGISTER 2, PA RAMP 5
BITS[DB12:DB11] (16 CODES PER BIT)
2 PA RAMP 6
(8 CODES PER BIT)

08635-038
6 REGISTER 2, PA RAMP 7
IDAC
BITS[DB18:DB13] (4 CODES PER BIT)

Figure 39. PA Ramping Settings

RFOUT
REGISTER 2, BIT DB7
PA Bias Currents
+
REGISTER 0, BIT DB27 The PA_BIAS bits (Register 2, Bits[DB12:DB11]) facilitate an
RFGND
adjustment of the PA bias current to further extend the output
08635-037

power control range, if necessary. If this feature is not required,

FROM VCO
the default value of 9 μA is recommended. If output power
Figure 38. PA Configuration greater than 10 dBm is required, a PA bias setting of 11 μA is
The PA is equipped with overvoltage protection, which makes it recommended. The output stage is powered down by resetting
robust in severe mismatch conditions. Depending on the applica- Register 2, Bit DB7 to 0.
tion, users can design a matching network for the PA to exhibit MODULATION SCHEMES
optimum efficiency at the desired radiated output power level for
a wide range of antennas, such as loop or monopole antennas. The ADF7021-V supports 2FSK, 3FSK, and 4FSK modulation.
See the LNA/PA Matching section for more information. The implementation of these modulation schemes is shown in
Figure 40.
PA Ramping TO
LOOP FILTER PA STAGE
PFD/
When the PA is switched on or off quickly, its changing input REF
CHARGE VCO ÷2
impedance momentarily disturbs the VCO output frequency. PUMP

This process is called VCO pulling, and it manifests as spectral

splatter or spurs in the output spectrum around the desired ÷N
carrier frequency. Some radio emissions regulations place
FRACTIONAL_N
limits on these PA transient-induced spurs (for example, the THIRD-ORDER
Σ-∆ MODULATOR
ETSI EN 300 220 regulations). By gradually ramping the PA
on and off, PA transient spurs are minimized. Tx_FREQUENCY_ INTEGER_N
DEVIATION
The ADF7021-V has built-in PA ramping configurability. As 2FSK
Figure 39 illustrates, there are eight ramp rate settings, defined TxRxDATA
GAUSSIAN
as a certain number of PA setting codes per one data bit period. OR 3FSK 1 – D2 PR PRE-
MUX SHAPING CODER
RAISED COSINE
The PA steps through each of its 64 code levels but at different FILTERING
speeds for each setting. The ramp rate is set by configuring 4FSK
4FSK
08635-039

Bits[DB10:DB8] in Register 2. BIT SYMBOL

MAPPER
If the PA is enabled/disabled by the PA_ENABLE bit (Register 2, Figure 40. Transmit Modulation Implementation
Bit DB7), it ramps up and down. If it is enabled/disabled by the
Tx/Rx bit (Register 0, Bit DB27), it ramps up and turns hard off.

Rev. B | Page 25 of 61

 

0
–1 +1

08635-040
fC – fDEV fC fC + fDEV
RF FREQUENCY





 

Tx DATA
0, 1 PRECODER 0, 1 CONVOLUTIONAL
1/P(D) ENCODER
P(D)

0, +1, –1

fC
FSK MOD fC + fDEV
CONTROL fC – fDEV
TO
08635-041

AND N DIVIDER
DATA FILTERING
 Tx DATA 0 0 0 1 1 0 1 1

f
+3fDEV

+fDEV
SYMBOL
FREQUENCIES
–fDEV

–3fDEV
08635-042

t
 OFFSET
CORRECTION

FSK
1 A A A LATCH DEMOD

IFWR IFWR IFWR IFWR CLK

RSSI
ADC

08635-044
R

 LIMITERS
I

DEMOD FILTER
CORRELATOR
Q DEMODULATOR

POST
MUX

LINEAR
DEMODULATOR

THRESHOLD
DETECTION
TxRxDATA 2FSK/3FSK/4FSK
CLOCK
AND
DATA MUX
TxRxCLK
RECOVERY
VITERBI
08635-045

DETECTION
3FSK
  

  



  
  
 
 

  
  
  
 

  
  
  
 

  
 
  
 
   
  
  
 

  
 
  
 
 


 100 3 
K  Round  
 2  f DEV    
  
 
 
 


 ADF7021-V
RFIN
LNA
RFIN

GAIN ADJUST
POLYPHASE
IF FILTER
RSSI/
MUX LOG AMP

INTERNAL
SIGNAL
SOURCE

7-BIT
ADC

PHASE ADJUST

I Q

FROM LO
SERIAL
INTERFACE
4

PHASE ADJUST
REGISTER 5 RSSI READBACK
4
GAIN ADJUST
REGISTER 5

MICROCONTROLLER
I/Q GAIN/PHASE ADJUST AND

08635-050
RSSI MEASUREMENT
ALGORITHM

SYNC ID

08635-052
PREAMBLE WORD FIELD DATA FIELD CRC

60
CAL AT +25°C

50
IMAGE REJECTION (dB)

40 CAL AT +85°C
CAL AT –40°C

30
VDD = 3.0V
IFBW = 25kHz
20
WANTED SIGNAL: INTERFERER SIGNAL:
RF FREQ = 430MHz RF FREQ = 429.8MHz
MODULATION = 2FSK MODULATION = 2FSK
10 DATA RATE = 9.6kbps, DATA RATE = 9.6kbps,
DATA = PRBS9 DATA = PRBS11
fDEV = 4kHz fDEV = 4kHz
LEVEL= –100dBm
0
08635-051

–60 –40 –20 0 20 40 60 80 100

TEMPERATURE (°C)
 READBACK MODE READBACK VALUE

DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

AFC READBACK RV16 RV15 RV14 RV13 RV12 RV11 RV10 RV9 RV8 RV7 RV6 RV5 RV4 RV3 RV2 RV1

RSSI READBACK X X X X X LG2 LG1 FG2 FG1 RV7 RV6 RV5 RV4 RV3 RV2 RV1

BATTERY VOLTAGE/ADCIN/
TEMP. SENSOR READBACK X X X X X X X X X RV7 RV6 RV5 RV4 RV3 RV2 RV1

SILICON REVISION RV16 RV15 RV14 RV13 RV12 RV11 RV10 RV9 RV8 RV7 RV6 RV5 RV4 RV3 RV2 RV1
08635-056

FILTER CAL READBACK 0 0 0 0 0 0 0 0 RV8 RV7 RV6 RV5 RV4 RV3 RV2 RV1
 MICROCONTROLLER ADF7021-V
TxDATA TxRxCLK
UART
RxDATA TxRxDATA

CE
SWD
SREAD
GPIO
SLE

08635-058
SDATA
SCLK

ADuC84x ADF7021-V
MISO TxRxDATA
MOSI
SCLOCK TxRxCLK
SS
P3.7 CE
MICROCONTROLLER ADF7021-V
P3.2/INT0 SWD
P2.4 SREAD MISO TxRxCLK
P2.5 SLE SPI MOSI TxRxDATA
GPIO
08635-057

P2.6 SDATA SCLK CLKOUT

P2.7 SCLK
CE
SWD
SREAD
GPIO
SLE
SDATA
08635-059

SCLK

ADSP-BF533 ADF7021-V
SCK SCLK
MOSI SDATA
MISO SREAD
PF5 SLE
RSCLK1 TxRxCLK
DT1PRI TxRxDATA
DR1PRI
RFS1 SWD
08635-060

PF6 CE
 DB28 UART_MODE

Tx/Rx
ADDRESS
MUXOUT INTEGER_N FRACTIONAL_N BITS
DB31

DB30

DB29

DB27

DB26

DB25

DB24

DB23

DB22

DB21

DB20

DB19

DB18

DB17

DB16

DB15

DB14

DB13

DB12

DB11

DB10

DB9

DB5

DB4

DB1

DB0
DB8

DB7

DB6

DB3

DB2
C4 (0)

C3 (0)

C2 (0)

C1 (0)
M15

M11

M10
M14

M13

M12
TR1
M3

M6

M2

M1
M2

M1

M9

M8

M7

M5

M4

M3
N5

N4
U1

N8

N7

N6

N3

N2

N1
FRACTIONAL_N
TR1 Tx/Rx M15 M14 M13 ... M3 M2 M1 DIVIDE RATIO
0 TRANSMIT 0 0 0 ... 0 0 0 0
1 RECEIVE 0 0 0 ... 0 0 1 1
0 0 0 ... 0 1 0 2
U1 UART_MODE
. . . ... . . . .
0 DISABLED . . . ... . . . .
1 ENABLED . . . ... . . . .
M3 M2 M1 MUXOUT 1 1 1 ... 1 0 0 32,764
1 1 1 ... 1 0 1 32,765
0 0 0 REGULATOR_READY (DEFAULT) 1 1 1 ... 1 1 0 32,766
0 0 1 FILTER_CAL_COMPLETE 1 1 1 ... 1 1 1 32,767
0 1 0 DIGITAL_LOCK_DETECT
0 1 1 RSSI_READY
1 0 0 Tx_Rx
1 0 1 LOGIC_ZERO
1 1 0 TRISTATE
1 1 1 LOGIC_ONE

INTEGER_N
N8 N7 N6 N5 N4 N3 N2 N1 DIVIDE RATIO
0 0 0 1 0 1 1 1 23
0 0 0 1 1 0 0 0 24
. . . . . . . . .
. . . . . . . . .
. . . . . . . . .
1 1 1 1 1 1 0 1 253

1 1 1 1 1 1 1 0 254

08635-061
1 1 1 1 1 1 1 1 255

 

 
   
 

 
    
 


 IMPEDANCE
RF_DIVIDE_

CURRENT

DOUBLER
BUFFER_

ENABLE
XOSC_

XTAL_
CP_
BY_2
RESERVED XTAL_ CLKOUT_ ADDRESS
R_COUNTER
BIAS DIVIDE BITS

DB24

DB23

DB22

DB21

DB20

DB19

RFD1 DB18

DB17

DB16

DB15

DB14

DB13

DB12

DB10
DB11
DB25

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0
C4 (0)

C3 (0)

C2 (0)

C1 (1)
RE7

RE6

RE5

RE4

RE3

RE2

RE1

CP2

CP1

XB2

XB1
VE1

CL4

CL3

CL2

CL1
D1

R3

R2

R1
X1
RF R_COUNTER
R3 R2 R1 DIVIDE RATIO
RFD1 RF_DIVIDE_BY_2 0 0 1 1
0 OFF 0 1 0 2
1 ON . . . .
. . . .
. . . .
1 1 1 7

CLKOUT_
CL4 CL3 CL2 CL1 DIVIDE RATIO
0 0 0 0 OFF
0 0 0 1 2
0 0 1 0 4
. . . . .
BUFFER_ . . . . .
VE1 IMPEDANCE
. . . . .
0 50Ω 1 1 1 1 30
1 HIGH IMPEDANCE
XTAL_
D1 DOUBLER
0 DISABLED
1 ENABLED

RSET = 3.6kΩ X1 XOSC_ENABLE

CP2 CP1 ICP (mA)
0 OFF
0 0 0.3 1 ON
0 1 0.9
1 0 1.5 XB2 XB1 XTAL_BIAS
1 1 2.1 0 0 20µA
0 1 25µA
1 0 30µA

08635-062
1 1 35µA

 



 R-COSINE_

ENABLE
TxDATA_ MODULATION_ ADDRESS
ALPHA

PA_
INVERT Tx_FREQUENCY_DEVIATION POWER_AMPLIFIER PA_BIAS PA_RAMP SCHEME BITS
NRC1 DB30

DB29

DB28

TFD9 DB27

TFD8 DB26

TFD7 DB25

TFD6 DB24

TFD5 DB23

TFD4 DB22

TFD3 DB21

TFD2 DB20

TFD1 DB19

DB18

DB17

DB16

DB15

DB14

DB13

DB12

DB10
DB11

DB6

DB0
DB9

DB8

DB7

DB5

DB4

DB3

DB2

DB1
C4 (0)

C3 (0)

C2 (1)

C1 (0)
PR3

PR2

PR1

PE1
PA2

PA1
DI2

DI1

P5

P4

S3
P6

P3

P2

P1

S2

S1
PA2 PA1 PA_BIAS PE1 PA_ENABLE
0 0 5µA 0 OFF
0 1 7µA 1 ON
1 0 9µA
1 1 11µA

DI2 DI1 TxDATA_INVERT

0 0 NORMAL PR3 PR2 PR1 PA_RAMP RATE
0 1 INVERT CLK 0 0 0 NO RAMP
1 0 INVERT DATA 0 0 1 256 CODES/BIT
1 1 INV CLK AND DATA 0 1 0 128 CODES/BIT
0 1 1 64 CODES/BIT
1 0 0 32 CODES/BIT
1 0 1 16 CODES/BIT
TFD9 ... TFD3 TFD2 TFD1 fDEV 1 1 0 8 CODES/BIT
1 1 1 4 CODES/BIT
0 ... 0 0 0 0
0 ... 0 0 1 1
0 ... 0 1 0 2 S3 S2 S1 MODULATION_SCHEME
0 ... 0 1 1 3 0 0 0 2FSK
. ... . . . . 0 0 1 GAUSSIAN 2FSK
1 ... 1 1 1 511 0 1 0 3FSK
0 1 1 4FSK
1 0 0 OVERSAMPLED 2FSK
1 0 1 RAISED COSINE 2FSK
1 1 0 RAISED COSINE 3FSK
1 1 1 RAISED COSINE 4FSK
NRC1 R-COSINE_ALPHA POWER_
P6 P5 ... P2 P1 AMPLIFIER
0 0.5 (DEFAULT)
0 0 ... 0 0 0 (PA OFF)
1 0.7
0 0 ... 0 1 1 (–16.0dBm)
0 0 ... 1 0 2
0 0 ... 1 1 3
. . ... . . .

08635-063
. . ... . . .
1 1 ... 1 1 63 (+13dBm)

 








 BBOS_CLK_
DIVIDE
DEMOD_CLK_ ADDRESS
AGC_CLK_DIVIDE SEQ_CLK_DIVIDE CDR_CLK_DIVIDE DIVIDE BITS
DB31

DB30

DB29

DB28

DB27

DB26

DB25

DB24

DB23

DB22

DB21

DB20

DB19

DB18

DB17

DB16

DB15

DB14

DB13

DB12

DB10
DB11

DB7

DB6

DB5

DB2

DB1
DB9

DB8

DB4

DB3

DB0
C4 (0)

C3 (0)

C2 (1)

C1 (1)
GD6

GD5

GD4

GD3

GD2

GD1

OK4

OK3

OK2

OK1

BK2

BK1
SK6

SK2

SK1
SK8

SK7

SK5

SK4

SK3

FS5

FS4
FS8

FS7

FS6

FS3

FS2

FS1
SK8 SK7 ... SK3 SK2 SK1 SEQ_CLK_DIVIDE BK2 BK1 BBOS_CLK_DIVIDE
0 0 ... 0 0 1 1 0 0 4
0 0 ... 0 1 0 2 0 1 8
. . ... . . . . 1 0 16
1 1 ... 1 1 0 254 1 1 32
1 1 ... 1 1 1 255
OK4 OK3 OK2 OK1 DEMOD_CLK_DIVIDE
GD6 GD5 GD4 GD3 GD2 GD1 AGC_CLK_DIVIDE 0 0 0 0 INVALID
0 0 0 0 0 0 INVALID 0 0 0 1 1
0 0 0 0 0 1 1 ... ... ... ... ...
... ... ... ... ... ... ... 1 1 1 1 15
1 1 1 1 1 1 63
FS8 FS7 ... FS3 FS2 FS1 CDR_CLK_ DIVIDE
0 0 ... 0 0 1 1
0 0 ... 0 1 0 2
. . ... . . . .

08635-064
1 1 ... 1 1 0 254
1 1 ... 1 1 1 255





 DOT_PRODUCT
IF_FILTER_BW

Rx_ DEMOD_ ADDRESS

POST_DEMOD_BW DISCRIMINATOR_BW INVERT SCHEME BITS
DB31

DB30

DW10 DB29

DW9 DB28

DW8 DB27

DW7 DB26

DW6 DB25

DW5 DB24

DW4 DB23

DW3 DB22

DW2 DB21

DW1 DB20

DB19

DB18

DB17

DB16

DB15

DB14

DB13

DB12

DB10
DB11

DB9

DB8

DB6

DB5

DB3

DB2

DB1
DB7

DB4

DB0
C4 (0)

C3 (1)

C2 (0)

C1 (0)
TD10
IFB1

DS3

DS2
DP1

DS1
IFB2

TD9

TD8

TD7

TD6

TD5

TD4

TD3

TD2

TD1

RI2

RI1
IF_FILTER _ DP1 DOT_PRODUCT
IFB2 IFB1 BW
0 CROSS_PRODUCT
0 0 9kHz 1 DOT_PRODUCT
0 1 13.5kHz
1 0 18.5kHz
1 1 INVALID
RI2 RI1 Rx_INVERT
0 0 NORMAL
0 1 INVERT CLK
1 0 INVERT DATA
1 1 INVERT CLK/DATA DS3 DS2 DS1 DEMOD_SCHEME
DW10 . DW6 DW5 DW4 DW3 DW2 DW1 POST_DEMOD_BW 0 0 0 2FSK LINEAR DEMODULATOR
0 0 1 2FSK CORRELATOR DEMODULATOR
0 . 0 0 0 0 0 1 1
0 1 0 3FSK DEMODULATOR
0 . 0 0 0 0 1 0 2
0 1 1 4FSK DEMODULATOR
. . . . . . . . .
1 0 0 RESERVED
. . . . . . . . .
1 0 1 RESERVED
. . . . . . . . .
1 1 0 RESERVED
. . . . . . . . .
1 1 1 RESERVED
1 . 1 1 1 1 1 1 1023

TD10 . TD6 TD5 TD4 TD3 TD2 TD1 DISCRIMINATOR_BW

0 . 0 0 0 0 0 1 1
0 . 0 0 0 0 1 0 2
. . . . . . . . .
. . . . . . . . .
. . . . . . . . .

08635-065
. . . . . . . . .
1 . 0 1 0 1 0 0 660

  
 
  
 


  
  
 
  

  
    
   
 

  
  
  
 
 DB24 ADJUST_DIRECTION

IF_CAL_COARSE
ADJUST_UP/DN

IR_PHASE_
ADJUST_I/Q
IR_GAIN_

IR_GAIN_

IR_GAIN_ IR_PHASE_ ADDRESS

ADJUST_MAG ADJUST_MAG IF_FILTER_ADJUST IF_FILTER_DIVIDER BITS
DB31

DB30

DB29

GM4 DB28

GM3 DB27

GM2 DB26

DB25

DB23

DB22

DB21

DB20

IFA6 DB19

IFA5 DB18

IFA4 DB17

IFA3 DB16

IFA2 DB15

IFA1 DB14

IFD9 DB13

IFD8 DB12

IFD6 DB10
IFD7 DB11

DB6

DB5

DB2

DB1
DB9

DB8

DB7

DB4

DB3

DB0
C4 (0)

C3 (1)

C2 (0)

C1 (1)
IFD3

IFD2
IFD5

IFD4

IFD1
GM5

GM1
GQ1
GA1

PM4

PM3

PM2
PD1

CC1
PM1
CC1 IF_CAL_COARSE
0 DISABLED
1 ENABLED
IR_PHASE_
PM4 PM3 PM2 PM1 ADJUST_MAG

0 0 0 0 0 IF_FILTER_
0 0 0 1 1 IFD9 . IFD6 IFD5 IFD4 IFD3 IFD2 IFD1 DIVIDER
0 0 1 0 2 0 . 0 0 0 0 0 1 1
. . . . ... 0 . 0 0 0 0 1 0 2
1 1 1 1 15 . . . . . . . . .
. . . . . . . . .
. . . . . . . . .
PD1 IR_PHASE_ADJUST_DIRECTION . . . . . . . . .
1 . 1 1 1 1 1 1 511
0 ADJUST I CH
1 ADJUST Q CH

IR_GAIN_
GM5 GM4 GM3 GM2 GM1 ADJUST_MAG

0 0 0 0 0 0
0 0 0 0 1 1 IFA6 IFA5 ... IFA2 IFA1 IF_FILTER_ADJUST
0 0 0 1 0 2 0 0 ... 0 0 0
. . . . . ... 0 0 ... 0 1 +1
1 1 1 1 1 31 0 ...
0 1 0 +2
.. .. ... .. .. ...
0 1 ... 1 1 +31
GQ1 IR_GAIN_ADJUST_I/Q 1 0 ... 0 0 0
0 ADJUST I CH 1 0 ... 0 1 –1
1 ADJUST Q CH 1 0 ... 1 0 –2
1 . ... . . ...
GA1 IR_GAIN_ADJUST_UP/DN 1 1 ... 1 1 –31

08635-066
0 GAIN
1 ATTENUATE

 




 IRC1 DB28 DRIVE_LEVEL
SOURCE ÷2

IF_FINE_
SOURCE_
IRD1 DB30 IR_CAL_

CAL
IRC2 DB29 IR_CAL_ ADDRESS
IF_CAL_DWELL_TIME IF_CAL_UPPER_TONE_DIVIDE IF_CAL_LOWER_TONE_DIVIDE BITS

DB27

DB26

DB25

DB24

DB23

DB22

DB21

DB20

DB19

DB18

DB17

DB16

DB15

DB14

DB13

DB12

DB10
DB11

DB9

DB8

DB5

DB4

DB1
DB7

DB6

DB3

DB2

DB0
C4 (0)

C3 (1)

C2 (1)

C1 (0)
CD6

CD3

CD2
CD7

CD5

CD4

CD1

UT7

UT6

UT3

FC1
UT8

UT5

UT4

UT2

UT1

LT8

LT5

LT4

LT1
LT7

LT6

LT3

LT2
IRD1 IR_CAL_SOURCE ÷2
0 SOURCE ÷2 OFF
1 SOURCE ÷2 ON IF_CAL_UPPER_ FC1 IF_FINE_CAL
UT8 UT7 ... UT3 UT2 UT1 TONE_DIVIDE
0 DISABLED
0 0 ... 0 0 1 1 1 ENABLED
0 0 ... 0 1 0 2
IR_CAL_SOURCE_
0 0 ... 0 1 1 3
IRC2 IRC1 DRIVE_LEVEL
. . ... . . . .
0 0 OFF . . ... . . . .
0 1 LOW
0 1 ... 1 1 1 127
1 0 MED
1 1 HIGH

IF_CAL_LOWER_
LT8 LT7 ... LT3 LT2 LT1 TONE_DIVIDE
0 0 ... 0 0 1 1
IF_CAL_ 0 0 ... 0 1 0 2
CD7 ... CD3 CD2 CD1 DWELL_TIME 0 0 ... 0 1 1 3
. . ... . . . .
0 ... 0 0 1 1
. . ... . . . .
0 ... 0 1 0 2
0 ... 0 1 1 3 1 1 ... 1 1 1 255
. ... . . . .

08635-067
. ... . . . .
1 ... 1 1 1 127

 




 
 READBACK_ ADC_ CONTROL
SELECT MODE BITS

DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

RB3 RB2 RB1 AD2 AD1 C4 (0) C3 (1) C2 (1) C1 (1)

RB3 READBACK_SELECT AD2 AD1 ADC_MODE

0 DISABLED 0 0 MEASURE RSSI
1 ENABLED 0 1 BATTERY VOLTAGE
1 0 TEMP SENSOR
1 1 TO EXTERNAL PIN
RB2 RB1 READBACK MODE
0 0 AFC WORD
0 1 ADC OUTPUT

08635-068
1 0 FILTER CAL
1 1 SILICON REV

 


 Tx/Rx_SWITCH_
PA_ENABLE_

LNA/MIXER_
LOG_AMP_
COUNTER_

RESERVED
Rx_MODE

DEMOD_

FILTER_

SYNTH_
ENABLE
ENABLE

ENABLE

ENABLE
ENABLE

ENABLE
ENABLE
RESET

ADC_
CONTROL
Rx_RESET BITS

DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

CR1 RR2 RR1 PD7 SW1 LE1 PD6 PD5 PD4 PD3 RES PD1 C4 (1) C3 (0) C2 (0) C1 (0)

CR1 COUNTER_RESET PD1 SYNTH_ENABLE

0 NORMAL 0 SYNTH OFF
1 RESET 1 SYNTH ON

RR2 CDR_RESET
0 NORMAL
1 RESET

RR1 DEMOD_RESET
0 NORMAL PD3 LNA/MIXER_ENABLE
1 RESET
0 LNA/MIXER OFF
1 LNA/MIXER ON
PD7 PA_ENABLE_Rx_MODE
0 PA OFF
1 PA ON PD4 FILTER_ENABLE
0 FILTER OFF
SW1 Tx/Rx_SWITCH_ENABLE 1 FILTER ON
0 DEFAULT (ON)
1 OFF PD5 ADC_ENABLE

LE1 LOG_AMP_ENABLE 0 ADC OFF

1 ADC ON
0 LOG AMP OFF
1 LOG AMP ON

PD6 DEMOD_ENABLE

08635-069
0 DEMOD OFF
1 DEMOD ON
 LNA_MODE
LINEARITY

CURRENT
FILTER_
MIXER_
LNA_ FILTER_ LNA_ AGC_ ADDRESS
BIAS GAIN GAIN MODE AGC_HIGH_THRESHOLD AGC_LOW_THRESHOLD BITS
DB28

DB27

DB26

DB25

DB24

DB23

DB22

DB21

DB20

DB19

DB18

DB17

DB16

DB15

DB14

DB13

DB12

DB10
DB11

DB8

DB7

DB3

DB2

DB1
DB9

DB6

DB5

DB4

DB0
C4 (1)

C3 (0)

C2 (0)

C1 (1)
GM2

GM1
LM1

GH7

GH6

GH3

GH2

GH1
GH5

GH4
ML1

FG1

LG2
FG2

LG1

GL7

GL6

GL5

GL4

GL3

GL2

GL1
LI2

LI1

FI1
ML1 MIXER_LINEARITY AGC_LOW_
GM2 GM1 AGC_MODE
GL7 GL6 GL5 GL4 GL3 GL2 GL1 THRESHOLD
0 DEFAULT
0 0 AUTO AGC
1 HIGH 0 0 0 0 0 0 1 1
0 1 MANUAL AGC
0 0 0 0 0 1 0 2
1 0 FREEZE AGC
0 0 0 0 0 1 1 3
LI2 LI1 LNA_BIAS 1 1 RESERVED
0 0 0 0 1 0 0 4
0 0 800µA (DEFAULT) . . . . . . . .
. . . . . . . .
. . . . . . . .
1 1 1 1 1 0 1 61
LM1 LNA_MODE 1 1 1 1 1 1 0 62
0 DEFAULT 1 1 1 1 1 1 1 63
1 REDUCED GAIN
AGC_HIGH_
GH7 GH6 GH5 GH4 GH3 GH2 GH1 THRESHOLD
FI1 FILTER_CURRENT
0 0 0 0 0 0 1 1
0 LOW
0 0 0 0 0 1 0 2
1 HIGH
0 0 0 0 0 1 1 3
0 0 0 0 1 0 0 4
FG2 FG1 FILTER_GAIN . . . . . . . .
. . . . . . . .
0 0 8
. . . . . . . .
0 1 24
1 0 0 1 1 1 0 78
1 0 72
1 0 0 1 1 1 1 79
1 1 INVALID
1 0 1 0 0 0 0 80

LG2 LG1 LNA_GAIN

0 0 3
0 1 10

08635-070
1 0 30
1 1 INVALID

 

 
 AFC_EN
ADDRESS
MAX_AFC_RANGE KP KI AFC_SCALING_FACTOR BITS

DB11
DB31

DB30

DB29

DB28

DB27

DB26

DB25

DB24

DB23

DB22

DB21

DB20

DB19

DB18

DB17

DB16

DB15

DB14

DB13

DB12

DB10

DB9

DB8

DB7

DB4

DB0
DB6

DB5

DB3

DB2

DB1
C4 (1)

C3 (0)

C2 (1)

C1 (0)
MA8

MA4

MA3
MA7

MA6

MA5

MA2

MA1

AE1
KP2
KP3

KP1

M12

M10
M11
KI4

KI3

KI2

KI1

M9

M5
M8

M7

M6

M4

M1
M3

M2
KP3 KP2 KP1 KP KI4 KI3 KI2 KI1 KI AE1 AFC_EN
0 0 0 2^0 0 0 0 0 2^0 0 AFC OFF
0 0 1 2^1 0 0 0 1 2^1 1 AFC ON
. . . ... . . . . ...
1 1 1 2^7 1 1 1 1 2^15

AFC_SCALING_
MA8 ... MA3 MA2 MA1 MAX_AFC_RANGE M12 ... M3 M2 M1 FACTOR
0 ... 0 0 1 1 0 ... 0 0 1 1
0 ... 0 1 0 2 0 ... 0 1 0 2
0 ... 0 1 1 3 0 ... 0 1 1 3
0 ... 1 0 0 4 0 ... 1 0 0 4
. ... . . . . . ... . . . .
. ... . . . . . ... . . . .
. ... . . . . . ... . . . .
1 ... 1 0 1 253 1 ... 1 0 1 4093

08635-071
1 ... 1 1 0 254 1 ... 1 1 0 4094
1 ... 1 1 1 255 1 ... 1 1 1 4095

 

  
  
 




 SYNC_BYTE_
TOLERANCE
MATCHING_

LENGTH
CONTROL
SYNC_BYTE_SEQUENCE BITS
SB24 DB31

SB23 DB30

SB22 DB29

SB21 DB28

SB20 DB27

SB19 DB26

SB18 DB25

SB17 DB24

SB16 DB23

SB15 DB22

SB14 DB21

SB13 DB20

SB12 DB19

SB11 DB18

SB10 DB17

DB16

DB15

DB14

DB13

DB12

DB10
DB11

DB8

DB7

DB6

DB4

DB3
DB9

DB5

DB2

DB1

DB0
C4 (1)

C3 (0)

C2 (1)

C1 (1)
MT2

MT1
SB8

SB5

SB3

SB1
SB9

SB7

SB6

SB4

SB2

PL1
PL2
SYNC_BYTE_
PL2 PL1 LENGTH
0 0 12 BITS
0 1 16 BITS
1 0 20 BITS
1 1 24 BITS

MATCHING_
MT2 MT1 TOLERANCE
0 0 ACCEPT 0 ERRORS
0 1 ACCEPT 1 ERROR

08635-072
1 0 ACCEPT 2 ERRORS
1 1 ACCEPT 3 ERRORS

THRESHOLD_
SWD_MODE

LOCK_

MODE

CONTROL
DATA_PACKET_LENGTH BITS
DB15

DB14

DB13

DB12

DB11

DB10

DB9

DB8

DB7

DB5

DB4

DB3

DB2

DB1

DB0
DB6

C4 (1)

C3 (1)

C2 (0)

C1 (0)
LM2

LM1
DP8

DP6

DP5

DP4

DP2

DP1
DP7

DP3

IL2

IL1

DPx DATA_PACKET_LENGTH
0 INVALID
1 1 BYTE
... ...
255 255 BYTES

ILx SWD_MODE
0 SWD PIN LOW
1 SWD PIN HIGH AFTER NEXT SYNC WORD
2 SWD PIN HIGH AFTER NEXT SYNC WORD
FOR DATA PACKET LENGTH NUMBER OF BYTES
3 SWD PIN HIGH

LMx LOCK_THRESHOLD_MODE
0 THRESHOLD FREE RUNNING
1 LOCK THRESHOLD AFTER NEXT SYNC WORD
2 LOCK THRESHOLD AFTER NEXT SYNC WORD
08635-073

FOR DATA PACKET LENGTH NUMBER OF BYTES

3 LOCK THRESHOLD
 3FSK_VITERBI_
CORRECTION

DETECTOR
VITERBI_
MEMORY
PHASE_
PATH_
3FSK_PREAMBLE_ 3FSK/4FSK_ CONTROL
TIME_VALIDATE 3FSK_CDR_THRESHOLD SLICER_THRESHOLD BITS
PTV4 DB25

PTV3 DB24

PTV2 DB23

PTV1 DB22

DB21

DB20

DB19

DB18

DB17

DB16

DB15

DB14

DB13

DB12

DB10
DB11

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0
C4 (1)

C3 (1)

C2 (0)

C1 (1)
VM2

VM1

VD1
VT7

VT6

VT5

VT4

VT3

VT2

VT1

PC1

ST7

ST6

ST5

ST4

ST3

ST2

ST1
3FSK_VITERBI_
VD1 DETECTOR
3FSK_CDR_
VT7 ... VT3 VT2 VT1 THRESHOLD 0 DISABLED
0 0 1 ENABLED
0 ... 0 OFF
0 ... 0 0 1 1
0 ... 0 1 0 2 PHASE_
0 1 1 PC1 CORRECTION
0 ... 3
. ... . . . . 0 DISABLED
. ... . . . . 1 ENABLED
1 ... 1 1 1 127

3FSK/4FSK_SLICER_
ST7 ... ST3 ST2 ST1 THRESHOLD
VITERBI_PATH _
0 ... 0 0 0 OFF
VM2 VM1 MEMORY
0 ... 0 0 1 1
0 0 4 BITS 0 ... 0 1 0 2
0 1 6 BITS 0 ... 0 1 1 3
1 0 8 BITS . ... . . . .
1 1 32 BITS . ... . . . .
1 ... 1 1 1 127

3FSK_PREMABLE_
PTV4 PTV3 PTV2 PTV1 TIME_VALIDATE
0 0 0 0 0
0 0 0 1 1
0 0 1 0 2
0 0 1 1 3
. . . . .

08635-074
. . . . .
1 1 1 1 15
 EXTENSION
RESPONSE

ED_LEAK_
ED_PEAK_

TDAC_EN
FACTOR

PULSE_

TEST_
ADDRESS
TEST_DAC_GAIN TEST_DAC_OFFSET BITS
DB31

DB30

DB29

DB28

DB27

DB26

DB25

DB24

DB23

DB22

DB21

TO16 DB20

TO15 DB19

TO14 DB18

TO13 DB17

TO12 DB16

TO11 DB15

TO10 DB14

DB13

DB12

DB11

DB10

DB6

DB5

DB3

DB2
DB9

DB8

DB7

DB4

DB1

DB0
C4 (1)

C3 (1)

C2 (1)

C1 (0)
TG4

TG3

TO7

TO6

TO2

TO1
TG2

TG1

TO9

TO8

TO5

TO4

TO3
ER2

ER1
PE2

PE1

EF3

EF2

EF1

TE1
EFx ED_LEAK_FACTOR ERx PULSE_EXTENSION TGx TEST_DAC_GAIN TE1 TEST_TDAC_EN
LEAKAGE = 0 NO PULSE EXTENSION 0 NO GAIN 0 TEST DAC DISABLED
0 2^–8 1 EXTENDED BY 1 1 × 2^1 1 TEST DAC ENABLED
1 2^–9 2 EXTENDED BY 2 ... ...
2 2^–10 3 EXTENDED BY 3 15 × 2^15
3 2^–11
4 2^–12
5 2^–13
6 2^–14
7 2^–15

PEx ED_PEAK_RESPONSE
0 FULL RESPONSE TO PEAK
1 0.5 RESPONSE TO PEAK

08635-075
2 0.25 RESPONSE TO PEAK
3 0.125 RESPONSE TO PEAK


 FORCE_LD_
OVERRIDE

REG1_PD
CAL_

HIGH ANALOG_TEST_ PLL_TEST_ PFD/CP_ Σ-Δ_TEST_ Tx_TEST_ Rx_TEST_ ADDRESS

MODES MODES CLK_MUX TEST_MODES MODES MODES MODES BITS
DB31

DB30

DB29

DB28

DB27

DB26

DB25

DB24

DB23

DB22

DB21

DB20

DB19

DB18

DB17

DB16

DB15

DB14

DB13

DB12

DB10
DB11

DB9

DB8

DB4

DB0
DB7

DB6

DB5

DB3

DB2

DB1
C4 (1)

C3 (1)

C2 (1)

C1 (1)
AM2

AM1

CM1
AM4

AM3

CM3

CM2
CO1

PM2
CO2

PM4

PM3

PM1

TM2

TM1
TM3
RD1

PC3

SD2
PC2

PC1

SD3

SD1
FH1

RT1
RT4

RT3

RT2
COx CAL_OVERRIDE
PCx PFD/CP_TEST_MODES
0 AUTO CAL
0 DEFAULT, NO BLEED
1 OVERRIDE GAIN
1 (+VE) CONSTANT BLEED
2 OVERRIDE BW
2 (–VE) CONSTANT BLEED
3 OVERRIDE BW AND GAIN
3 (–VE) PULSED BLEED
4 (–VE) PULSE BLD, DELAY UP
RD1 REG1_PD 5 CP PUMP UP
6 CP TRISTATE
0 NORMAL
7 CP PUMP DN
1 POWER-DOWN

FH1 FORCE_LD_HIGH SDx Σ-Δ_TEST_MODES

0 NORMAL 0 DEFAULT, 3RD-ORDER Σ-Δ, NO DITHER
1 FORCE 1 1ST-ORDER Σ-Δ
2 2ND-ORDER Σ-Δ
AMx ANALOG_TEST_MODES 3 DITHER TO FIRST STAGE
0 BAND GAP VOLTAGE 4 DITHER TO SECOND STAGE
1 40µA CURRENT FROM REG4 5 DITHERTO THIRD STAGE
2 FILTER I CHANNEL: STAGE 1 6 DITHER × 8
3 FILTER I CHANNEL: STAGE 2 7 DITHER × 32
4 FILTER I CHANNEL: STAGE 1
5 FILTER Q CHANNEL: STAGE 1
6 FILTER Q CHANNEL: STAGE 2 TMx Tx_TEST_MODES
7 FILTER Q CHANNEL: STAGE 1 0 NORMAL OPERATION
8 ADC REFERENCE VOLTAGE 1 Tx CARRIER ONLY
9 BIAS CURRENT FROM RSSI 5µA 2 Tx +fDEV TONE ONLY
10 FILTER COARSE CAL OSCILLATOR OUTPUT 3 Tx –fDEV TONE ONLY
11 ANALOG RSSI L I CHANNE 4 Tx "1010" PATTERN
12 OFFSET LOOP +VE FBACK V (I CH) 5 Tx PN9 DATA SEQUENCE
13 SUMMED OUTPUT OF RSSI RECTIFIER+ 6 Tx SWD PATTERN REPEATEDLY
14 SUMMED OUTPUT OF RSSI RECTIFIER–
15 BIAS CURRENT FROM BB FILTER
RTx Rx_TEST_MODES
0 NORMAL
PMx PLL_TEST_MODES
1 SCLK, SDATA I,Q
0 NORMAL OPERATION 2 REVERSE I,Q
1 R DIV 3 I,Q TO TxRxCLK, TxRxDATA
2 N DIV 4 3FSK SLICER ON TxRxDATA
3 RCNTR/2 ON MUXOUT 5 CORRELATOR SLICER ON TxRxDATA
4 NCNTR/2 ON MUXOUT 6 LINEAR SLICER ON TxRxDATA
5 ACNTR TO MUXOUT 7 SDATA TO CDR
6 PFD PUMP UP TO MUXOUT 8 ADDITIONAL FILTERING ON I,Q
7 PFD PUMP DNTO MUXOUT 9 ENABLE REG 14 DEMOD PARAMETERS
8 S DATA TO MUXOUT (OR SREAD) 10 POWER DOWN DDT AND ED IN T/4 MODE
9 ANALOG LOCK DETECT ON MUXOUT 11 ENVELOPE DETECTOR WATCHDOG DISABLED
10 END OF COARSE CAL ON MUXOUT 12 RESERVED
11 END OF FINE CAL ON MUXOUT 13 PROHIBIT CAL ACTIVE
12 FORCE NEW PRESCALER CONFIG 14 FORCE CAL ACTIVE
FOR ALL N 15 ENABLE DEMOD DURING CAL
13 TEST MUX SELECTS DATA
14 LOCK DETECT PRECISION
15 RESERVED

CMx CLK_MUX ON CLKOUT PIN

0 NORMAL, NO OUTPUT
1 DEMOD CLK
2 CDR CLK
3 SEQ CLK
4 BB OFFSET CLK
5 Σ-Δ CLK
08635-076

6 ADC CLK
7 TxRxCLK

 


 7.00 0.30
BSC SQ 0.23
PIN 1 0.18 PIN 1
INDICATOR INDICATOR
37 48
36 1

0.50
BSC EXPOSED 4.25
PAD
4.10 SQ
3.95

25 12
24 13
0.45 0.20 MIN
TOP VIEW BOTTOM VIEW
0.40
0.35 FOR PROPER CONNECTION OF
0.80 THE EXPOSED PAD, REFER TO
0.75 THE PIN CONFIGURATION AND
0.05 MAX FUNCTION DESCRIPTIONS
0.70 SECTION OF THIS DATA SHEET.
0.02 NOM
COPLANARITY
0.08
SEATING 0.20 REF

08-16-2010-B
PLANE

COMPLIANT TO JEDEC STANDARDS MO-220-WKKD.