Digital Circuits

OHM Institute,
Hyderabad.

Live Session – 10
Batch : GATE-22 Date: 30-05-2021
 Adder

A + B = 0 + 0 = 010 = 002
A + B = 0 + 1 = 110 = 012
A + B = 1 + 0 = 110 = 012
A + B = 1 + 1 = 210 = 102

Input Output
A B A + B (in decimal) C S
S = AB + AB = A  B 0 0 0 0 0
C = AB 0 1 1 0 1
1 0 1 0 1
1 1 2 1 0
Truth Table
Full Adder

Inputs Outputs
A B Ci A + B +Ci Co S
(in decimal)
0 0 0 0 0 0
0 0 1 1 0 1
0 1 0 1 0 1
0 1 1 2 1 0
1 0 0 1 0 1
1 0 1 2 1 0
1 1 0 2 1 0
1 1 1 3 1 1
Truth Table
S = ABCi + ABCi + ABCi + ABCi = m(1, 2, 4, 7) = (A  B)  Ci
Co = ABCi + ABCi + ABCi + ABCi = m(3,5, 6, 7) = AB + BCi + ACi = (A  B)Ci + AB
Half − adder Half − adder
S= AB
A
S = A  B  Cin
B

( A  B) Cin
Cin
Cout = ( A  B) Cin + AB

C = AB

Fig : 7.7
Delay Calculations:
Delay Calculations:
Delay Calculations:
Half − adder Half − adder
S= AB
A
S = A  B  Cin
B

( A  B) Cin
Cin
Cout = ( A  B) Cin + AB

C = AB

Fig : 7.7
Delay Calculations:
Subtractor:

Half subtractor
A
B
Subtractor:

Half subtractor Half subtractor

A
B D

Bin
Bout
Subtractor:
 Ripple Carry Adder

B4 A4 B3 A3 B2 A2 B1 A1

C3 C2 C1
FA4 FA3 FA2 FA1 Cin

C4 S4 S3 S2 S1
Fig : 7.20
 Ripple Carry Adder

B4 A4 B3 A3 B2 A2 B1 A1

C3 C2 C1
FA4 FA3 FA2 FA1 Cin

C4 S4 S3 S2 S1
Fig : 7.20
 Ripple Carry Adder

Half − adder Half − adder

S= AB
A
S = A  B  Cin
B

( A  B) Cin
Cin
Cout = ( A  B) Cin + AB

C = AB

Fig : 7.7
 Ripple Carry Adder

B4 A4 B3 A3 B2 A2 B1 A1

C3 C2 C1
FA4 FA3 FA2 FA1 Cin

C4 S4 S3 S2 S1
Fig : 7.20
 Carry Look Ahead (CLA) Adder

Half − adder Half − adder

S= AB
A
S = A  B  Cin
B

( A  B) Cin
Cin
Cout = ( A  B) Cin + AB

C = AB
Carry Look Ahead (CLA) Adder

C5 C5
B4
P4 P4
A4
S4
C4
G4

B3
P3
A3 P3
S3
C3
G3
Look − ahead − carry
B2 generator
P2
A2 P2
S2
C2
G2

B1
P1
A1 P1
S1
G1

C1 C1
BCD Adder
 B3 B2 B1 B0 BCD
BCD Adder codegroup

C4
4 − bit paralleladder ( 74LS83)
C0 carryfrom
thelower position
adder

BCD
S4 S3 S2 S1 S0 A3 A 2 A1 A 0 codegroup

Carryof the X
next BCDadder
correction logic

C4 C0 = 0
not used
4 − bit paralleladder ( 74LS83)

 3  2 1 0 Correction
adder
BCD sum
 Comparator

A  B(L)

A0
A = B(E)
B0

A  B(G )
 Comparator

A1
B1
A  B(G )
A0
B0
A1
B1
A = B(E)
A0
B0
A0
B0
A  B(L)
A1
B1
Q1.
Q2.
Q4.
Q5.

a) 2.4 b) 4.8 c) 6.0 d) 9.6

Q5.

a) 2.4 b) 4.8 c) 6.0 d) 9.6

Q6.
Q7.
Q8.
Q9.
Q10.
Q11.
Q11.
Q12.
 Hope the session is
useful and informative

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