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A 70W High Efficiency Power Amplifier for Base Station Applications

Conference Paper · November 2019

DOI: 10.1109/COMCAS44984.2019.8958420

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 A 70W High Efficiency Power Amplifier for Base Station
Applications
M.Alon, S.Singer

Tel Aviv University, meirsate@hotmail.com, singer@gmail.com, Israel

Abstract High Efficiency power amplifier for cellular base harmonic at the center frequency 2.7 Ghz. The markers at the
station is in high demand as 5G infrastructure will include more equal efficiency contours were placed at the periphery of the
cells in order to cover denser areas of transport. High Efficiency smith.
power amplifiers are demanded, as they serve a key bottle neck
in each cell. high efficiency power amplifier is introduced with This knowledge allows a low pass matching to be
peak power of 70W in a range of 2Ghz- 3.6Ghz bandwidth with preformed in order to maintain the desired match for the
50-62% efficiency. The design makes harmonic engineering till fundamental and harmonics.
the 3rd harmonic at the output and at the input of the power
amplifier, in order to reach the highest efficiency. The amplifier
is tested with a 40Mhz LTE signal with DPD implementation. .
Index Terms —Load Pull, power amplifiers, delay filters,
delay-lines,.

I. INTRODUCTION
Power amplifiers is the key component in the design of
future base station cells as the number of cells increases
gradually there is a demand for higher efficiency. power
amplifier efficiency is highly dependent on the frequency
content at the output and at the input as well.
Different Power Amplifiers Topologies are implemented in
order to reach high efficiency amplifiers when the power is
back off in high PAPR communication signals, from
traditional Class AB [1,2] power amplifiers, continuous modes (a)
[4,5] Doherty and Envelope Tracking[5].
In order to increase efficiency the harmonic contents of the
voltage and current signals should be considered. Load pull is
preformed usually for the fundamental and harmonics in order
to reach the optimum design goals.
In this paper, a broadband 90W high power amplifier
QPD0060 of Qorvo is analyzed. The optimal impedances for
the amplifier were examined and a wideband step impedance
matching network based on Chebyshev coefficient were
designed. the PA was introduced with a 40 Mhz LTE signal
with digital pre-distortion (DPD) implementation. (b) (c)

Fig. 1 Load pull for desired impedances,(a) Fundamental frequency

II. FUNDAMENTAL AND HARMONIC ANALYSIS
The design procedure starts with a Load Pull procedure
ranged up to 12 Ghz in order to include the third harmonic
contents. The load impedances are shown in Fig .1 on the
smith chart while the desired bandwidth is 2- 3.6 Ghz. The
main points of the load are as follow, . 3.3
3.5 , . 3.3 ∗ 0.37 , . 2.1 ∗ 2.8 , these
points reach an efficiency in the range of 65-80%, while the
highest efficiency is at low frequencies. The second and third
harmonic load pull contents were also examined in order to
maximize the efficiency. It can be seen in the harmonic desired
impedances an efficiency persistence once the values are
maintained near the periphery of the smith chart as shown in
Fig. 1, (a) for the second harmonic and (b) for the third
of 2.7Ghz (b) second harmonic (c) third harmonic ,
III. POWER AMPLIFIER DESIGN
The matching network should reflect the optimal
∗ impedances to the PA in order to reach the desired power and
efficiency. A low pass matching network was chosen for this
design as it also matches the harmonic impedances needed.
The stepped impedance matching network use different
transmission lines (TL) impedance in order to design an
inductor and capacitor. In order to implement an inductor a
high impedance TL is used and a low impedance TL for A
capacitor. This kind of matching network gives much lower
volume design compared to stubs implementation.
The design procedure used in this article is as follows:
 1) Defining the bandwidth needed band transformation
matching coefficient.
2) Using a low pass Chebyshev architecture which
developed in [8,9], a 80% bandwidth coefficient with
15:1 transformation. The center frequency was
chosen as 2.8 .
3) The low pass coefficients which supply's the
inductors and capacitors needed to fulfil the spec are
transformed to the stepped impedance [7] network
shown in Fig. 2 by using,:
(1)
And:
. (2)
is the cut off frequency calculated with respect to the the
center frequency of the low pass filter. Where is the phase
constant, is the physical length of TL, and are the low
impedance TL and high impedances TL respectively.
High matching transformation in the low pass components is
needed, the capacitor value is high in order to decrease the real
value of the 50 Ω to the desired value at the drain of the
transistor. so to stay in the approximation zone of the stepped
TL lines, the chosen values for the design were
5 Ω, 40 Ω. the dielectric thickness were chosen
appropriately in order to reach this goal, while taking a
respectively thinner dielectric material in order to reach lower
width of TL'S. The dielectric material chosen is Rogers 4003C
with relative dielectric constant of 3.55 with 8 mil thickness.
The width of the lines chosen for the first iteration were 280
mil for the , and 25 mil for . These values were further
optimized in order to get the desired impedances at the input
of the matching network.
Fig. 2. Stepped micro strip architecture
On the input side an S parameter analysis were made in
order to achieve:
5
10 20
Choosing the right input components, capacitors and
resistors in order to stand in the above constrains and to have
a stable system. The next step included matching the power
amplifier with a Chebyshev transformation. The input
matching is shown in Fig. 3 as an EM simulation was
preformed.
Fig. 3 EM Simulation of the amplifier by ADS
IV. POWER AMPLIFIER SIMULATION AND RESULTS
A 90W Qorvo device QPD0060 is used in order to design
the Power Amplifier using simulation engine of ADS from
Keysignt and Modelitics measured Model.
Usually one of the main challenges in the design of the
matching circuit is tracking as close as possible to the optimum
frequencies while the matching circuit is a Foster type while
the optimum points are non Foster. secondly, in order to have
high bandwidth a compromise should be made in efficiency
aspect. Simulations showed at discrete frequencies high
efficiency reaching 80% especially at low frequencies of the
desired bandwidth. in order to achieve high bandwidth the
optimization had to move to less optimized contours in the
PAE contours.
The complete Electromagnetic simulation done in
Momentum (ADS) is shown in Fig. 3 showing the stepped
matching network at the output and at the input. The device
can be seen at the center.
After optimizing both the input and output Matching while
implementing a complete EM model in order to reach gain and
output power flatness ,the Simulation results are shown in Fig.
3, it can be seen a 50-62% efficiency over all the desired
bandwidth 2- 3.6Ghz. Output power close to 48 1 .
70
Simulated OutputPower
Simulated Gain
60 Simulated Efficiency
50
40
30
10
2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
Frequency (Ghz)
Fig. 4. PAE, Output Power and Gain (Simulation).

The Layout Circuit is shown in Fig. 4 made in Altium.
The fabricate PA PCB board was mounted on a cooling
substrate in order to preform good heat sinking as shown in
Fig. 5.
The total power added efficiency reached 55%. Other
frequencies will be tested In the future as the driver didn't
reach the desired power needed for the final PA.

Fig. 4 Complete PCB Circuit (Layout)

Fig. 7 X ray of under the Chip, Verify the Vias are filled, some
are voided.

Fig. 5 Complete PCB Circuit on heat sink .

Figure 7 shows the X ray of the chip, the PCB is also

soldered to the heat sink. it can be seen some voids via's and Fig. 8 S11 parameter
air bubbles in the PCB connections. These air bubbles resist
the heat transfer from the chip. S21
17
After assembly the PA undergo firstly an S parameters
16
testing, Fig. 8 shows the S11 and Fig.9 the S21 as over the
complete band. in Fig.5 there can be seen some corrections in 15

the PCB as to match the simulation. These corrections can be 14

explained as the model was taken with a substrate thickness
off 20 mil and the circuit built here is 8 mil thickness. This 13

difference influence the impedance of the source to ground. 12

The next testing was Power Added Efficiency (PAE). The
11
PA was introduced with a pulses of nominal power using
signal generator SMW200A and a FSW8 spectrum analyzer 10

from Rohde and Shwarz company, Fig. 10 shows the complete 9

system. The Efficiency measurement was done at center
frequency of 2.8Ghz, the output power measured was 48.6 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
dBm ( 72.4 W). the power from the power supply was measure Frequency 109

on a sensing resistor of 220 Ω. The input power to the PA Fig. 9 S11 parameter
were measured by a directional coupler with a peak sensor A similarity was found between the result in fig. 4, still the
form Rohde Schwarz. The value read was 36.75 dBm (4.7W). gain needs to be optimized to get flatter gain response.
 V.LTE SIGNAL
A 40Mhz LTE - 2.5W signal is produces by A Zynq Xilinx
FPGA board is shown in Fig.11 with a wideband transceiver
AD9375 supplied by Analog Devices in order to examine the
ACPR performance required for downlink performance, and
to verify the linearity performance.
It can be seen at figure 12 the signal at the output of the PA
with a DPD implementation made. The result reach about -54
dBc of ACPR.

Fig. 12 ACPR Testing with DPD implementaion.

ACKNOWLEDGEMENT
The authors wish to acknowledge the assistance and support
of the Amir Shalom from Analog Devices Israel, ADS of
Keysight by Meidan Borochov, Aharon Sagiv from Mini
Circuit and Itamar and Sharon from Interligent Company
where the testing begun. Also great thanks to Yariv Shavit
from Eastronics (Rohde Schwarz) for the Testing assistance.
Also great thanks to Alex Genayzer from Eastronics (Rohde
Schwarz) for coordinating the Equipment.
Fig. 10 Rohde Schwarz Equipment Setup.
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