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Acer Aspire 5310-5315-5710 1 JDW50-JDY70 - LA-3771P - Rev 0.3
Acer Aspire 5310-5315-5710 1 JDW50-JDY70 - LA-3771P - Rev 0.3
1 1
Compal Confidential
2 2
3 2007-4-12 3
REV: 0.3
4 4
A
Dr-Bios.com
B
Security Classification
Issued Date 2007/1/15
Compal Secret Data
Deciphered Date 2007/12/25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C D
Title
Size
B
Date:
Compal Electronics, Inc.
Document Number
Cover Page
JDW50/JDYL70 M/B LA-3771P
Monday, April 16, 2007
E
Sheet 1 of 44
Rev
0.2
A B C D E
Compal Confidential
Intel Merom Processor Thermal Sensor Clock Generator
Fan Control
Model Name : JDW50/70 page 33
ADM1032
uPGA-478 Package page 4 page 14
File Name : LA-3771P
(Socket M) page 4,5
1 1
FSB
H_A#(3..35) 533/667MHz H_D#(0..63)
DVI-D Conn. LCD Conn. CRT & TV-out
page 16 page 16 page 17
Intel Memory BUS(DDRII)
LVDS 200pin DDRII-SO-DIMM X2
LVDS SDVO
945/PM/GM/943GML Dual Channel BANK 0, 1, 2, 3 page 12,13
DVI
1.8V DDRII 533/667
uFCBGA-1466
PCI-Express page 6,7,8,9,10,11
MXM II VGA/B
DMI C-Link USB conn x2 Bluetooth CMOS
page 15
page 26
Conn page 27
Camera page 16
USB port 0, 2 USB port 5 USB port 3
PCI-Express
2
Intel ICH7-M 3.3V 48MHz USB
2
4 w/Woofer(JDY70) 4
page 35 page 32
A
Dr-Bios.com B
Security Classification
Issued Date 2007/1/15
Compal Secret Data
Deciphered Date 2007/12/25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C D
Title
Size
B
Date:
Document Number
Compal Electronics, Inc.
Block Diagrams
JDW50/JDYL70 M/B LA-3771P
Monday, April 16, 2007
E
Sheet 2 of 44
Rev
0.2
A B C D E
SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Voltage Rails
Full ON HIGH HIGH HIGH HIGH ON ON ON ON
Power Plane Description S1 S3 S5 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
VIN Adapter power supply (19V) N/A N/A N/A S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
B+ AC or battery power rail for power circuit. N/A N/A N/A
1
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF 1
+CPU_CORE Core voltage for CPU ON OFF OFF
+0.9VS 0.9V switched power rail for DDR terminator ON OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+1.05VS 1.05V switched power rail ON OFF OFF
+1.25VS 1.25V switched power rail ON OFF OFF
+1.5VS 1.5V switched power rail ON OFF OFF Board ID / SKU ID Table for AD channel
+1.8V 1.8V power rail for DDR ON ON OFF Vcc 3.3V +/- 5%
+1.8VS 1.8V switched power rail ON OFF OFF Ra/Rc/Re 100K +/- 5%
+2.5VS 2.5V switched power rail ON OFF OFF Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+3VALW 3.3V always on power rail ON ON ON* 0 0 0 V 0 V 0 V
+3V 3.3V power rail for SB ON ON X 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
+3V_LAN 3.3V power rail for LAN ON ON X 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+3VS 3.3V switched power rail ON OFF OFF 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
+5VALW 5V always on power rail ON ON ON* 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
+5VS 5V switched power rail ON OFF OFF 5 100K +/- 5% 1.453 V 1.650 V 1.759 V
+VSB VSB always on power rail ON ON ON* 6 200K +/- 5% 1.935 V 2.200 V 2.341 V
+RTCVCC RTC power ON ON ON 7 NC 2.500 V 3.300 V 3.300 V
2 2
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
4 4
A
Dr-Bios.comB
Security Classification
Issued Date 2007/1/15
Compal Secret Data
Deciphered Date 2007/12/25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C D
Title
Size
B
Date:
Document Number
Compal Electronics, Inc.
E
Sheet 3 of 44
Rev
0.2
5 4 3 2 1
JP22A
5
Layout Note:
Dr-Bios.com
THERMDA & THERMDC Trace / Space = 10 / 10 mil
4
Security Classification
Issued Date 2007/1/15
Compal Secret Data
Deciphered Date 2007/12/25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3 2
Title
Size
B
Date:
Document Number
Compal Electronics, Inc.
Merom (1/2)
JDW50/JDYL70 M/B LA-3771P
Monday, April 16, 2007 Sheet
1
4 of 44
Rev
0.2
5 4 3 2 1
+CPU_CORE
JP22C
100_0402_1% +CPU_CORE
+CPU_CORE 2 1 JP22B 3 x 330uF(9mOhm/3) AE18 K1
R20 VCC VSS
AE17 VCC VSS J2
42 VCCSENSE VCCSENSE AF7 AB26 1 1 1 AB15 M2
VSSSENSE AE7 VCCSENSE VSS VCC VSS
20mils 42 VSSSENSE VSSSENSE VSS AA25
+ C669 + C670 + C671
AA15 VCC VSS N1
2 1 R21 VSS AD25 @ AD15 VCC VSS T1
100_0402_1% AE26 AC15 R2
VSS 330U_D2E_2.5VM_R9 330U_D2E_2.5VM_R9 330U_D2E_2.5VM_R9 VCC VSS
+1.5VS B26 VCCA VSS AB23 AF15 VCC VSS V2
2 2 2
VSS AC24 AE15 VCC VSS W1
D 1 1 +1.05VS K6 VCCP VSS AF24 AB14 VCC VSS A26 D
C148 C153 J6 AE23 South Side Secondary AA13 D26
VCCP VSS VCC VSS
M6 VCCP VSS AA22 AD14 VCC VSS C25
10U_0805_10V4Z 0.01U_0402_16V7K N6 AD22 AC13 F25
2 2
T6
VCCP
VCCP
YONAH VSS
VSS AC21
+CPU_CORE
AF14
VCC
VCC
VSS
VSS B24
R6 VCCP VSS AF21 AE13 VCC VSS A23
K21 VCCP VSS AB19 3 x 330uF(9mOhm/3) AB12 VCC VSS D23
J21 AA19 AA12 E24
Layout Note: M21
VCCP
VCCP
VSS
VSS AD19 1 1 1 AD12
VCC
VCC
YONAH VSS
VSS B21
N21 AC19 AC12 C22
Place C626 near Pin B26 T21
VCCP VSS
AF19 + C672 + C673 + C674 AF12
VCC VSS
F22
VCCP VSS @ VCC VSS
R21 VCCP VSS AE19 AE12 VCC VSS E21
V21 AB16 330U_D2E_2.5VM_R9 330U_D2E_2.5VM_R9 330U_D2E_2.5VM_R9 AB10 B19
VCCP VSS 2 2 2 VCC VSS
W21 VCCP VSS AA16 AB9 VCC VSS A19
V6 AD16 AA10 D19
Dr-Bios.com
TRACE CLOSELY CPU < 0.5'
COMP0, COMP2 layout : Width 18mils and Space 25mils (27.4Ohms) Security Classification Compal Secret Data Compal Electronics, Inc.
COMP1, COMP3 layout : Space 25mils (55Ohms) Issued Date 2007/1/15 Deciphered Date 2007/12/25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Merom (2/2)
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JDW50/JDYL70 M/B LA-3771P
Date: Monday, April 16, 2007 Sheet 5 of 44
5 4 3 2 1
5 4 3 2 1
H_A#[3..31] 4
4 H_D#[0..63] U41A
H_D#0 F1 H9 H_A#3
HD0# HA3#
H_D#1 J1 HD1# HA4# C9 H_A#4 Description at page10
H_D#2 H1 E11 H_A#5 U41B
H_D#3 HD2# HA5# H_A#6
J6 HD3# HA6# G11
H_D#4 H3 F11 H_A#7 DMI_ITX_MRX_N0 AE35 K16 MCH_CLKSEL0
HD4# HA7# 20 DMI_ITX_MRX_N0 DMIRXN0 CFG0 MCH_CLKSEL0 14
H_D#5 K2 G12 H_A#8 DMI_ITX_MRX_N1 AF39 K18 MCH_CLKSEL1
HD5# HA8# 20 DMI_ITX_MRX_N1 DMIRXN1 CFG1 MCH_CLKSEL1 14
H_D#6 G1 F9 H_A#9 DMI_ITX_MRX_N2 AG35 J18 MCH_CLKSEL2
HD6# HA9# 20 DMI_ITX_MRX_N2 DMIRXN2 CFG2 MCH_CLKSEL2 14
H_D#7 G2 H11 H_A#10 DMI_ITX_MRX_N3 AH39 F18 CFG3 PAD
HD7# HA10# 20 DMI_ITX_MRX_N3 DMIRXN3 CFG3 T17
H_D#8 K9 J12 H_A#11 E15 CFG4 PAD
HD8# HA11# CFG4 T22
H_D#9 K1 G14 H_A#12 F15 CFG5
HD9# HA12# CFG5 CFG5 10
D H_D#10 K7 D9 H_A#13 DMI_ITX_MRX_P0 AC35 E18 CFG6 PAD D
HD10# HA13# 20 DMI_ITX_MRX_P0 DMIRXP0 CFG6 T20
H_D#11 J8 J14 H_A#14 DMI_ITX_MRX_P1 AE39 D19 CFG7
HD11# HA14# 20 DMI_ITX_MRX_P1 DMIRXP1 CFG7 CFG7 10
H_D#12 H4 H13 H_A#15 DMI_ITX_MRX_P2 AF35 D16 CFG8 PAD
HD12# HA15# 20 DMI_ITX_MRX_P2 DMIRXP2 CFG8 T19
DMI
H_D#13 J3 J15 H_A#16 DMI_ITX_MRX_P3 AG39 G16 CFG9
HD13# HA16# 20 DMI_ITX_MRX_P3 DMIRXP3 CFG9 CFG9 10
H_D#14 K11 F14 H_A#17 E16 CFG10 PAD
HD14# HA17# CFG10 T18
H_D#15 G4 D12 H_A#18 D15 CFG11
HD15# HA18# CFG11 CFG11 10
H_D#16 T10 A11 H_A#19 DMI_MTX_IRX_N0 AE37 G15 CFG12
HD16# HA19# 20 DMI_MTX_IRX_N0 DMITXN0 CFG12 CFG12 10
H_D#17 W11 C11 H_A#20 DMI_MTX_IRX_N1 AF41 K15 CFG13
HD17# HA20# 20 DMI_MTX_IRX_N1 DMITXN1 CFG13 CFG13 10
H_D#18 H_A#21 DMI_MTX_IRX_N2 CFG14
CFG
T3 HD18# HA21# A12 20 DMI_MTX_IRX_N2 AG37 DMITXN2 CFG14 C15 PAD T15
H_D#19 U7 A13 H_A#22 DMI_MTX_IRX_N3 AH41 H16 CFG15 PAD
HD19# HA22# 20 DMI_MTX_IRX_N3 DMITXN3 CFG15 T21
H_D#20 U9 E13 H_A#23 G18 CFG16
HD20# HA23# CFG16 CFG16 10
H_D#21 U11 G13 H_A#24 H15 CFG17 PAD
HD21# HA24# CFG17 T16
H_D#22 T11 F12 H_A#25 DMI_MTX_IRX_P0 AC37 J25 CFG18
HD22# HA25# 20 DMI_MTX_IRX_P0 DMITXP0 CFG18 CFG18 10
H_D#23 W9 B12 H_A#26 DMI_MTX_IRX_P1 AE41 K27 CFG19
HD23# HA26# 20 DMI_MTX_IRX_P1 DMITXP1 CFG19 CFG19 10
H_D#24 T1 B14 H_A#27 DMI_MTX_IRX_P2 AF37 J26 CFG20
HD24# HA27# 20 DMI_MTX_IRX_P2 DMITXP2 CFG20 CFG20 10
H_D#25 T8 C12 H_A#28 DMI_MTX_IRX_P3 AG41
HD25# HA28# 20 DMI_MTX_IRX_P3 DMITXP3
H_D#26 T4 A14 H_A#29
H_D#27 HD26# HA29# H_A#30 CLK_MCH_3GPLL
W7 HD27# HA30# C14 G_CLKP AG33 CLK_MCH_3GPLL 14
H_D#28 U5 D14 H_A#31 AY35 AF33 CLK_MCH_3GPLL#
HD28# HA31# 12 DDRA_CLK0 SM_CK0 G_CLKN CLK_MCH_3GPLL# 14
H_D#29 T9 AR1
HD29# 12 DDRA_CLK1 SM_CK1
H_D#30 W6 AW7 A27 CLK_DREF_96M#
CLK
HD30# 13 DDRB_CLK0 SM_CK2 D_REF_CLKN CLK_DREF_96M# 14
H_D#31 T5 AW40 A26 CLK_DREF_96M
HOST
HD31# H_REQ#[0..4] 4 13 DDRB_CLK1 SM_CK3 D_REF_CLKP CLK_DREF_96M 14
H_D#32 AB7 D8 H_REQ#0
H_D#33 HD32# HREQ#0 H_REQ#1 CLK_DREF_SSC#
AA9 HD33# HREQ#1 G8 12 DDRA_CLK0# AW35 SM_CK0# D_REF_SSCLKN C40 CLK_DREF_SSC# 14
H_D#34 W4 B8 H_REQ#2 AT1 D41 CLK_DREF_SSC
HD34# HREQ#2 12 DDRA_CLK1# SM_CK1# D_REF_SSCLKP CLK_DREF_SSC 14
H_D#35 W3 F8 H_REQ#3 AY7
HD35# HREQ#3 13 DDRB_CLK0# SM_CK2#
H_D#36 Y3 A8 H_REQ#4 AY40 H32 MCH_CLKREQ#
HD36# HREQ#4 13 DDRB_CLK1# SM_CK3# CLK_REQ# MCH_CLKREQ# 14
H_D#37 Y7
H_D#38 HD37#
W5 HD38# 12 DDRA_CKE0 AU20 SM_CKE0
DDR MUXING
C H_D#39 Y10 B9 H_ADSTB#0 AT20 C
HD39# HADSTB#0 H_ADSTB#0 4 12 DDRA_CKE1 SM_CKE1
H_D#40 AB8 C13 H_ADSTB#1 BA29 A3
HD40# HADSTB#1 H_ADSTB#1 4 13 DDRB_CKE0 SM_CKE2 NC0
H_D#41 W2 AY29 A39
HD41# 13 DDRB_CKE1 SM_CKE3 NC1
H_D#42 AA4 AG1 CLK_MCH_BCLK# A4
HD42# HCLKN CLK_MCH_BCLK# 14 NC2
H_D#43 AA7 AG2 CLK_MCH_BCLK AW13 A40
HD43# HCLKP CLK_MCH_BCLK 14 12 DDRA_SCS#0 SM_CS0# NC3
H_D#44 AA2 AW12 AW1
HD44# 12 DDRA_SCS#1 SM_CS1# NC4
H_D#45 AA6 K4 H_DSTBN#0 AY21 AW41
HD45# HDSTBN#0 H_DSTBN#0 4 13 DDRB_SCS#0 SM_CS2# NC5
H_D#46 AA10 T7 H_DSTBN#1 AW21 AY1
HD46# HDSTBN#1 H_DSTBN#1 4 13 DDRB_SCS#1 SM_CS3# NC6
H_D#47 Y8 Y5 H_DSTBN#2 BA1
NC
H_D#48 HD47# HDSTBN#2 H_DSTBN#3 H_DSTBN#2 4 NC7
AA1 HD48# HDSTBN#3 AC4 H_DSTBN#3 4 T37 PAD AL20 SM_OCDCOMP0 NC8 BA2
H_D#49 AB4 K3 H_DSTBP#0 PAD AF10 BA3
HD49# HDSTBP#0 H_DSTBP#0 4 T38 SM_OCDCOMP1 NC9
H_D#50 AC9 T6 H_DSTBP#1 BA39
H_D#51 HD50# HDSTBP#1 H_DSTBP#2 H_DSTBP#1 4 NC10
AB11 HD51# HDSTBP#2 AA5 H_DSTBP#2 4 12 DDRA_ODT0 BA13 SM_ODT0 NC11 BA40
H_D#52 AC11 AC5 H_DSTBP#3 BA12 BA41
HD52# HDSTBP#3 H_DSTBP#3 4 12 DDRA_ODT1 SM_ODT1 NC12
H_D#53 AB3 AY20 C1
+1.05VS H_D#54 HD53# +1.8V13 DDRB_ODT0 SM_ODT2 NC13
AC2 HD54# 13 DDRB_ODT1 AU21 SM_ODT3 NC14 AY41
H_D#55 AD1 J7 H_DINV#0 B2
H_D#56 HD55# HDINV#0 H_DINV#1 H_DINV#0 4 R426 180.6_0402_1% SMRCOMP NC15
AD9 HD56# HDINV#1 W8 H_DINV#1 4 2 AV9 SM_RCOMPN NC16 B41
H_D#57 AC1 U3 H_DINV#2 R425 1 2 SMRCOMP# AT9 C41
H_D#58 HD57# HDINV#2 H_DINV#3 H_DINV#2 4 80.6_0402_1% SM_RCOMPP NC17
AD7 HD58# HDINV#3 AB10 H_DINV#3 4 NC18 D1
2
54.9_0402_1%
R529
PM
H8 H_DRDY# PM_EXTTS#1 H26 AG11
RESERVED
HDRDY# H_DRDY# 4 PM_EXTTS1# RESERVED5
J13 C3 H_DEFER# 4,19 H_THERMTRIP# R5301 0_0402_5%
2 G6 AF11
HVREF0 HDEFER# H_DEFER# 4 PM_THERMTRIP# RESERVED6
H_VREF K13 D4 H_HITM# GMCH_PW ROK AH33 H7
B HVREF1 HHITM# H_HITM# 4 PWROK RESERVED7 B
H_XRCOMP E1 D3 H_HIT# MCH_RSTIN# AH34 J19
HXRCOMP HHIT# H_HIT# 4 RSTIN# RESERVED8
H_XSCOMP E2 B3 H_LOCK# A41
HXSCOMP HLOCK# H_LOCK# 4 RESERVED9
H_YRCOMP Y1 C7 H_BR0# 18 MCH_ICH_SYNC# K28 A34
HYRCOMP HBREQ0# H_BR0# 4 ICH_SYNC# RESERVED10
H_YSCOMP U1 C6 H_BNR# D28
HYSCOMP HBNR# H_BNR# 4 RESERVED11
H_SW NG0 E4 F6 H_BPRI# D27
HXSWING HBPRI# H_BPRI# 4 RESERVED12
H_SW NG1 W1 A7 H_DBSY# A35
HYSWING HDBSY# H_DBSY# 4 RESERVED13
E3 H_CPUSLP#
HCPUSLP# H_CPUSLP# 4
CALISTOGA_FCBGA1466~D
24.9_0402_1%
24.9_0402_1%
1
1
H_RS#[0..2] 4 PM@
R532
R531
B4 H_RS#0
HRS0# H_RS#1
HRS1# E6
D6 H_RS#2
HRS2# MCH_RSTIN#
18,20,22,24,28 PLT_RST#
2
2
2
+1.05VS +1.05VS SYS_PW ROK 1 2
20,30 SYS_PW ROK
R334 R332 0_0402_5%
+1.05VS 100_0402_1%
1
20/20mil
221_0603_1%
221_0603_1%
1
2
SM_VREF
100_0402_1%
R534
R535
2
R533
1
1 C354 R335
2
20,42 PM_DPRSLPVR
1
A A
2
2
1 1
0.1U_0402_16V4Z
1
200_0603_1%
Dr-Bios.com
R539
C712
R537
R538
C711
C710
2 2
1
1
2
Security Classification Compal Secret Data Compal Electronics, Inc.
2
DDRB_SDQ[0..63]
13 DDRB_SDQ[0..63]
DDRA_SDQ[0..63]
12 DDRA_SDQ[0..63] DDRB_SMA[0..13]
13 DDRB_SMA[0..13]
DDRA_SMA[0..13]
12 DDRA_SMA[0..13]
D D
U41D U41E
CALISTOGA_FCBGA1466~D CALISTOGA_FCBGA1466~D
PM@ PM@
A A
5
Dr-Bios.com 4
Security Classification
Issued Date 2007/1/15
Compal Secret Data
Deciphered Date 2007/12/25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3 2
Title
Size
B
Date:
Compal Electronics, Inc.
Calistoga (2/6)
Document Number
JDW50/JDYL70 M/B LA-3771P
Monday, April 16, 2007 Sheet
1
7 of 44
Rev
0.2
5 4 3 2 1
U41C
H27 D40 PEG_COMP 1 2 +1.5VS_PCIE
SDVOCTRL_DATA EXP_COMPI R540 24.9_0402_1%
H28 SDVOCTRL_CLK EXP_COMPO D38 10mils
F34 PCIE_GTX_C_MRX_N0
GMCH_TXOUT0+ EXP_RXN0 PCIE_GTX_C_MRX_N1 PCIE_MTX_C_GRX_N[0..15]
16 GMCH_TXOUT0+ B37 LA_DATA0 EXP_RXN1 G38 PCIE_MTX_C_GRX_N[0..15] 15
GMCH_TXOUT1+ B34 H34 PCIE_GTX_C_MRX_N2
16 GMCH_TXOUT1+ LA_DATA1 EXP_RXN2 PCIE_MTX_C_GRX_P[0..15]
GMCH_TXOUT2+ A36 J38 PCIE_GTX_C_MRX_N3
16 GMCH_TXOUT2+ LA_DATA2 EXP_RXN3 PCIE_MTX_C_GRX_P[0..15] 15
L34 PCIE_GTX_C_MRX_N4
GMCH_TXOUT0- EXP_RXN4 PCIE_GTX_C_MRX_N5 PCIE_GTX_C_MRX_N[0..15]
16 GMCH_TXOUT0- C37 LA_DATA#0 EXP_RXN5 M38 PCIE_GTX_C_MRX_N[0..15] 15
D GMCH_TXOUT1- B35 N34 PCIE_GTX_C_MRX_N6 D
16 GMCH_TXOUT1- LA_DATA#1 EXP_RXN6 PCIE_GTX_C_MRX_P[0..15]
GMCH_TXOUT2- A37 P38 PCIE_GTX_C_MRX_N7
16 GMCH_TXOUT2- LA_DATA#2 EXP_RXN7 PCIE_GTX_C_MRX_P[0..15] 15
R34 PCIE_GTX_C_MRX_N8
GMCH_TZOUT0+ EXP_RXN8 PCIE_GTX_C_MRX_N9
16 GMCH_TZOUT0+ F30 LB_DATA0 EXP_RXN9 T38
GMCH_TZOUT1+ D29 V34 PCIE_GTX_C_MRX_N10
LVDS
16 GMCH_TZOUT1+ LB_DATA1 EXP_RXN10
GMCH_TZOUT2+ F28 W38 PCIE_GTX_C_MRX_N11
16 GMCH_TZOUT2+ LB_DATA2 EXP_RXN11
Y34 PCIE_GTX_C_MRX_N12
GMCH_TZOUT0- EXP_RXN12 PCIE_GTX_C_MRX_N13
16 GMCH_TZOUT0- G30 LB_DATA#0 EXP_RXN13 AA38
GMCH_TZOUT1- D30 AB34 PCIE_GTX_C_MRX_N14
16 GMCH_TZOUT1- LB_DATA#1 EXP_RXN14
GMCH_TZOUT2- F29 AC38 PCIE_GTX_C_MRX_N15
16 GMCH_TZOUT2- LB_DATA#2 EXP_RXN15
GMCH_TXCLK+ A32 D34 PCIE_GTX_C_MRX_P0
16 GMCH_TXCLK+ LA_CLK EXP_RXP0
GMCH_TXCLK- A33 F38 PCIE_GTX_C_MRX_P1
16 GMCH_TXCLK- LA_CLK# EXP_RXP1
GMCH_TZCLK+ E26 G34 PCIE_GTX_C_MRX_P2
16 GMCH_TZCLK+ LB_CLK EXP_RXP2
GMCH_TZCLK- E27 H38 PCIE_GTX_C_MRX_P3
16 GMCH_TZCLK- LB_CLK# EXP_RXP3
PCI-EXPRESS GRAPHICS
J34 PCIE_GTX_C_MRX_P4
R541 GM@ 0_0402_5% EXP_RXP4
16 DPST_PW M 1@ R7372 D32 LBKLT_CTL EXP_RXP5 L38 PCIE_GTX_C_MRX_P5
15,28 ENBKL 1 2 LBKLT_EN 0_0402_5% LBKLT_EN J30 M34 PCIE_GTX_C_MRX_P6
LCTLA_CLK LBKLT_EN EXP_RXP6 PCIE_GTX_C_MRX_P7
H30 LCTLA_CLK EXP_RXP7 N38
LCTLB_DATA H29 P34 PCIE_GTX_C_MRX_P8
GMCH_LCD_CLK LCTLB_DATA EXP_RXP8 PCIE_GTX_C_MRX_P9
16 GMCH_LCD_CLK G26 LDDC_CLK EXP_RXP9 R38
16 GMCH_LCD_DATA GMCH_LCD_DATA G25 T34 PCIE_GTX_C_MRX_P10
GMCH_ENVDD LDDC_DATA EXP_RXP10 PCIE_GTX_C_MRX_P11
16 GMCH_ENVDD F32 LVDD_EN EXP_RXP11 V38
LIBG B38 W34 PCIE_GTX_C_MRX_P12
LIBG EXP_RXP12 PCIE_GTX_C_MRX_P13
C35 LVBG EXP_RXP13 Y38
C33 AA34 PCIE_GTX_C_MRX_P14
LVREFH EXP_RXP14 PCIE_GTX_C_MRX_P15
C32 LVREFL EXP_RXP15 AB38
TV
L36 PCIE_MTX_GRX_N4 C212 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N4
EXP_TXN4 C217 1
1 2 TV_IREF J20 TV_IREF EXP_TXN5 M40 PCIE_MTX_GRX_N5 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N5
R542 4.99K_0402_1% N36 PCIE_MTX_GRX_N6 C229 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N6
EXP_TXN6 C240 1
B16 TV_IRTNA EXP_TXN7 P40 PCIE_MTX_GRX_N7 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N7
B18 R36 PCIE_MTX_GRX_N8 C246 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N8
TV_IRTNB EXP_TXN8 C252 1
B19 TV_IRTNC EXP_TXN9 T40 PCIE_MTX_GRX_N9 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N9
V36 PCIE_MTX_GRX_N10 C261 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N10
EXP_TXN10 C270 1
J29 TV_DCONSEL1 EXP_TXN11 W40 PCIE_MTX_GRX_N11 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N11
K30 Y36 PCIE_MTX_GRX_N12 C277 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N12
TV_DCONSEL0 EXP_TXN12 C285 1
EXP_TXN13 AA40 PCIE_MTX_GRX_N13 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N13
AB36 PCIE_MTX_GRX_N14 C296 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N14
EXP_TXN14 C304 1
EXP_TXN15 AC40 PCIE_MTX_GRX_N15 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N15
GMCH_CRT_CLK C26
17 GMCH_CRT_CLK DDCCLK
CRT
GMCH_CRT_DATA C25 D36 PCIE_MTX_GRX_P0 C176 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P0
17 GMCH_CRT_DATA DDCDATA EXP_TXP0
F40 PCIE_MTX_GRX_P1 C180 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P1
EXP_TXP1 C189
17 GMCH_CRT_VSYNC H23 VSYNC EXP_TXP2 G36 PCIE_MTX_GRX_P2 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P2
G23 H40 PCIE_MTX_GRX_P3 C198 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P3
17 GMCH_CRT_HSYNC HSYNC EXP_TXP3
E23 J36 PCIE_MTX_GRX_P4 C204 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P4
17 GMCH_CRT_B BLUE EXP_TXP4
2 1 D23 L40 PCIE_MTX_GRX_P5 C214 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P5
R543 150_0402_1% BLUE# EXP_TXP5 C219
17 GMCH_CRT_G C22 GREEN EXP_TXP6 M36 PCIE_MTX_GRX_P6 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P6
2 1 B22 N40 PCIE_MTX_GRX_P7 C232 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P7
R544 150_0402_1% GREEN# EXP_TXP7 C241
17 GMCH_CRT_R A21 RED EXP_TXP8 P36 PCIE_MTX_GRX_P8 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P8
2 1 B21 R40 PCIE_MTX_GRX_P9 C248 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P9
R545 150_0402_1% RED# EXP_TXP9 C253
EXP_TXP10 T36 PCIE_MTX_GRX_P10 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P10
V40 PCIE_MTX_GRX_P11 C263 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P11
EXP_TXP11 C272
1 2 CRT_IREF J22 CRT_IREF EXP_TXP12 W36 PCIE_MTX_GRX_P12 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P12
B R546 255_0402_1% C283 1 B
EXP_TXP13 Y40 PCIE_MTX_GRX_P13 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P13
10mils AA36 PCIE_MTX_GRX_P14 C288 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P14
EXP_TXP14 C297 1
EXP_TXP15 AB40 PCIE_MTX_GRX_P15 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P15
+3VS
CALISTOGA_FCBGA1466~D
R547 1 2 10K_0402_5% GMCH_LCD_CLK PM@
5
Dr-Bios.com 4
Security Classification
Issued Date 2007/1/15
Compal Secret Data
Deciphered Date 2007/12/25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3 2
Title
Size
Custom
Date:
Compal Electronics, Inc.
Calistoga (3/6)
Document Number
JDW50/JDYL70 M/B LA-3771P
Monday, April 16, 2007
1
Sheet 8 of 44
Rev
0.2
5 4 3 2 1
D +2.5VS D
0.1U_0402_16V4Z
0.1U_0402_16V4Z
(800mA) AB14 B30 +2.5VS
VTT1 VCCTX_LVDS0
W14 VTT2 C30 1 1
VCCTX_LVDS1 +1.5VS_PCIE R558
V14 VTT3 A30 1 1
VCCTX_LVDS2
C715
C717
T14 0_0805_5% + C716 + C718
R14
VTT4
VTT5 VCC3G0
AB41 W=60 mils 2 1 +1.5VS
P14 AJ41 330U_D2E_2.5VM 330U_D2E_2.5VM
VTT6 VCC3G1 2 2 2 2
10U_0805_10V4Z
10U_0805_10V4Z
N14 L41 (1500mA) 1
VTT7 VCC3G2
M14 VTT8 N41 1 1
VCC3G3 C719 +
L14 R41
VTT9 VCC3G4 +2.5VS
C721
C720
AD13 V41
VTT10 VCC3G5
0.1U_0402_16V4Z
AC13 Y41 220U_D2_2VMR15
VTT11 VCC3G6 2 2 2
AB13 1
VTT12
1 AA13 VTT13 AC33 +1.5VS_3GPLL
VCCA_3GPLL
C722
Y13 G41 +2.5VS
C713 + VTT14 VCCA_3GBG (2mA) +3VS_TVDACB L59 +3VS +3VS_TVDACA L60 +3VS
W13 H41
VTT15 VSSA_3GBG L58 2 MBK1608301YZF_0603 MBK1608301YZF_0603
V13
220U_D2_2VMR15 VTT16 MBK1608301YZF_0603
U13 2 1 2 1
2 VTT17
0.022U_0402_16V7K
0.022U_0402_16V7K
T13 E21 (70mA) +2.5VS_CRTDAC 2 1 +2.5VS
VTT18 VCCA_CRTDAC0
0.022U_0402_16V7K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
R13 F21 1
VTT19 VCCA_CRTDAC1
0.1U_0402_16V4Z
N13 VTT20 VSSA_CRTDAC2
G21 1 close pin G41 1 1 1 1
+ C727
M13 1 1
VTT21
C724
C725
C730
+ C729
C726
L13
VTT22
C723
C728
AB12 B26 (50mA) +1.5VS_DPLLA 220U_D2_4VM
VTT23 VCCA_DPLLA 220U_D2_4VM 2 2 2 2 2
AA12 C39 (50mA) +1.5VS_DPLLB
VTT24 VCCA_DPLLB 2 2 2
Y12 AF1 (45mA) +1.5VS_HPLL
VTT25 VCCA_HPLL
C
W12 VTT26 CRTDAC: Route caps within C
V12 VTT27
U12 A38 (10mA) +2.5VS
250mil of Alviso. Route FB
VTT28 VCCA_LVDS
T12 VTT29 B39 within 3" of Calistoga
VSSA_LVDS
R12 VTT30
P12
VTT31
AF2 (45mA)
N12
M12
VTT32
VTT33
P O W E R VCCA_MPLL +1.5VS_MPLL +3VS_TVDACC L61 +3VS
+2.5VS
2.2U_0805_10V6K
4.7U_0805_10V4Z
0.022U_0402_16V7K
1 1 P11 (120mA)
VTT36
C731
C732
0.01U_0402_16V7K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
N11 VTT37
M11 VTT38 E19 +3VS_TVDACA 1 1
VCCA_TVDACA0
R10 VTT39 F19
2 2 VCCA_TVDACA1
C736
C735
P10 C20 +3VS_TVDACB 1 1
VTT40 VCCA_TVDACB0
C733
C734
N10 VTT41 D20
VCCA_TVDACB1 2 2
M10 E20 +3VS_TVDACC
VTT42 VCCA_TVDACC0
P9 F20
VTT43 VCCA_TVDACC1 2 2
N9 VTT44
M9
VTT45
R8 AH1 (150mA) +1.5VS
VTT46 VCCD_HMPLL0
P8 AH2
VTT47 VCCD_HMPLL1
N8
VTT48 close pin A38
M8
VTT49
P7 A28
VTT50 VCCD_LVDS0 (20mA)
N7 B28
VTT51 VCCD_LVDS1
M7 C28
R6
P6
VTT52
VTT53
VCCD_LVDS2
D21 (24mA)
+3VS_TVBG R559
0_0603_5%
+3VS PCI-E/MEM/PSB PLL decoupling
VTT54 VCCD_TVDAC +1.5VS_TVDAC
M6 H19 2 1
VTT55 VCCDQ_TVDAC
0.022U_0402_16V7K
MCH_A6 A6
VTT56 +1.5VS_3GPLL +1.5VS +1.5VS_TVDAC +1.5VS
0.1U_0402_16V4Z
0.47U_0603_16V4Z
B B
0.1U_0402_16V4Z
C739
C741
C737
0.022U_0402_16V7K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
M5 VTT60 1 1
C740
10U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
P4 VTT61 VCCAUX0 AK31
2 2
C738
N4 VTT62 AF31 1 1 1 1 1 1
2 VCCAUX1
C742
C744
C745
C747
M4 AE31
VTT63 VCCAUX2 2 2
C746
C743
R3 AC31
VTT64 VCCAUX3 @ @
P3 AL30
VTT65 VCCAUX4 2 2 2 2 2 2
N3 VTT66 AK30
VCCAUX5
M3 AJ30
VTT67 VCCAUX6 +1.5VS
0.22U_0603_16V7K
R2 VTT68 AH30
VCCAUX7
P2 VTT69 AG30
VCCAUX8
1 M2 AF30
VTT70 VCCAUX9
C748
MCH_D2
0.1U_0402_16V4Z
D2 VTT71 AE30
VCCAUX10
0.22U_0603_16V7K
2 VTT73 VCCAUX12
C749
1 P1 AG29
VTT74 VCCAUX13 +1.5VS_MPLL +1.5VS_HPLL
C750
2 VCCAUX16
AD29 45mA Max. 2 1 +1.5VS 45mA Max. 2 1 +1.5VS
1 VCCAUX17 AC29
0.1U_0402_16V4Z
0.1U_0402_16V4Z
AG28
VCCAUX18
C751
10U_0805_10V4Z
10U_0805_10V4Z
VCCAUX19 AF28
AE28 1 1 1 1
2 VCCAUX20
C752
C754
VCCAUX21 AH22
C753
C755
AJ21
VCCAUX22
AG14 AH21
VCCAUX32 VCCAUX23 2 2 2 2
AF14 VCCAUX33 AJ20
VCCAUX24
AE14 AH20
VCCAUX34 VCCAUX25
Y14 VCCAUX35 AH19
VCCAUX26
AF13 P19
VCCAUX36 VCCAUX27
AE13 VCCAUX37 P16
+1.5VS VCCAUX28
AF12 VCCAUX38 AH15
A VCCAUX29 A
AE12 P15
VCCAUX39 VCCAUX30
AD12 VCCAUX40 AH14
VCCAUX31
Dr-Bios.com
CALISTOGA_FCBGA1466~D
PM@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (4/6)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JDW50/JDYL70 M/B LA-3771P
Date: Monday, April 16, 2007 Sheet 9 of 44
5 4 3 2 1
5 4 3 2 1
AD27 VCC_NCTF0 VCCAUX_NCTF0 AG27 AA33 VCC0 VCC_SM0 AU41 011 = 667MT/s FSB
(3500mA) AC27 AF27 W33 AT41 MCH_AT41 CFG[2:0] 001 = 533MT/s FSB
VCC_NCTF1 VCCAUX_NCTF1 VCC1 VCC_SM1 MCH_AM41
AB27 AG26 P33 AM41
VCC_NCTF2 VCCAUX_NCTF2 VCC2 VCC_SM2
AA27
VCC_NCTF3 VCCAUX_NCTF3
AF26 N33
VCC3 VCC_SM3
AU40 0 = DMI x 2
0.47U_0603_16V4Z
0.47U_0603_16V4Z
Y27 VCC_NCTF4 VCCAUX_NCTF4 AG25 L33 VCC4 VCC_SM4 BA34 CFG5 1 = DMI x 4 *(Default)
W27 AF25 J33 AY34
VCC_NCTF5 VCCAUX_NCTF5 VCC5 VCC_SM5
V27 VCC_NCTF6 VCCAUX_NCTF6 AG24 AA32 VCC6 VCC_SM6 AW34 1 1 0 = Reserved
C758
C759
D D
U27 VCC_NCTF7 VCCAUX_NCTF7 AF24 Y32 VCC7 VCC_SM7 AV34 CFG7 1 = Mobile Yonah CPU *(Default)
T27 AG23 W32 AU34
VCC_NCTF8 VCCAUX_NCTF8 VCC8 VCC_SM8
0.22U_0603_16V7K
0.22U_0603_16V7K
0.22U_0603_16V7K
C757
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
U25
VCC_NCTF27 VCCAUX_NCTF27
AA17 U30 VCC27 VCC_SM27
AH28 CFG18 1 = 1.5V
1U_0603_10V4Z
10U_0805_10V4Z
R25 VCC_NCTF29 VCCAUX_NCTF29 V17 R30 VCC29 VCC_SM29 AH27 0 = Normal Operation * (Default)
C762
C764
C761
C763
1 1 1 AD24 VCC_NCTF30 VCCAUX_NCTF30 T17 P30
VCC30 VCC_SM30 BA26 CFG19 1 = DMI Lane Reversal Enable
AC24 R17 N30 AY26
VCC_NCTF31 VCCAUX_NCTF31 VCC31 VCC_SM31 2 2 2 2
C765
C766
C767
AB24
VCC_NCTF32 VCCAUX_NCTF32 AG16 M30
VCC32 P O W E R VCC_SM32 AW26 0 = No SDVO Device Present *
2 2 2
AA24
VCC_NCTF33 VCCAUX_NCTF33
AF16 L30
VCC33 VCC_SM33
AV26 (Default)
Y24
VCC_NCTF34 VCCAUX_NCTF34
AE16 AA29 VCC34 VCC_SM34 AU26 SDVO_CTRLDATA
W24 VCC_NCTF35 VCCAUX_NCTF35
AD16 Y29 VCC35 VCC_SM35 AT26 1 = SDVO Device Present
V24 AC16 W29 VCC36 VCC_SM36 AR26
VCC_NCTF36 VCCAUX_NCTF36
U24 AB16 V29 AJ26
VCC_NCTF37 VCCAUX_NCTF37 VCC37 VCC_SM37
C
T24 VCC_NCTF38 VCCAUX_NCTF38 AA16 U29 VCC38 VCC_SM38
AH26 0 = Only PCIE or SDVO is C
R24 VCC_NCTF39 VCCAUX_NCTF39 Y16 R29 VCC39 VCC_SM39
AJ25 CFG20 operational. *(Default)
AD23 W16 P29 AH25
VCC_NCTF40 VCCAUX_NCTF40 VCC40 VCC_SM40
V23 VCC_NCTF41 VCCAUX_NCTF41
V16 M29
VCC41 VCC_SM41 AJ24 (PCIE/SDVO select) 1 = PCIE/SDVO are operating
U23 U16 L29 AH24
T23
VCC_NCTF42 VCCAUX_NCTF42
T16 AB28
VCC42 VCC_SM42
BA23 simu.
VCC_NCTF43 VCCAUX_NCTF43 VCC43 VCC_SM43
R23 R16 AA28 VCC44 VCC_SM44 AJ23
VCC_NCTF44 VCCAUX_NCTF44
0.47U_0603_16V4Z
1 AD22 AG15 Y28 BA22
VCC_NCTF45 VCCAUX_NCTF45 VCC45 VCC_SM45
V22 AF15 V28 AY22
C768 + VCC_NCTF46 VCCAUX_NCTF46 VCC46 VCC_SM46
U22 AE15 U28 VCC47 AW22 1
VCC_NCTF47 VCCAUX_NCTF47 VCC_SM47
C769
T22 AD15 T28 AV22
220U_D2_2VMR15 VCC_NCTF48 VCCAUX_NCTF48 VCC48 VCC_SM48
R22 AC15 R28 VCC49 AU22
2 VCC_NCTF49 VCCAUX_NCTF49 VCC_SM49
AD21 AB15 P28 VCC50 AT22
VCC_NCTF50 VCCAUX_NCTF50 VCC_SM50 2 R564
V21 AA15 N28 AR22 6 CFG5 1 2 @ 2.2K_0402_5%
VCC_NCTF51 VCCAUX_NCTF51 VCC51 VCC_SM51
U21 Y15 M28 AP22
VCC_NCTF52 VCCAUX_NCTF52 VCC52 VCC_SM52 R565
T21 W15 L28 VCC53 VCC_SM53 AK22 6 CFG7 1 2 @ 2.2K_0402_5%
VCC_NCTF53 VCCAUX_NCTF53
R21 V15 P27 AJ22
VCC_NCTF54 VCCAUX_NCTF54 VCC54 VCC_SM54 R566
AD20 U15 N27
VCC55 VCC_SM55
AK21 6 CFG9 1 2 @ 2.2K_0402_5%
VCC_NCTF55 VCCAUX_NCTF55
V20 VCC_NCTF56 VCCAUX_NCTF56 T15 M27 VCC56 VCC_SM56 AK20 Place near pin BA23
U20 R15 L27 BA19 R567 1 2 @ 2.2K_0402_5%
VCC_NCTF57 VCCAUX_NCTF57 VCC57 VCC_SM57 6 CFG11
T20 P26 VCC58 AY19
VCC_NCTF58 VCC_SM58 R568
R20 N26 AW19 6 CFG12 1 2 @ 2.2K_0402_5%
VCC_NCTF59 VCC59 VCC_SM59
10U_0805_10V4Z
10U_0805_10V4Z
AD19 AE27 L26 AV19 1
VCC_NCTF60 VSS_NCTF0 VCC60 VCC_SM60 R569
1 V19 AE26 N25
VCC61 VCC_SM61
AU19 1 1 6 CFG13 1 2 @ 2.2K_0402_5%
VCC_NCTF61 VSS_NCTF1 + C773
U19 AE25 M25 AT19
VCC_NCTF62 VSS_NCTF2 VCC62 VCC_SM62
C772
C770 +
C771
T19 AE24 L25 AR19 R570 1 2 @ 2.2K_0402_5%
VCC_NCTF63 VSS_NCTF3 VCC63 VCC_SM63 6 CFG16
@ AD18 AE23 P24 AP19 330U_D2E_2.5VM_R9
220U_D2_2VMR15 VCC_NCTF64 VSS_NCTF4 VCC64 VCC_SM64 2 2 2
AC18 AE22 N24 AK19
2 VCC_NCTF65 VSS_NCTF5 VCC65 VCC_SM65
AB18 AE21 M24 AJ19
VCC_NCTF66 VSS_NCTF6 VCC66 VCC_SM66
AA18 AE20 AB23 AJ18
VCC_NCTF67 VSS_NCTF7 VCC67 VCC_SM67
Y18 AE19 AA23 AJ17
VCC_NCTF68 VSS_NCTF8 VCC68 VCC_SM68
W18 AE18 Y23 VCC69 AH17
VCC_NCTF69 VSS_NCTF9 VCC_SM69
V18 AC17 P23 AJ16
B VCC_NCTF70 VSS_NCTF10 VCC70 VCC_SM70 +3VS B
U18 Y17 N23 VCC71 AH16
VCC_NCTF71 VSS_NCTF11 VCC_SM71
T18 U17 M23 VCC72 BA15
+1.05VS VCC_NCTF72 VSS_NCTF12 VCC_SM72 R571
L23 AY15 6 CFG18 1 2 @ 1K_0402_5%
VCC73 VCC_SM73
0.47U_0603_16V4Z
AC22 AW15
+1.8V VCC74 VCC_SM74 R572
M19 AB22
VCC75 VCC_SM75
AV15 6 CFG19 1 2 @ 1K_0402_5%
VCC100
L19 AR6 Y22 AU15 1
VCC101 VCC_SM100 VCC76 VCC_SM76
C774
N18 AP6 W22 AT15 R573 1 2 @ 1K_0402_5%
VCC102 VCC_SM101 VCC77 VCC_SM77 6 CFG20
M18 AN6 P22 AR15
VCC103 VCC_SM102 VCC78 VCC_SM78
L18 AL6 N22 AJ15
VCC104 VCC_SM103 VCC79 VCC_SM79 2
P17 AK6 M22 VCC80 AJ14
VCC105 VCC_SM104 VCC_SM80
N17 AJ6 L22 VCC81 AJ13
VCC106 VCC_SM105 VCC_SM81
M17 AV1 MCH_AV1 AC21
VCC82 VCC_SM82 AH13
VCC107 VCC_SM106
N16 AJ1 MCH_AJ1 AA21 VCC83 VCC_SM83 AK12
VCC108 VCC_SM107
M16 W21 AJ12
VCC109 VCC84 VCC_SM84
0.47U_0603_16V4Z
0.47U_0603_16V4Z
C776
CALISTOGA_FCBGA1466~D
A A
PM@
5
Dr-Bios.com 4
Security Classification
Issued Date 2007/1/15
Compal Secret Data
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3 2
2007/10/4 Title
Size
B
Date:
Compal Electronics, Inc.
Document Number
Calistoga (5/6)
JDW50/JDYL70 M/B LA-3771P
Monday, April 16, 2007
1
Sheet 10 of 44
Rev
0.2
5 4 3 2 1
U41I U41J
AC41 AE34 AN21 AG10
VSS0 VSS100 VSS200 VSS280
AA41 VSS1 VSS101 AC34 AL21 AC10
VSS201 VSS281
W41 C34 AB21 W10
VSS2 VSS102 VSS202 VSS282
T41 VSS3 VSS103 AW33 Y21 U10
VSS203 VSS283
P41 AV33 P21 BA9
VSS4 VSS104 VSS204 VSS284
M41 VSS5 VSS105 AR33 K21 AW9
D VSS205 VSS285 D
J41 VSS6 VSS106 AE33 J21 AR9
VSS206 VSS286
F41 VSS7 VSS107 AB33 H21 AH9
VSS207 VSS287
AV40 VSS8 VSS108 Y33 C21 AB9
VSS208 VSS288
AP40 V33 AW20 Y9
VSS9 VSS109 VSS209 VSS289
AN40 T33 AR20 R9
VSS10 VSS110 VSS210 VSS290
AK40 VSS11 VSS111 R33 AM20 G9
VSS211 VSS292
AJ40 VSS12 VSS112
M33 AA20 E9
VSS212 VSS291
AH40 VSS13 VSS113 H33 K20 A9
VSS213 VSS293
AG40 VSS14 VSS114 G33 B20 AG8
VSS214 VSS294
AF40 F33 A20 AD8
VSS15 VSS115 VSS215 VSS295
AE40 VSS16 VSS116 D33 AN19 AA8
VSS216 VSS296
B40 VSS17 VSS117
B33 AC19 U8
VSS217 VSS297
AY39 VSS18 VSS118 AH32 W19 K8
VSS218 VSS298
AW39 AG32 K19 C8
VSS19 VSS119 VSS219 VSS299
AV39 VSS20 VSS120
AF32 G19 BA7
VSS220 VSS300
AR39 AE32 C19 AV7
VSS21 VSS121 VSS221 VSS301
AN39 AC32 AH18 AP7
VSS22 VSS122 VSS222 VSS302
AJ39 AB32 P18 AL7
VSS23 VSS123 VSS223 VSS303
AC39 VSS24 VSS124 G32 H18 AJ7
VSS224 VSS304
AB39 B32 D18 AH7
VSS25 VSS125 VSS225 VSS305
AA39 VSS26 VSS126 AY31 A18 AF7
VSS226 VSS306
Y39 AV31 AY17 AC7
VSS27 VSS127 VSS227 VSS307
W39 VSS28 VSS128 AN31 AR17 R7
VSS228 VSS308
V39
T39
VSS29
VSS30
VSS129
VSS130
AJ31
AG31
AP17
AM17
VSS229
VSS230
P O W E R VSS309
VSS310
G7
D7
R39 AB31 AK17 AG6
VSS31 VSS131 VSS231 VSS311
P39 Y31 AV16 AD6
VSS32 VSS132 VSS232 VSS312
N39 VSS33 VSS133
AB30 AN16 AB6
VSS233 VSS313
M39
L39
VSS34
VSS35
P O W E R VSS134
VSS135
E30
AT29
AL16
J16
VSS234
VSS235
VSS314
VSS315
Y6
U6
J39 VSS36 VSS136 AN29 F16 N6
VSS236 VSS316
H39 VSS37 VSS137 AB29 C16 K6
C VSS237 VSS317 C
G39 VSS38 VSS138 T29 AN15 H6
VSS238 VSS318
F39 N29 AM15 B6
VSS39 VSS139 VSS239 VSS319
D39 VSS40 VSS140 K29 AK15 AV5
VSS240 VSS320
AT38 VSS41 VSS141
G29 N15 AF5
VSS241 VSS321
AM38 VSS42 VSS142 E29 M15 AD5
VSS242 VSS322
AH38 VSS143
C29 L15 AY4
VSS43 VSS243 VSS323
AG38 VSS144 B29 B15 AR4
VSS44 VSS244 VSS324
AF38 A29 A15 AP4
VSS45 VSS145 VSS245 VSS325
AE38 VSS146 BA28 BA14 AL4
VSS46 VSS246 VSS326
C38 AW28 AT14 AJ4
VSS47 VSS147 VSS247 VSS327
AK37 VSS148 AU28 AK14 Y4
VSS48 VSS248 VSS328
AH37 AP28 AD14 U4
VSS49 VSS149 VSS249 VSS329
AB37 VSS150 AM28 AA14 R4
VSS50 VSS250 VSS330
AA37 AD28 U14 J4
VSS51 VSS151 VSS251 VSS331
Y37 VSS152 AC28 K14 F4
VSS52 VSS252 VSS332
W37 VSS153 W28 H14 C4
VSS53 VSS253 VSS333
V37 J28 E14 AY3
VSS54 VSS154 VSS254 VSS334
T37 VSS155 E28 AV13 AW3
VSS55 VSS255 VSS335
R37 AP27 AR13 AV3
VSS56 VSS156 VSS256 VSS336
P37 AM27 AN13 AL3
VSS57 VSS157 VSS257 VSS337
N37 AK27 AM13 AH3
VSS58 VSS158 VSS258 VSS338
M37 J27 AL13 AG3
VSS59 VSS159 VSS259 VSS339
L37 G27 AG13 AF3
VSS60 VSS160 VSS260 VSS340
J37 F27 P13 AD3
VSS61 VSS161 VSS261 VSS341
H37 VSS162 C27 F13 AC3
VSS62 VSS262 VSS342
G37 B27 D13 AA3
VSS63 VSS163 VSS265 VSS343
F37 VSS164 AN26 B13 G3
VSS64 VSS264 VSS344
D37 M26 AY12 AT2
VSS65 VSS165 VSS263 VSS345
AY36 K26 AC12 AR2
VSS66 VSS166 VSS266 VSS346
AW36 F26 K12 AP2
VSS67 VSS167 VSS267 VSS347
AN36 D26 H12 AK2
VSS68 VSS168 VSS268 VSS348
AH36 AK25 E12 AJ2
B VSS69 VSS169 VSS269 VSS349 B
AG36 VSS170 P25 AD11 AD2
VSS70 VSS270 VSS350
AF36 VSS171 K25 AA11 AB2
VSS71 VSS271 VSS351
AE36 VSS172 H25 Y11 Y2
VSS72 VSS272 VSS352
AC36 E25 J11 U2
VSS73 VSS173 VSS273 VSS353
C36 D25 D11 T2
VSS74 VSS174 VSS274 VSS354
B36 A25 B11 N2
VSS75 VSS175 VSS275 VSS355
BA35 BA24 AV10 J2
VSS76 VSS176 VSS276 VSS356
AV35 AU24 AP10 H2
VSS77 VSS177 VSS277 VSS357
AR35 AL24 AL10 F2
VSS78 VSS178 VSS278 VSS358
AH35 VSS179 AW23 AJ10 C2
VSS79 VSS279 VSS359
AB35 VSS180 AT23 AL1
VSS80 VSS360
AA35 AN23
VSS81 VSS181 CALISTOGA_FCBGA1466~D
Y35 VSS182 AM23
VSS82
W35 AH23 PM@
VSS83 VSS183
V35 VSS184 AC23
VSS84
T35 VSS185 W23
VSS85
R35 K23
VSS86 VSS186
P35 J23
VSS87 VSS187
N35 F23
VSS88 VSS188
M35 VSS189 C23
VSS89
L35 AA22
VSS90 VSS190
J35 VSS191 K22
VSS91
H35 G22
VSS92 VSS192
G35 VSS193 F22
VSS93
F35 E22
VSS94 VSS194
D35 VSS195 D22
VSS95
AN34 VSS196 A22
VSS96
AK34 VSS197 BA21
VSS97
AG34 VSS198 AV21
VSS98
AF34 AR21
VSS99 VSS199
CALISTOGA_FCBGA1466~D
A A
PM@
5
Dr-Bios.com
4
Security Classification
Issued Date 2007/1/15
Compal Secret Data
Deciphered Date 2007/10/4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3 2
Title
Size
B
Date:
Compal Electronics, Inc.
Document Number
Calistoga (6/6)
JDW50/JDYL70 M/B LA-3771P
Monday, April 16, 2007
1
Sheet 11 of 44
Rev
0.2
5 4 3 2 1
JP28
1
+DIMM_VREF 1 2
VREF VSS DDRA_SDQ6 R345
3 4
DDRA_SDQ4 VSS DQ4 DDRA_SDQ0 +DIMM_VREF
5 6
DDRA_SDQ1 DQ0 DQ5 1K_0402_1%
7 DQ1 VSS 8
9 10 DDRA_SDM0
2
DDRA_SDQS0# VSS DM0 +DIMM_VREF
7 DDRA_SDQS0# DDRA_SDQS0
11 DQS0# VSS 12
DDRA_SDQ5
20mils
13 DQS0 DQ6
14
7 DDRA_SDQS0
1
15 16 DDRA_SDQ7 1 C376 1
DDRA_SDQ2 VSS DQ7 R344 C410
17 18
DDRA_SDQ3 DQ2 VSS DDRA_SDQ13
19 DQ3 DQ12 20
D DDRA_SDQ12 1K_0402_1% 2.2U_0805_10V6K 0.1U_0402_16V4Z D
21 VSS DQ13 22
DDRA_SDQ8 23 24 2 2
2
DDRA_SDQ14 DQ8 VSS DDRA_SDM1
25 DQ9 DM1 26
27 VSS VSS
28
DDRA_SDQS1# 29 30
7 DDRA_SDQS1# DQS1# CK0 DDRA_CLK0 6
DDRA_SDQS1 31 32
7 DDRA_SDQS1 DQS1 CK0# DDRA_CLK0# 6
33 34
DDRA_SDQ9 VSS VSS DDRA_SDQ11
35 DQ10 DQ14
36
DDRA_SDQ15 37 38 DDRA_SDQ10
DQ11 DQ15 DDRA_SMA[0..13]
39 40 7 DDRA_SMA[0..13]
VSS VSS
DDRA_SDQ[0..63]
7 DDRA_SDQ[0..63]
41 VSS VSS 42
DDRA_SDQ16 43 44 DDRA_SDQ20 DDRA_SDM[0..7]
DQ16 DQ20 7 DDRA_SDM[0..7] +1.8V
DDRA_SDQ17 45 46 DDRA_SDQ21
DQ17 DQ21
47 48
DDRA_SDQS2# VSS VSS R1191 0_0402_5%
49 DQS2# NC 50 2 PM_EXTTS#0 6,13
7 DDRA_SDQS2# DDRA_SDQS2 DDRA_SDM2
51 52
7 DDRA_SDQS2 DQS2 DM2
53 VSS VSS
54 1 1 1 1 1 1 1
DDRA_SDQ18 55 56 DDRA_SDQ23 C611 C605 C608 C606 C389 C400 C388
DDRA_SDQ19 DQ18 DQ22 DDRA_SDQ22
57 58
DQ19 DQ23 2.2U_0805_10V6K 2.2U_0805_10V6K 1U_0402_6.3V4Z 1U_0402_6.3V4Z
59 60
DDRA_SDQ29 VSS VSS DDRA_SDQ28 2 2 2 2 2 2 2
61 DQ24 DQ28 62
DDRA_SDQ24 63 64 DDRA_SDQ25 2.2U_0805_10V6K 2.2U_0805_10V6K 1U_0402_6.3V4Z
DQ25 DQ29
65 66
DDRA_SDM3 VSS VSS DDRA_SDQS3#
67 68
DM3 DQS3# DDRA_SDQS3 DDRA_SDQS3# 7
69 70
NC DQS3 DDRA_SDQS3 7
71 VSS VSS 72
DDRA_SDQ26 73 74 DDRA_SDQ31 +1.8V
DDRA_SDQ27 DQ26 DQ30 DDRA_SDQ30 +0.9VS
75 DQ27 DQ31 76
77 VSS VSS 78
DDRA_CKE0 79 80 DDRA_CKE1 DDRA_CKE0 1 4
C 6 DDRA_CKE0 CKE0 NC/CKE1 DDRA_CKE1 6 DDRA_SBS2# C
81 82 2 3 1 1 1 1
VDD VDD RP19 56_0404_4P2R_5% C411 C414 C417 C413
83 84
DDRA_SBS2# NC NC/A15
7 DDRA_SBS2# 85 86
BA2 NC/A14 DDRA_SMA12 0.1U_0402_16V4Z 0.1U_0402_16V4Z
87 88 1 4
DDRA_SMA12 VDD VDD DDRA_SMA11 DDRA_SMA9 2 2 2 2
89 A12 A11 90 2 3
DDRA_SMA9 91 92 DDRA_SMA7 RP20 56_0404_4P2R_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRA_SMA8 A9 A7 DDRA_SMA6
93 A6 94
A8 DDRA_SMA5
95 96 1 4
DDRA_SMA5 VDD VDD DDRA_SMA4 DDRA_SMA8
97 98 2 3
DDRA_SMA3 A5 A4 DDRA_SMA2 RP21 56_0404_4P2R_5%
99 A2 100
DDRA_SMA1 A3 DDRA_SMA0
101 A0 102
A1 DDRA_SMA1
103 104 1 4
DDRA_SMA10 VDD VDD DDRA_SBS1# DDRA_SMA3 +0.9VS
105 106 DDRA_SBS1# 7 2 3
DDRA_SBS0# A10/AP BA1 DDRA_SRAS# RP22 56_0404_4P2R_5%
7 DDRA_SBS0# 107 108 DDRA_SRAS# 7
DDRA_SWE# BA0 RAS# DDRA_SCS#0
7 DDRA_SWE# 109 S0# 110 DDRA_SCS#0 6
WE# DDRA_SMA10
111 112 1 4
DDRA_SCAS# VDD VDD DDRA_ODT0 DDRA_SBS0#
7 DDRA_SCAS# 113 114 DDRA_ODT0 6 2 3 1 1 1 1
DDRA_SCS#1 CAS# ODT0 DDRA_SMA13 RP23 56_0404_4P2R_5% C427 C404 C407 C425
6 DDRA_SCS#1 115 NC/A13 116 1
NC/S1# C403
117 118
DDRA_ODT1 VDD VDD DDRA_SWE# 0.1U_0402_16V4Z 0.1U_0402_16V4Z
6 DDRA_ODT1 119 120 1 4
NC/ODT1 NC DDRA_SCS#1 2 2 2 2 0.1U_0402_16V4Z
121 122 2 3
DDRA_SDQ37 VSS VSS DDRA_SDQ39 RP24 56_0404_4P2R_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2
123 124
DDRA_SDQ36 DQ32 DQ36 DDRA_SDQ38
125 126
DQ33 DQ37 DDRA_SCAS#
127 128 1 4
DDRA_SDQS4# VSS VSS DDRA_SDM4 DDRA_ODT1
129 130 2 3
7 DDRA_SDQS4# DDRA_SDQS4 DQS4# DM4 RP25 56_0404_4P2R_5% +0.9VS
131 132
7 DDRA_SDQS4 DQS4 VSS DDRA_SDQ34
133 DQ38 134
DDRA_SDQ35 VSS DDRA_SDQ33
135 136
DDRA_SDQ32 DQ34 DQ39
137 138
DQ35 VSS DDRA_SDQ45 DDRA_SMA11
139 140 1 4 1 1 1 1 1
DDRA_SDQ40 VSS DQ44 DDRA_SDQ43 DDRA_CKE1 C422 C405 C409 C408 C406
141 142 2 3
DDRA_SDQ44 DQ40 DQ45 RP26 56_0404_4P2R_5%
143 144
B DQ41 VSS DDRA_SDQS5# 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z B
145 DQS5# 146
DDRA_SDM5 VSS DDRA_SDQS5 DDRA_SDQS5# 7 DDRA_SMA6 2 2 2 2 2
147 DQS5 148 1 4
DM5 DDRA_SDQS5 7 DDRA_SMA7 0.1U_0402_16V4Z 0.1U_0402_16V4Z
149 VSS 150 2 3
DDRA_SDQ41 VSS DDRA_SDQ47 RP27 56_0404_4P2R_5%
151 DQ46 152
DDRA_SDQ46 DQ42 DDRA_SDQ42
153 154
DQ43 DQ47 DDRA_SMA2
155 156 1 4
DDRA_SDQ49 VSS VSS DDRA_SDQ52 DDRA_SMA4 +0.9VS
157 158 2 3
DDRA_SDQ48 DQ48 DQ52 DDRA_SDQ53 RP28 56_0404_4P2R_5%
159 160
DQ49 DQ53
161 162
VSS VSS DDRA_SBS1#
163 164 DDRA_CLK1 6 1 4
NC,TEST CK1 DDRA_SMA0
165 166 DDRA_CLK1# 6 2 3 1 1 1
DDRA_SDQS6# VSS CK1# RP29 56_0404_4P2R_5% C424 C423 C426
167 VSS 168
7 DDRA_SDQS6# DDRA_SDQS6 DQS6# DDRA_SDM6
169 DM6 170
7 DDRA_SDQS6 DQS6 DDRA_SCS#0 0.1U_0402_16V4Z 0.1U_0402_16V4Z
171 172 1 4
DDRA_SDQ54 VSS VSS DDRA_SDQ51 DDRA_SRAS# 2 2 2
173 174 2 3
DDRA_SDQ50 DQ50 DQ54 DDRA_SDQ55 RP30 56_0404_4P2R_5% 0.1U_0402_16V4Z
175 176
DQ51 DQ55
177 178
DDRA_SDQ60 VSS VSS DDRA_SDQ57 DDRA_SMA13
179 180 1 4
DDRA_SDQ61 DQ56 DQ60 DDRA_SDQ56 DDRA_ODT0
181 182 2 3
DQ57 DQ61 RP31 56_0404_4P2R_5%
183 VSS 184
DDRA_SDM7 VSS DDRA_SDQS7#
185 DQS7# 186
DM7 DDRA_SDQS7 DDRA_SDQS7# 7
187 DQS7 188
DDRA_SDQ59 VSS DDRA_SDQS7 7
189 190
DDRA_SDQ58 DQ58 VSS DDRA_SDQ62
191 DQ62 192
DQ59 DDRA_SDQ63
193 194
D_CK_SDATA VSS DQ63
13,14 D_CK_SDATA 195 196
D_CK_SCLK SDA VSS R3531
13,14 D_CK_SCLK 197 198 2 10K_0402_5%
SCL SAO R3541
+3VS 199 200 2 10K_0402_5%
VDDSPD SA1
203 GND GND 204
FOX_AS0A426-M2RN-7F
CONN@
A +3VS A
Dr-Bios.com
1 1
C607 C402
0.1U_0402_16V4Z
2
2.2U_0805_10V6K 2 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/1/15 Deciphered Date 2007/12/25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII-SODIMM0
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JDW50/JDYL70 M/B LA-3771P
Date: Monday, April 16, 2007 Sheet 12 of 44
5 4 3 2 1
A B C D E
+DIMM_VREF +1.8V
+1.8V +1.8V
1 1
1 1 1 1 1 1
JP29 C373 C386 C519 + C556+ C420 C429 C385 C374
+DIMM_VREF 1 2
VREF VSS DDRB_SDQ5 2.2U_0805_10V6K 0.1U_0402_16V4Z 0.1U_0402_16V4Z
3 VSS DQ4 4
DDRB_SDQ0 5 6 DDRB_SDQ4 2 2
0.1U_0402_16V4Z 2 2 2 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z
DDRB_SDQ1 DQ0 DQ5
7 DQ1 VSS 8
9 10 DDRB_SDM0 330U_D2E_2.5VM_R9 150U_D2_6.3VM
DDRB_SDQS0# VSS DM0 @
11 DQS0# VSS 12
1 7 DDRB_SDQS0# DDRB_SDQS0 DDRB_SDQ6 1
13 14
7 DDRB_SDQS0 DQS0 DQ6 DDRB_SDQ7
15 VSS DQ7 16
DDRB_SDQ2 17 18
DDRB_SDQ3 DQ2 VSS DDRB_SDQ12
19 20
21
DQ3
VSS
DQ12
DQ13
22 DDRB_SDQ13 For EMI
DDRB_SDQ8 23 24
DDRB_SDQ9 DQ8 VSS DDRB_SDM1
25 26
DQ9 DM1 +1.8V +1.8V +1.8V +1.8V
27 VSS VSS 28
DDRB_SDQS1# 29 30
7 DDRB_SDQS1# DQS1# CK0 DDRB_CLK1 6
DDRB_SDQS1 31 32
7 DDRB_SDQS1 DQS1 CK0# DDRB_CLK1# 6
33 34
DDRB_SDQ10 VSS VSS DDRB_SDQ14 DDRB_SMA[0..13]
35 DQ10 DQ14 36 7 DDRB_SMA[0..13] 1 1 1 1 1 1 1 1
DDRB_SDQ11 37 38 DDRB_SDQ15 C615 C616 C617 C618 C619 C620 C622 C621
DQ11 DQ15 DDRB_SDQ[0..63]
39 VSS VSS
40
7 DDRB_SDQ[0..63] 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRB_SDM[0..7] 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z 2
7 DDRB_SDM[0..7]
41 VSS VSS 42
DDRB_SDQ17 43 44 DDRB_SDQ21
DDRB_SDQ20 DQ16 DQ20 DDRB_SDQ16
45 DQ17 DQ21 46
47 48 0_0402_5%
DDRB_SDQS2# VSS VSS R356 1 +1.05VS +5VALW +1.5VS
49 50 2 PM_EXTTS#0 6,12
7 DDRB_SDQS2# DDRB_SDQS2 DQS2# NC DDRB_SDM2
51 52
7 DDRB_SDQS2 DQS2 DM2
53 VSS VSS 54
DDRB_SDQ18 55 56 DDRB_SDQ22
DDRB_SDQ19 DQ18 DQ22 DDRB_SDQ23
57 58
DQ19 DQ23
59 VSS VSS 60
DDRB_SDQ28 61 62 DDRB_SDQ26
DDRB_SDQ25 DQ24 DQ28 DDRB_SDQ24
63 DQ25 DQ29 64
65 66
DDRB_SDM3 VSS VSS DDRB_SDQS3# +1.8V
67 68
DM3 DQS3# DDRB_SDQS3 DDRB_SDQS3# 7 +0.9VS
69 NC DQS3 70
DDRB_SDQS3 7
71 72
2 DDRB_SDQ30 VSS VSS DDRB_SDQ29 2
73 DQ26 DQ30 74
DDRB_SDQ31 75 76 DDRB_SDQ27 DDRB_CKE0 1 4 1 1 1 1 1 1 1
DQ27 DQ31 DDRB_SBS2# C372 C369 C370 C371 C421 C419 C428
77 78 2 3
DDRB_CKE0 VSS VSS DDRB_CKE1 RP32 56_0404_4P2R_5%
6 DDRB_CKE0 79 80 DDRB_CKE1 6
CKE0 NC/CKE1 2.2U_0805_10V6K 2.2U_0805_10V6K 1U_0402_6.3V4Z 1U_0402_6.3V4Z
81 VDD VDD 82
83 84 DDRB_SMA12 1 4 2 2
2.2U_0805_10V6K 2 2
2.2U_0805_10V6K 2 2
1U_0402_6.3V4Z 2
DDRB_SBS2# NC NC/A15 DDRB_SMA9
7 DDRB_SBS2# 85 BA2 NC/A14
86 2 3
87 88 RP33 56_0404_4P2R_5%
DDRB_SMA12 VDD VDD DDRB_SMA11
89 A12 A11 90
DDRB_SMA9 91 92 DDRB_SMA7 DDRB_SMA8 1 4
DDRB_SMA8 A9 A7 DDRB_SMA6 DDRB_SMA5 +1.8V
93 A8 A6 94 2 3
95 96 RP34 56_0404_4P2R_5%
DDRB_SMA5 VDD VDD DDRB_SMA4
97 A5 A4 98
DDRB_SMA3 99 100 DDRB_SMA2 DDRB_SMA3 1 4
DDRB_SMA1 A3 A2 DDRB_SMA0 DDRB_SMA1
101 102 2 3 1 1 1 1
A1 A0 RP35 56_0404_4P2R_5% C384 C398 C375 C399
103 104
DDRB_SMA10 VDD VDD DDRB_SBS1#
105 106 DDRB_SBS1# 7
DDRB_SBS0# A10/AP BA1 DDRB_SRAS# DDRB_SMA10 0.1U_0402_16V4Z 0.1U_0402_16V4Z
7 DDRB_SBS0# 107 BA0 RAS#
108 DDRB_SRAS# 7 1 4
DDRB_SWE# DDRB_SCS#0 DDRB_SBS0# 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z 2
7 DDRB_SWE# 109 110 DDRB_SCS#0 6 2 3
WE# S0# RP36 56_0404_4P2R_5%
111 VDD VDD 112
DDRB_SCAS# 113 114 DDRB_ODT0
7 DDRB_SCAS# CAS# ODT0 DDRB_ODT0 6
DDRB_SCS#1 115 116 DDRB_SMA13 DDRB_SWE# 1 4
6 DDRB_SCS#1 NC/S1# NC/A13
117 118 DDRB_SCAS# 2 3
DDRB_ODT1 VDD VDD RP37 56_0404_4P2R_5%
6 DDRB_ODT1 119 NC/ODT1 NC
120
121 122
DDRB_SDQ32 VSS VSS DDRB_SDQ36 DDRB_SCS#1
123 124 1 4
DDRB_SDQ33 DQ32 DQ36 DDRB_SDQ37 DDRB_ODT1 +0.9VS
125 126 2 3
DQ33 DQ37 RP38 56_0404_4P2R_5%
127 VSS
128
DDRB_SDQS4# VSS DDRB_SDM4
129 130
7 DDRB_SDQS4# DDRB_SDQS4 DQS4# DM4
131 132
7 DDRB_SDQS4 DQS4 VSS DDRB_SDQ39
133 134 1 1 1 1 1
DDRB_SDQ34 VSS DQ38 DDRB_SDQ38 DDRB_SMA11 C382 C391 C392 C378 C393
135 DQ39 136 1 4
3 DDRB_SDQ35 DQ34 DDRB_CKE1 3
137 VSS 138 2 3
DQ35 DDRB_SDQ44 RP39 56_0404_4P2R_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z
139 DQ44 140
DDRB_SDQ40 VSS DDRB_SDQ45 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z
141 DQ45 142
DDRB_SDQ41 DQ40 DDRB_SMA6
143 VSS 144 1 4
DQ41 DDRB_SDQS5# DDRB_SMA7
145 146 2 3
DDRB_SDM5 VSS DQS5# DDRB_SDQS5 DDRB_SDQS5# 7 RP40 56_0404_4P2R_5%
147 148
DM5 DQS5 DDRB_SDQS5 7
149 150
DDRB_SDQ42 VSS VSS DDRB_SDQ46 DDRB_SMA2 +0.9VS
151 152 1 4
DDRB_SDQ43 DQ42 DQ46 DDRB_SDQ47 DDRB_SMA4
153 154 2 3
DQ43 DQ47 RP41 56_0404_4P2R_5%
155 VSS VSS 156
DDRB_SDQ48 157 158 DDRB_SDQ52
DDRB_SDQ49 DQ48 DQ52 DDRB_SDQ53 DDRB_SBS1#
159 160 1 4 1 1 1 1 1
DQ49 DQ53 DDRB_SMA0 C397 C396 C383 C379 C394
161 162 2 3
VSS VSS RP42 56_0404_4P2R_5%
163 164 DDRB_CLK0 6
NC,TEST CK1 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
165 VSS CK1# 166 DDRB_CLK0# 6
DDRB_SDQS6# DDRB_SCS#0 1 4 2 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z 2
167 168
7 DDRB_SDQS6# DDRB_SDQS6 DQS6# VSS DDRB_SDM6 DDRB_SRAS#
169 170 2 3
7 DDRB_SDQS6 DQS6 DM6 RP43 56_0404_4P2R_5%
171 172
DDRB_SDQ51 VSS VSS DDRB_SDQ54
173 174
DDRB_SDQ50 DQ50 DQ54 DDRB_SDQ55 DDRB_SMA13 +0.9VS
175 DQ51 DQ55 176 1 4
177 178 DDRB_ODT0 2 3
DDRB_SDQ56 VSS VSS DDRB_SDQ60 RP44 56_0404_4P2R_5%
179 180
DDRB_SDQ61 DQ56 DQ60 DDRB_SDQ57
181 182
DQ57 DQ61
183 VSS VSS 184 1 1 1
DDRB_SDM7 185 186 DDRB_SDQS7# C381 C395 C380
DM7 DQS7# DDRB_SDQS7 DDRB_SDQS7# 7
187 VSS DQS7 188
DDRB_SDQ59 DDRB_SDQS7 7 0.1U_0402_16V4Z 0.1U_0402_16V4Z
189 DQ58 VSS
190
DDRB_SDQ58 191 192 DDRB_SDQ62 2 2
0.1U_0402_16V4Z 2
DQ59 DQ62 DDRB_SDQ63
193 VSS DQ63 194
D_CK_SDATA 195 196
12,14 D_CK_SDATA SDA VSS
D_CK_SCLK 197 198 1 2
12,14 D_CK_SCLK SCL SAO
+3VS 199 200 R3481 2 10K_0402_5% +3VS
4 VDDSPD SA1 R349 10K_0402_5% 4
201 202
GND GND
FOX_AS0A426-MARG-7F
Dr-Bios.com
CONN@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII-SODIMM1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JDW50/JDYL70 M/B LA-3771P
Date: Monday, April 16, 2007 Sheet 13 of 44
A B C D E
A B C D E F G H
R574
0_0805_5% 40mil
+CLK_VDD1
Clock Generator
FSLC FSLB FSLA CPU SRC PCI +CLK_VDD48 +CLK_VDDREF +3VS 1 2
CLKSEL2 CLKSEL1 CLKSEL0 MHz MHz MHz 1 1 1 1 1 1 1 1
C777 C778 C779
C780 C781 C782 C783 C784
0 0 1 133 100 33.3 10U_0805_10V4Z 0.047U_0402_16V7K 0.047U_0402_16V7K 10U_0805_10V4Z 0.047U_0402_16V7K 0.047U_0402_16V7K 0.047U_0402_16V7K 0.047U_0402_16V7K
2 2 2 2 2 2 2 2
1
14 CLK_CPU0 R581 1 2 0_0402_5% CLK_CPU_BCLK
+3VS CPUCLKT0LP CLK_CPU_BCLK 4
Y1 CLK_XTALIN 20 X1 CLK_CPU0# R582 1 CLK_CPU_BCLK#
**SEL_PCI5=1=PCICLK5 C791
CPUCLKC0LP
13 2 0_0402_5% CLK_CPU_BCLK# 4
33P_0402_50V8J 14.31818MHz_20P_1BX14318BE1A
2
1 2 CLK_REF 1 2 CLK_XTALOUT 19
R583 10K_0402_5% X2
CPUCLKT2_ITP/SRCCLKT10LP 6
CLK_48M_SD R693 1 2 12_0402_5%
23 CLK_48M_SD
CLK_ICH_48M R694 1 2 12_0402_5% CLKSEL0 41 5 CLK_MCH_BCLK 1 2
20 CLK_ICH_48M USB_48MHz/FSLA CPUCLKC2_ITP/SRCCLKC10LP
1 2 CLK_PCI0 R585 @ 49.9_0402_1%
R586 10K_0402_5% CLKSEL1 45 CLK_MCH_BCLK# 1 2
FSLB/TEST_MODE/24Mhz CLK_SRC9 R588 1 CLK_PCIE_CARD
ITP_EN/PCICLK_F0=0=SRC pair SRCCLKT9LP 3 2 0_0402_5% CLK_PCIE_CARD 27
R587 @ 49.9_0402_1%
R687 1 Dbg@ 2 33_0402_5% CLKSEL2 23 CLK_CPU_BCLK 1 2
26 CLK_14M_Dbg REF0/FSLC/TEST_SEL
2 CLK_SRC9# R590 1 2 0_0402_5% CLK_PCIE_CARD# R589 @ 49.9_0402_1%
SRCCLKC9LP CLK_PCIE_CARD# 27
CLK_CPU_BCLK# 1 2
1 2 CLK_PCI4 26 CLK_PCI_Dbg
R688 1 Dbg@ 2 33_0402_5% CLK_PCI4 34 PCICLK4/FCTSEL1 CLKREQ9# 72 EXP_CLKREQ# 27
R591 @ 49.9_0402_1%
2 R592 10K_0402_5% R593 1 2
2 10K_0402_5% +3VS
33 70
SEL_48M/PCICLK3 SRCCLKT8LP
CLK_PCI_card R594 1 2 33_0402_5% CLK_PCI2 32 69
23 CLK_PCI_card SEL_24M/PCICLK2 SRCCLKC8LP CLK_PCIE_VGA 1 2
CLK_PCI_LPC R596 1 2 33_0402_5% CLK_PCI1 27 71 R595 @ 49.9_0402_1%
28 CLK_PCI_LPC SEL_PCI6/PCICLK1 CLKREQ8# CLK_PCIE_VGA# 1 2
66 R597 @ 49.9_0402_1%
CLK_ICH_14M R598 1 CLK_REF SRCCLKT7LP
20 CLK_ICH_14M 2 33_0402_5% 22 SEL_PCI5/REF1
67
SRCCLKC7LP
CLK_DREF_96M R599 1 GM@ 2 0_0402_5% CLK_DOT 43 38
6 CLK_DREF_96M DOTT_96MHz/27MHz_NonspreadCLKREQ7#/48Mhz_1 CLK_PCIE_ICH 1 2
CLK_DREF_96M# R601 1 GM@ 2 0_0402_5% CLK_DOT# 44 63 CLK_SRC6 R602 1 2 0_0402_5% CLK_PCIE_SATA R600 @ 49.9_0402_1%
6 CLK_DREF_96M# DOTC_96MHz/27MHz_spread SRCCLKT6LP CLK_PCIE_SATA 19 CLK_PCIE_ICH# 1 2
64 CLK_SRC6# R604 1 2 0_0402_5% CLK_PCIE_SATA# R603 @ 49.9_0402_1%
SRCCLKC6LP CLK_PCIE_SATA# 19
CLK_PCI_ICH R605 1 2 33_0402_5% CLK_PCI0 37 CLK_PCIE_MINI1 1 2
18 CLK_PCI_ICH ITP_EN/PCICLK_F0
62 R606 @ 49.9_0402_1%
CLKREQ6# SATA_CLKREQ# 20
R607 1 2 10K_0402_5% +3VS CLK_PCIE_MINI1# 1 2
CLK_ENABLE# 1 R743 2 0_0402_5% CLK_ENABLE#_R 39 60 CLK_SRC5 R609 1 2 0_0402_5% CLK_PCIE_ICH R608 @ 49.9_0402_1%
42 CLK_ENABLE# VTT_PWRGD#/PD SRCCLKT5LP CLK_PCIE_ICH 20 CLK_PCIE_SATA 1 2
@ 61 CLK_SRC5# R611 1 2 0_0402_5% CLK_PCIE_ICH# R610 @ 49.9_0402_1%
SRCCLKC5LP CLK_PCIE_ICH# 20
R612 1 2 0_0402_5% CLKIREF 9 CLK_PCIE_SATA# 1 2
+3VS GND R614 1
15mil 29 2 10K_0402_5% +3VS R613 @ 49.9_0402_1%
CLKREQ5#/PCICLK6 CLK_DREF_SSC 1 2
58 CLK_SRC4 R616 1 2 0_0402_5% CLK_PCIE_LAN R615 @ 49.9_0402_1%
SRCCLKT4LP CLK_PCIE_LAN 24
1 2 CLK_ENABLE#_R D_CK_SCLK 16 CLK_DREF_SSC# 1 2
12,13 D_CK_SCLK SMBCLK
R617 10K_0402_5% 59 CLK_SRC4# R619 1 2 0_0402_5% CLK_PCIE_LAN# R618 @ 49.9_0402_1%
SRCCLKC4LP CLK_PCIE_LAN# 24
CLK_DREF_96M 1 2
57 R621 1 2 @ 10K_0402_5% +3VS R620 @ 49.9_0402_1%
D_CK_SDATA CLKREQ4# CLK_DREF_96M# 1
12,13 D_CK_SDATA 17 2
SMBDAT CLK_SRC3 R623 1 PM@ CLK_PCIE_VGA
55 2 0_0402_5% CLK_PCIE_VGA 15
R622 @ 49.9_0402_1%
3 SRCCLKT3LP CLK_PCIE_CARD 1 3
2
4 56 CLK_SRC3# R625 1 PM@ 2 0_0402_5% CLK_PCIE_VGA# R624 @ 49.9_0402_1%
+3VS GNDSRC SRCCLKC3LP CLK_PCIE_VGA# 15 CLK_PCIE_CARD# 1 2
R629 15 28 CLK_PCI5 R627 1 2 @ 10K_0402_5% R626 @ 49.9_0402_1%
GNDCPU CLKREQ3#/PCICLK5 +3VS
4.7K_0402_5% CLK_MCH_3GPLL 1 2
2
2 +3VS 21 52 CLK_MCH_3GPLL 6
GNDREF SRCCLKT2LP CLK_MCH_3GPLL# 1
VGATE 6,20,42 2
1 3 D_CK_SDATA 31 53 CLK_SRC2# R632 1 2 0_0402_5% CLK_MCH_3GPLL# R631 @ 49.9_0402_1%
20,24,26,27 ICH_SMBDATA GNDPCI SRCCLKC2LP CLK_MCH_3GPLL# 6 CLK_PCIE_LAN 1 2
D
1 2 +3VS 46 MINI1_CLKREQ# 26
2N7002_SOT23 CLKREQ1# R639 1
73
THRM_PAD 2 10K_0402_5% +3VS
1 3 D_CK_SCLK 74 47 CLK_SRC0 R640 1 GM@ 2 0_0402_5% CLK_DREF_SSC
20,24,26,27 ICH_SMBCLK THRM_PAD LCD100/96/SRC0_TLP CLK_DREF_SSC 6
75
D
ICS9LPR325AKLFT_MLF72
+1.05VS +1.05VS +1.05VS
2
2
2
1
1
Dr-Bios.com
CPU_BSEL1 5 CPU_BSEL2 5
1 2 1 2 CPU_BSEL0 5 R650 R652 R653 R654
R655 R651 @ 0_0402_5% 0_0402_5% @ 0_0402_5% 0_0402_5%
@ 1K_0402_5% 0_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Clock Generator
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JDW50/JDYL70 M/B LA-3771P
Date: Monday, April 16, 2007 Sheet 14 of 44
A B C D E F G H
5 4 3 2 1
PCIE_MTX_C_GRX_N[0..15]
8 PCIE_MTX_C_GRX_N[0..15]
PCIE_MTX_C_GRX_P[0..15]
8 PCIE_MTX_C_GRX_P[0..15]
PCIE_GTX_C_MRX_N[0..15]
8 PCIE_GTX_C_MRX_N[0..15]
D PCIE_GTX_C_MRX_P[0..15] D
8 PCIE_GTX_C_MRX_P[0..15]
JP19A JP19B
2
+MXM_B+ +2.5VS +5VS
G
160mil(4A) L44 2 1 1 3 D_EC_SMB_DA1
B+ 28,29,38 EC_SMB_DA1
KC FBM-L11-201209-221LMAT_0805
S
PM@ 2 160mil(4A) 1 1 Q46
L43 2 1 C525 C471 C520 PM@ 2N7002_SOT23
KC FBM-L11-201209-221LMAT_0805
2
PM@ 0.1U_0402_16V4Z
G
1 1
C526 C527 1
0.1U_0603_25V7K PM@ 2 2
PM@ 0.1U_0402_16V4Z 1 3 D_EC_SMB_CK1
28,29,38 EC_SMB_CK1
680P_0603_50V7K 68P_0402_50V8J PM@
S
A 2 2 A
PM@ Q47
Dr-Bios.com
2N7002_SOT23
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MXM Connector
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JDW50/JDYL70 M/B LA-3771P
Date: Monday, April 16, 2007 Sheet 15 of 44
5 4 3 2 1
5 4 3 2 1
TXOUT0- 1 4 VGA_TXOUT0-
VGA_TXOUT0- 15
TXOUT0+ 2 3 VGA_TXOUT0+
LCD POWER CIRCUIT TXOUT1-
RP4
1 4
PM@ 0_0404_4P2R_5%
VGA_TXOUT1-
VGA_TXOUT0+ 15
1
1 TXCLK+ 2 3 VGA_TXCLK+
VGA_TXCLK+ 15
R11 R10 C19 RP10 PM@ 0_0404_4P2R_5%
300_0603_5% 100K_0402_5% TZOUT0- 1 4 VGA_TZOUT0-
D VGA_TZOUT0- 15 D
4.7U_0805_10V4Z TZOUT0+ 2 3 VGA_TZOUT0+
2 VGA_TZOUT0+ 15
RP12 PM@ 0_0404_4P2R_5%
1 2
2
TZOUT1- 1 4 VGA_TZOUT1-
VGA_TZOUT1- 15
3
D S
TZOUT1+ VGA_TZOUT1+
G 2 3 VGA_TZOUT1+ 15
Q2 2 2 1 2 Q1 RP14 PM@ 0_0404_4P2R_5%
2N7002_SOT23 G R9 1K_0402_5% AO3413_SOT23-3 TZOUT2- 1 4 VGA_TZOUT2-
TZOUT2+ VGA_TZOUT2+ VGA_TZOUT2- 15
S 1
D 2 3 VGA_TZOUT2+ 15
1
C16 +LCDVDD RP16 PM@ 0_0404_4P2R_5%
W=60mils TZCLK- 1 4 VGA_TZCLK-
VGA_TZCLK- 15
1
GM@ D 0.047U_0402_16V7K TZCLK+ VGA_TZCLK+
2 3 VGA_TZCLK+ 15
R14 1 2 0_0402_5% Q3 2 RP18 PM@ 0_0404_4P2R_5%
8 GMCH_ENVDD 2
PM@ G 2N7002_SOT23 1 1
R13 1 2 0_0402_5% S C17 C10
15 ENVDD
3
1
4.7U_0805_10V4Z 0.1U_0402_16V4Z I2CC_SCL 1 4 GMCH_LCD_CLK GMCH_LCD_CLK 8
R12 2 2 I2CC_SDA 2 3 GMCH_LCD_DATA GMCH_LCD_DATA 8
100K_0402_5% RP2 GM@ 0_0404_4P2R_5%
2
TXOUT0- 2 3 GMCH_TXOUT0-
+3VS TXOUT0+ GMCH_TXOUT0+ GMCH_TXOUT0- 8
1 4 GMCH_TXOUT0+ 8
RP3 GM@ 0_0404_4P2R_5%
TXOUT1- 2 3 GMCH_TXOUT1-
GMCH_TXOUT1- 8
1
TXOUT1+ 1 4 GMCH_TXOUT1+
GMCH_TXOUT1+ 8
R8 DAC_BRIG 1 2 RP5 GM@ 0_0404_4P2R_5%
C9 220P_0402_50V7K TXOUT2- 2 3 GMCH_TXOUT2-
INVTPWM TXOUT2+ GMCH_TXOUT2+ GMCH_TXOUT2- 8
4.7K_0402_5% 1 2 1 4 GMCH_TXOUT2+ 8
D4 C15 220P_0402_50V7K RP7 GM@ 0_0404_4P2R_5%
2
GMCH_TZOUT2- 8
TZOUT2+ 1 4 GMCH_TZOUT2+
GMCH_TZOUT2+ 8
JP1 RP15 GM@ 0_0404_4P2R_5%
42 41 DAC_BRIG TZCLK- 2 3 GMCH_TZCLK-
GND GND DAC_BRIG 28 TZCLK+ GMCH_TZCLK+ GMCH_TZCLK- 8
+INVPWR_B+ 40 40 39 39 1 4 GMCH_TZCLK+ 8
38 37 INVTPWM R7 1 2 0_0402_5% RP17 GM@ 0_0404_4P2R_5%
38 37 INVT_PWM 28
+3VS 36 35 DISPOFF#
I2CC_SCL 36 35
15 I2CC_SCL 34 34 33
33 +LCDVDD
I2CC_SDA 32 31
15 I2CC_SDA 32 31
TZOUT0-
30 30 29
29 W=60mils W=40mils
28 27
TZOUT0+ 28 27 TXOUT0- +DVI_VCC
26 26 25 25
24 23 TXOUT0+ F2 D7
TZOUT1+ 24 23
22 21 1 2 1 2 +5VS
TZOUT1- 22 21 TXOUT1-
20 19 1
20 19 TXOUT1+ 1.1A_6VDC_FUSE RB411DT146_SOT23-3
18 18 17
17
TZOUT2+ 16 15 C23 DVI@ DVI@
TZOUT2- 16 15 TXOUT2+ 0.1U_0402_16V4Z
14 13
14 13 TXOUT2- 2 DVI@
12 11
TZCLK-
TZCLK+
10
8
12
10
11
9 9
7 TXCLK- R501 1 2 180_0402_1%
DVI-D Connector
0_0603_5% 8 7 TXCLK+ @ DVI_TXD0- +3VS
6 5 15 VGA_DVI_TXD0- 1 4 +DVI_VCC
R3 USB20_N3_R 6 5 DVI_TXD0+ JP15
20 USB20_N3 1 2 4 3 15 VGA_DVI_TXD0+ 2 3
4 3
1
1
R4 1 2 USB20_P3_R 2 1 RP45 0_0404_4P2R_5% 17 14
20 USB20_P3 2 1 +3VS TMDS_DATA0- +5V
0_0603_5% DVI@ 18 R17 R18
ACES_88242-4001 R502 1 TMDS_DATA0+ 4.7K_0402_5% 4.7K_0402_5%
2 180_0402_1%
2
B CONN@ @ DVI_TXD1- DVI@ DVI@ B
G
15 VGA_DVI_TXD1- 2 3 9 TMDS_DATA1-
1 4 DVI_TXD1+ 10
2
15 VGA_DVI_TXD1+
2
RP1 0_0404_4P2R_5% TMDS_DATA1+
1 3 VGA_DVI_SCLK 15
DVI@ 1
S
DVI_TXD2- TMDS_DATA2- Q35
15 VGA_DVI_TXD2- 2 3 2 6
TMDS_DATA2+ DDC_CLOCK
2
DVI_TXD2+ 2N7002_SOT23
G
15 VGA_DVI_TXD2+ 1 4
RP46 0_0404_4P2R_5% 12 DVI@
DVI@ TMDS_DATA3-
1 2 13 7 1 3 VGA_DVI_SDATA 15
R503 180_0402_1% TMDS_DATA3+ DDC_DATA
S
+3VS @ 4 Q36
TMDS_DATA4- 2N7002_SOT23
5 TMDS_DATA4+ DVI@
1
U48 20 R360
TMDS_DATA5- DVI_DET
21 16 1 2
P
NC
1
@ DVI@
G
1 4 DVI_TXC+ 23 R361
15 VGA_DVI_TXC+ DVI_TXC- TMDS_Clock+
NC7SZ14P5X_NL_SC70-5 2 3 24 D20
3
15 VGA_DVI_TXC- TMDS_Clock-
@ RP47 0_0404_4P2R_5% 100K_0402_5% SKS10-04AT_TSMA
DVI@ 3 DVI@ @
2
TMDS_DATA2/4 shield
11
TMDS_DATA1/3 shield
Optional for ATI M66M/M7x 25 Shield TMDS_DATA0/5 shield 19
2
G
R746 26 22
Shield TMDS_Clock shield
27 Shield
+3VS 1 2 INVTPWM 1 3 28
Shield
31
D
10K_0402_5% Shield
32
@ Shield
@ Q56
2N7002_SOT23 For GMCH DPST 8 Analog VSYNC GND 15
SUYIN_070939FR024S531PL
A CONN@ A
+INVPWR_B+ +LCDVDD
+3VS
Dr-Bios.com
L31 2 1 B+
W=40mils KC FBM-L11-201209-221LMAT_0805
1 1 1
L29 2 1 C18 C14 C8
KC FBM-L11-201209-221LMAT_0805
1 1 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z Security Classification Compal Secret Data Compal Electronics, Inc.
C432 C433 2 2 2
Issued Date 2007/1/15 Deciphered Date 2007/12/25 Title
680P_0603_50V7K 68P_0402_50V8J
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS & DVI Connector
2 2 Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JDW50/JDYL70 M/B LA-3771P
Date: Monday, April 16, 2007 Sheet 16 of 44
5 4 3 2 1
A B C D E
CRT Connector D3 D2 D1
W=40mils
@ @ @ +5VS +R_CRT_VCC +CRT_VCC
DAN217_SC59 DAN217_SC59 DAN217_SC59
D19 F1 W=40mils
1
2 1 1 2
RB411DT146_SOT23-3 1.1A_6VDC_FUSE
1
+2.5VS @ 2 1 R685
0_0603_5% C430
3
+3VS @ 2 1 R686 0.1U_0402_16V4Z
0_0603_5% 2
1 1
1
13
1
R6 R2 1 1 1 1 1 1 3
R1 9
C12 C6 C2 C7 C5 C3 14
150_0402_1% 10P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J 4
2
2 2 2 2 2 2 10 16
2
150_0402_1% 10P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J 15 17
150_0402_1% 1 5
C436
SUYIN_070549FR015S208CR
1 2 CRT_HSYNC_2 CONN@
L32 FCM1608C-121T_0603 2
change to 47pf for ATI M66/M7x CRT_DET 20
100P_0402_50V8J
1 2 CRT_VSYNC_2
2
L30 FCM1608C-121T_0603 DSUB_12
+CRT_VCC R763
1 1 1 100K_0402_5%
1 2 2 1 C434
C439 0.1U_0402_16V4Z R359 10K_0402_5% C435
1
10P_0402_50V8J 10P_0402_50V8J DSUB_15
+CRT_VCC
1
2 U18 2 2 C437 2 2
68P_0402_50V8J 1
OE#
P
4 1 CRT_VSYNC CRT_HSYNC 2 4 CRT_HSYNC_1
8 GMCH_CRT_VSYNC A Y
3 2 CRT_HSYNC C431
8 GMCH_CRT_HSYNC
G
RP48 GM@ 33_0404_4P2R_5% 68P_0402_50V8J
4 1 CRT_B SN74AHCT1G125DCKR_SC70-5 2
8 GMCH_CRT_B
3
3 2 CRT_G
8 GMCH_CRT_G +CRT_VCC
RP49 GM@ 0_0404_4P2R_5%
4 1 CRT_R
8 GMCH_CRT_R TV_COMPS
8 GMCH_TV_COMPS 3 2 1 2
RP50 GM@ 0_0404_4P2R_5% C438 0.1U_0402_16V4Z
1
4 1 TV_LUMA U19 +CRT_VCC
8 GMCH_TV_LUMA
3 2 TV_CRMA
OE#
P
8 GMCH_TV_CRMA
RP51 GM@ 0_0404_4P2R_5% CRT_VSYNC 2 4 CRT_VSYNC_1 Place closed to chipset
A Y
G
SN74AHCT1G125DCKR_SC70-5 +3VS
1
1 4 CRT_VSYNC pull-up 2.2k on GPU side
15 VGA_CRT_VSYNC
2 3 CRT_HSYNC
15 VGA_CRT_HSYNC
RP52 PM@ 0_0404_4P2R_5% R381 1 2 R391
1 4 CRT_B 4.7K_0402_5% R384 PM@ 0_0402_5% VGA_DDC_DATA 15
15 VGA_CRT_B
2 3 CRT_G
15 VGA_CRT_G
2
RP53 PM@ 0_0404_4P2R_5%
G
1 4 CRT_R 4.7K_0402_5% R398 GM@ 0_0402_5%
15 VGA_CRT_R TV_COMPS DSUB_12
15 VGA_TV_COMPS 2 3 1 3 2 1
RP54 PM@ 0_0404_4P2R_5% GMCH_CRT_DATA 8
S
1 4 TV_LUMA Q20
15 VGA_TV_LUMA
2
TV_CRMA D14 D24 D25 2N7002_SOT23
G
15 VGA_TV_CRMA 2 3
RP55 PM@ 0_0404_4P2R_5% @ @ @
DAN217_SC59 DAN217_SC59 DAN217_SC59 DSUB_15 1 3 2 1
TV-OUT Conn. R399 GMCH_CRT_CLK 8
S
1
1
1
Place closed to chipset Q21 GM@ 0_0402_5%
3 2N7002_SOT23 3
1 2 R392
PM@ 0_0402_5% VGA_DDC_CLK 15
3
2
3
+3VS
TV_LUMA 1 2
L42 FCM1608C-121T_0603 JP24
3
TV_CRMA 1 2 TV_CRMA_1 6
L40 FCM1608C-121T_0603 TV_COMPS_1 7
5
TV_COMPS 1 2 2
L18 FCM1608C-121T_0603 TV_LUMA_1 4
1
8
1
GM@ GM@
150_0402_1% 6P_0402_50V8K 6P_0402_50V8K
4 4
change to 47pf for ATI M66/M7x
P/N: SE071470J80 ( S CER CAP 47P 50V J NPO 0402 )
A
Dr-Bios.com B
Security Classification
Issued Date 2007/1/15
Compal Secret Data
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C D
2007/12/25 Title
Size
B
Date:
Document Number
Compal Electronics, Inc.
CRT & TV-OUT Connector
JDW50/JDYL70 M/B LA-3771P
Monday, April 16, 2007
E
Sheet 17 of 44
Rev
0.2
5 4 3 2 1
+3VS
23 PCI_AD[0..31] U42B
PCI_AD0 E18 D7 PCI_REQ#0
AD0 REQ0# PCI_REQ#0 23
PCI_AD1 C18 E7 PCI_GNT#0
AD1 GNT0# PCI_GNT#0 23
R143 1 2 8.2K_0402_5% PCI_DEVSEL# PCI_AD2 PCI_REQ#1
PCI_AD3
A16
F18
AD2 PCI REQ1# C16
D16
R144 1 AD3 GNT1#
D 2 8.2K_0402_5% PCI_STOP# PCI_AD4 E16 AD4 REQ2# C17 PCI_REQ#2 D
PCI_AD5 A18 D17
R139 1 AD5 GNT2#
2 8.2K_0402_5% PCI_TRDY# PCI_AD6 E17 AD6 REQ3# E13 PCI_REQ#3
PCI_AD7 A17 F13
R145 1 AD7 GNT3#
2 8.2K_0402_5% PCI_FRAME# PCI_AD8 A15 AD8 REQ4# / GPIO22 A13 PCI_REQ#4
PCI_AD9 C14 A14 PCI_GNT#4
R137 1 AD9 GNT4# / GPIO48
2 8.2K_0402_5% PCI_PLOCK# PCI_AD10 E14 AD10 GPIO1 / REQ5# C8 PCI_REQ#5
PCI_AD11 D14 D8 PCI_GNT#5
R122 1 AD11 GPIO17 / GNT5#
2 8.2K_0402_5% PCI_IRDY# PCI_AD12 B12 AD12
PCI_AD13 C13 B15 PCI_CBE#0
AD13 C/BE0# PCI_CBE#0 23
R124 1 2 8.2K_0402_5% PCI_SERR# PCI_AD14 G15 C12 PCI_CBE#1
AD14 C/BE1# PCI_CBE#1 23
PCI_AD15 G13 D12 PCI_CBE#2
AD15 C/BE2# PCI_CBE#2 23
R138 1 2 8.2K_0402_5% PCI_PERR# PCI_AD16 E12 C15 PCI_CBE#3
AD16 C/BE3# PCI_CBE#3 23
PCI_AD17 C11
PCI_AD18 AD17 PCI_IRDY#
D11 AD18 IRDY# A7 PCI_IRDY# 23
PCI_AD19 A11 E10 PCI_PAR
+3VS AD19 PAR PCI_PAR 23
PCI_AD20 A10 B18 PCI_RST#
AD20 PCIRST# PCI_RST# 23,26,27
PCI_AD21 F11 A12 PCI_DEVSEL#
AD21 DEVSEL# PCI_DEVSEL# 23
PCI_AD22 F10 C9 PCI_PERR#
AD22 PERR# PCI_PERR# 23
R109 1 2 8.2K_0402_5% PCI_PIRQA# PCI_AD23 E9 E11 PCI_PLOCK#
PCI_AD24 AD23 PLOCK# PCI_SERR#
D9 AD24 SERR# B10 PCI_SERR# 23
R120 1 2 8.2K_0402_5% PCI_PIRQB# PCI_AD25 B9 F15 PCI_STOP# Place closely pin B10
AD25 STOP# PCI_STOP# 23
PCI_AD26 A8 F14 PCI_TRDY#
AD26 TRDY# PCI_TRDY# 23
R136 1 2 8.2K_0402_5% PCI_PIRQC# PCI_AD27 A6 F16 PCI_FRAME#
AD27 FRAME# PCI_FRAME# 23
PCI_AD28 C7 CLK_PCI_ICH
R140 1 AD28
2 8.2K_0402_5% PCI_PIRQD# PCI_AD29 B6 AD29 PLTRST# C26 PLT_RST#
PLT_RST# 6,20,22,24,28
2
PCI_AD30 E6 A9 CLK_PCI_ICH
AD30 PCICLK CLK_PCI_ICH 14
R108 1 2 8.2K_0402_5% PCI_PIRQE# PCI_AD31 D6 B19 PCI_PME#
AD31 PME# PCI_PME#
R123
C R111 1 2 8.2K_0402_5% PCI_PIRQF# 10_0402_5% C
Interrupt I/F @
1
R112 1 2 8.2K_0402_5% PCI_PIRQG# PCI_PIRQA# A3 G8 PCI_PIRQE#
PIRQA# GPIO2 / PIRQE# PCI_PIRQE# 23
PCI_PIRQB# B4 F7 PCI_PIRQF# 1
R134 1 PIRQB# GPIO3 / PIRQF# C126
2 8.2K_0402_5% PCI_PIRQH# PCI_PIRQC# C5 PIRQC# GPIO4 / PIRQG# F8 PCI_PIRQG#
PCI_PIRQD# B5 G7 PCI_PIRQH# 10P_0402_50V8J
R135 1 PIRQD# GPIO5 / PIRQH#
2 8.2K_0402_5% PCI_REQ#0 @
2
R125 1
MISC
2 8.2K_0402_5% PCI_REQ#1 AE5 RSVD[1] RSVD[6] AE9
AD5 RSVD[2] RSVD[7] AG8
R146 1 2 8.2K_0402_5% PCI_REQ#2 AG4 AH8
RSVD[3] RSVD[8]
AH4 RSVD[4] RSVD[9] F21
R142 1 2 8.2K_0402_5% PCI_REQ#3 AD9 AH20
RSVD[5] MCH_SYNC# MCH_ICH_SYNC# 6
R666 1 2 8.2K_0402_5% PCI_REQ#4
ICH7_BGA652~D
R667 1 2 8.2K_0402_5% PCI_REQ#5
+3VS
5
U8
PLT_RST#
PCI_GNT#5 PCI_GNT#4 Boot BIOS Loaction 2 B
P
Y 4 PLT_RST_BUF# 26
1 A
G
0 1 SPI
1
NC7SZ08P5X_NL_SC70-5
3
R316
100K_0402_5%
1 0 PCI
2
+3VS
1 1 LPC*
5
U9
2 B
P
Y 4 2 1 PLTRST_VGA# 15
1 R321 100_0402_5%
A
G
PM@
1
NC7SZ08P5X_NL_SC70-5
3
PM@ R317
100K_0402_5%
PM@
2
A A
5
Dr-Bios.com4
Security Classification
Issued Date 2007/1/15
Compal Secret Data
Deciphered Date 2007/12/25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3 2
Title
Size
Date:
Compal Electronics, Inc.
Document Number
ICH7M(1/4)-PCI
JDW50/JDYL70 M/B LA-3771P
Monday, April 16, 2007 Sheet
1
18 of 44
Rev
0.2
5 4 3 2 1
+RTCVCC
C287
18P_0402_50V8J
2 1 ICH_RTCX1
1
R265 X1
10M_0402_5%
1
3 NC OUT 4
R263
1M_0402_5%
32.768KHZ_12.5P_MC-306 2 1 +1.05VS
2
SM_INTRUDER# NC IN U42A
C286
RTC
D 18P_0402_50V8J AB1 AA6 LPC_AD0 D
RTXC1 LAD0 LPC_AD0 26,28
2 1 ICH_RTCX2 AB2 AB5 LPC_AD1
+RTCVCC RTCX2 LAD1 LPC_AD1 26,28
AC4 LPC_AD2
LAD2 LPC_AD2 26,28
+RTCVCC 1 2 ICH_RTCRST# AA3 Y6 LPC_AD3 H_FERR# 2 1
RTCRST# LAD3 LPC_AD3 26,28
LPC
R264 R250 56_0402_5%
20K_0402_5% ICH_INTVRMEN W4 AC3
INTVRMEN LDRQ0#
1
SM_INTRUDER# Y5 AA5
R281 R754 INTRUDER# LDRQ1# / GPIO23 LPC_DRQ#1 26
332K_0402_1% 1 2 AB3 LPC_FRAME#
LFRAME# LPC_FRAME# 26,28
close to RAM door @ 10K_0603_5% W1 EE_CS
Y1 2 1 R271 10K_0402_5% +3VS
2
EE_SHCLK EC_GA20
Y2 EE_DOUT A20GATE AE22 EC_GA20 28
LAN
ICH_INTVRMEN C292 W3 AH28 H_A20M#
EE_DIN A20M# H_A20M# 4
CPU
High = Internal VR Enable 1U_0603_10V4Z
1 2 V3 LAN_CLK CPUSLP# AG27
AC-97/AZALIA
1 2 HDA_BITCLK_ICH U1 R272 2 1 10K_0402_5%
30 HDA_BITCLK_MDC +3VS
2
SATA
31 HDA_BITCLK_AUDIO 1 2 HDA_BITCLK_ICH SATA_ITX_DRX_P0 AH2 SATA0TXP IDE_DD[0..15] 22
R279 39_0402_5% AB15 IDE_DD0
SATA_DTX_C_IRX_N1 DD0 IDE_DD1
22 SATA_DTX_C_IRX_N1 AF7 SATA2RXN DD1 AE14
31 HDA_SYNC_AUDIO 1 2 HDA_SYNC_ICH 22 SATA_DTX_C_IRX_P1 SATA_DTX_C_IRX_P1 AE7 AG13 IDE_DD2
R273 39_0402_5% SATA_ITX_DRX_N1 SATA2RXP DD2 IDE_DD3
AG6 SATA2TXN DD3 AF13
SATA_ITX_DRX_P1 AH6 AD14 IDE_DD4
HDA_RST_ICH# SATA2TXP DD4 IDE_DD5
31 HDA_RST_AUDIO# 1 2 DD5 AC13
R300 39_0402_5% CLK_PCIE_SATA# AF1 AD12 IDE_DD6
14 CLK_PCIE_SATA# SATA_CLKN DD6
CLK_PCIE_SATA AE1 AC12 IDE_DD7
14 CLK_PCIE_SATA SATA_CLKP DD7
31 HDA_SDOUT_AUDIO 1 2 HDA_SDOUT_ICH AE12 IDE_DD8
R299 39_0402_5% DD8 IDE_DD9
AH10 SATARBIASN DD9 AF12 MAINPW ON 35,36,38
R242 1 2 24.9_0402_1% SATARBIAS AG10 AB13 IDE_DD10
B SATARBIASP DD10 IDE_DD11 B
10mils width less than 500mils DD11 AC14
IDE_DD12 R189
DD12 AF14
1
AH13 IDE_DD13 @ 330_0402_5% C
DD13 IDE_DD14 Q10
IDE_DIORDY AG16
IDE DD14 AH14
AC15 IDE_DD15
+1.05VS 1 2 2
B
22 IDE_DIORDY IORDY DD15 E
4.7K_0402_5% 2 1 R203 IDE_DIORDY IDE_IRQ AH16 2SC2411K_SOT23
+3VS 22 IDE_IRQ
3
IDE_DDACK# IDEIRQ @
22 IDE_DDACK# AF16 DDACK#
IDE_DIOW # AH15 AE15 IDE_DDREQ
22 IDE_DIOW # DIOW# DDREQ IDE_DDREQ 22
8.2K_0402_5% 2 1 R199 IDE_IRQ IDE_DIOR# AF15 H_THERMTRIP#
22 IDE_DIOR# DIOR#
ICH7_BGA652~D
5
Dr-Bios.com 4
Security Classification
Issued Date 2007/1/15
Compal Secret Data
Deciphered Date 2007/12/25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3 2
Title
Size
B
Date:
Compal Electronics, Inc.
ICH7M(2/4)-LAN,IDELPC,RTC
Document Number
JDW50/JDYL70 M/B LA-3771P
Monday, April 16, 2007 Sheet
1
19 of 44
Rev
0.2
5 4 3 2 1
+3V
+3VS
Place closely pin B2 Place closely pin AC1
1
10K_0402_5%
R308 1 2 SERIRQ R157 R155
2.2K_0402_5% 2.2K_0402_5% +3VS CLK_ICH_48M CLK_ICH_14M
8.2K_0402_5% U42C
R270 1 2 PM_CLKRUN# @ R284
1
ICH_SMBCLK C22 AF19 2 1
14,24,26,27 ICH_SMBCLK SMBCLK GPIO21 / SATA0GP
14,24,26,27 ICH_SMBDATA ICH_SMBDATA B22 AH18 10K_0402_5% R168 R283
SMBDATA GPIO19 / SATA1GP
SMB
SATA
GPIO
10K_0402_5% LINKALERT# A26 AH19 10_0402_5% 10_0402_5%
R658 1 ICH_VGATE ICH_SMLINK0 LINKALERT# GPIO36 / SATA2GP @ @
2 B25 AE19 2 1
ICH_SMLINK1 SMLINK0 GPIO37 / SATA3GP R65910K_0402_5%
A25
2
SMLINK1
8.2K_0402_5% 1 1
R309 1 2 EC_THERM# AC1 CLK_ICH_14M C165 C298
CLK14 CLK_ICH_14M 14
Clocks
D @ EC_SWI# CLK_ICH_48M 10P_0402_50V8J 10P_0402_50V8J D
A28 B2 CLK_ICH_48M 14
28 EC_SWI# RI# CLK48 @ @
SB_SPKR A19 2 2
31 SB_SPKR SPKR
High: CRT Plugged PAD SUS_STAT# A27 C20 SUS_CLK
T6 SUS_STAT# SUSCLK
XDP_DBRESET# A22
4 XDP_DBRESET# SYS_RST#
SYS
B24 PM_SLP_S3#
PM_BMBUSY# SLP_S3# PM_SLP_S4# PM_SLP_S3# 28
AB18 D23 PM_SLP_S4# 28
6 PM_BMBUSY# GPIO0 / BM_BUSY# SLP_S4# PM_SLP_S5#
SLP_S5# F22 PM_SLP_S5# 28
SMBALERT# B23
+3V GPIO11 / SMBALERT#
AA4 SYS_PWROK SYS_PWROK 6,30
10K_0402_5% PM_STP_PCI# PWROK
AC20 1 2
POWER MGT
14 PM_STP_PCI# GPIO18 / STPPCI#
GPIO
R313 1 2 EC_SWI# PM_STP_CPU# AF21 AC22 DPRSLPVRR2621 210K_0402_5%
14 PM_STP_CPU# GPIO20 / STPCPU# GPIO16 / DPRSLPVR PM_DPRSLPVR 6,42
R286 100_0402_5%
10K_0402_5% CP_PE# A21 C21 PM_BATLOW#
R312 1 ICH_SMLINK0 27 CP_PE# GPIO26 TP0 / BATLOW#
2
PROJECT_ID0 B21 C23 PBTN_OUT#
PROJECT_ID1 GPIO27 PWRBTN# PBTN_OUT# 28
10K_0402_5% E23
R303 1 ICH_SMLINK1 GPIO28
2 LAN_RST#
C19 PLT_RST# 6,18,22,24,28
PM_CLKRUN# AG18 No used Integrated LAN,
10K_0402_5% 28 PM_CLKRUN# GPIO32 / CLKRUN# SB_RSMRST#
Y4
R276 1 LINKALERT# RSMRST# connecting to PLT_RST#
2 AC19 GPIO33 / AZ_DOCK_EN#
IDE_HRESET# U2
22 IDE_HRESET# GPIO34 / AZ_DOCK_RST#
150_0402_1%
R311 1 2 XDP_DBRESET# ICH_PCIE_WAKE# F20 E20 EC_SCI# 100K_0402_5% +3VS
24,26,27 ICH_PCIE_WAKE# WAKE# GPIO9 EC_SCI# 28
SERIRQ AH21 A20 2 1 R278 @
26,28 SERIRQ SERIRQ GPIO10
1K_0402_5% EC_THERM# AF20 F19 R453 2 1 0_0402_5%
ICH_PCIE_WAKE# 28 EC_THERM# THRM# GPIO12
R302 1 2 E19 2 1 Q14
GPIO13 EC_LID_OUT# 28 ACIN 28,38
6,14,42 VGATE 2 1 ICH_VGATE AD22 R4 D15 MMBT3906_NL_SOT23-3
8.2K_0402_5% R267 0_0402_5% VRMPWRGD GPIO14 SB_RSMRST#
E22
C
GPIO15 EC_RSMRST# 28
R287 2 1 PM_BATLOW# R3 RB751V_SOD323
E
CRT_DET# GPIO24
AC21 GPIO6 GPIO GPIO25 D20
1
10K_0402_5% AC18 AD21
B
C SPI_CS#1 EC_SMI# GPIO7 GPIO35 / SATAREQ# SATA_CLKREQ# 14 C
R660 1 2 E21 AD20 R259 1 2
28 EC_SMI# GPIO8 GPIO38 +3V
10K_0402_5% AE20 10K_0402_5% R325 4.7K_0402_5%
R661 1 SPI_MOSI GPIO39
2
10K_0402_5% ICH7_BGA652~D
2
R662 1 2 SPI_MISO D17A
1
6
2
10K_0402_5%
R277 1 2 SMBALERT# BAV99DW-7_SOT363
@ 10K_0402_5% D17B
R269 1 2 4
3
10K_0402_5% U42D 5
R268 1 2 PROJECT_ID0 PCIE_PTX_C_IRX_N1 F26 V26 DMI_MTX_IRX_N0
27 PCIE_PTX_C_IRX_N1 PERn1 DMI0RXN DMI_MTX_IRX_N0 6
1
PCIE_PTX_C_IRX_P1 F25 V25 DMI_MTX_IRX_P0 BAV99DW-7_SOT363
27 PCIE_PTX_C_IRX_P1 PERp1 DMI0RXP DMI_MTX_IRX_P0 6
10K_0402_5% For Express Card 27 PCIE_ITX_C_PRX_N1 C175 2 1 0.1U_0402_16V7K PCIE_ITX_PRX_N1 E28 U28 DMI_ITX_MRX_N0 R329
PETn1 DMI0TXN DMI_ITX_MRX_N0 6
2
R285 1 PM_DPRSLPVR PERn2 DMI1RXN DMI_MTX_IRX_P1
2 H25 Y25 DMI_MTX_IRX_P1 6
PERp2 DMI1RXP DMI_ITX_MRX_N1
G28 W28 DMI_ITX_MRX_N1 6
PETn2 DMI1TXN DMI_ITX_MRX_P1
G27 W27 DMI_ITX_MRX_P1 6
PETp2 DMI1TXP
PCI-EXPRESS
PCIE_PTX_C_IRX_N3 K26 AB26 DMI_MTX_IRX_N2
24 PCIE_PTX_C_IRX_N3 PERn3 DMI2RXN DMI_MTX_IRX_N2 6
@ 10K_0402_5% PCIE_PTX_C_IRX_P3 K25 AB25 DMI_MTX_IRX_P2
24 PCIE_PTX_C_IRX_P3 PERp3 DMI2RXP DMI_MTX_IRX_P2 6
R663 1 2 SUS_CLK For PCIE LAN 24 PCIE_ITX_C_PRX_N3 C166 2 1 0.1U_0402_16V7K PCIE_ITX_PRX_N3 J28 AA28 DMI_ITX_MRX_N2
PETn3 DMI2TXN DMI_ITX_MRX_N2 6
24 PCIE_ITX_C_PRX_P3 C168 2 1 0.1U_0402_16V7K PCIE_ITX_PRX_P3 J27 AA27 DMI_ITX_MRX_P2
PETp3 DMI2TXP DMI_ITX_MRX_P2 6
PCIE_PTX_C_IRX_N4 M26 AD25 DMI_MTX_IRX_N3
26 PCIE_PTX_C_IRX_N4 PERn4 DMI3RXN DMI_MTX_IRX_N3 6
PCIE_PTX_C_IRX_P4 M25 AD24 DMI_MTX_IRX_P3
B 26 PCIE_PTX_C_IRX_P4 PERp4 DMI3RXP DMI_MTX_IRX_P3 6 B
For Wireless LAN 26 PCIE_ITX_C_PRX_N4 C162 2 1 0.1U_0402_16V7K PCIE_ITX_PRX_N4 L28 AC28 DMI_ITX_MRX_N3
PETn4 DMI3TXN DMI_ITX_MRX_N3 6
26 PCIE_ITX_C_PRX_P4 C158 2 1 0.1U_0402_16V7K PCIE_ITX_PRX_P4 L27 AC27 DMI_ITX_MRX_P3
PETp4 DMI3TXP DMI_ITX_MRX_P3 6
P26 AE28 CLK_PCIE_ICH#
PERn5 DMI_CLKN CLK_PCIE_ICH# 14
P25 AE27 CLK_PCIE_ICH
PERp5 DMI_CLKP CLK_PCIE_ICH 14
N28
PETn5 R213 24.9_0402_1%
N27
PETp5 DMI_ZCOMP
C25
DMI_IRCOMP
Within 500 mils
D25 1 2 +1.5VS
DMI_IRCOMP
T25
PERn6
+3V 1 2 USB_OC#1 T24 F1 USB20_N0
USB20_N0 27
R294 10K_0402_5% PERp6 USBP0N USB20_P0
R28 PETn6 USBP0P F2 USB20_P0 27 USB Conn.
1 2 USB_OC#3 R27 G4 USB20_N1
USB20_N1 27
R320 10K_0402_5% PETp6 USBP1N USB20_P1
USBP1P G3 USB20_P1 27 New Card
1 2 USB_OC#5 R2 H1 USB20_N2
USB20_N2 27
R296 10K_0402_5% SPI_CS#1 SPI_CLK USBP2N USB20_P2
P6 SPI_CS# USBP2P H2 USB20_P2 27 USB Conn.
SPI
1 2 USB_OC#7 P1 J4 USB20_N3
USB20_N3 16
R668 10K_0402_5% SPI_ARB USBP3N USB20_P3
SPI_MOSI USBP3P
J3
USB20_N4 USB20_P3 16 CMOS Camera
P5 K1 USB20_N4 26
SPI_MISO SPI_MOSI USBP4N USB20_P4
P2
SPI_MISO USBP4P
K2
USB20_N5
USB20_P4 26 USB/B
USBP5N L4 USB20_N5 27
L5 USB20_P5 Bluetooth
USBP5P USB20_P5 27
1 2 USB_OC#4 27 USB_OC#0
USB_OC#0 D3 M1 USB20_N6
USB20_N6 26
R512 10K_0402_5% USB_OC#1 OC0# USBP6N USB20_P6
+3VS 1 2 USB_OC#6 USB_OC#2
C4
D5
OC1# USB USBP6P
M2
N4 USB20_N7 USB20_P6 26 USB/B
27 USB_OC#2 OC2# USBP7N USB20_N7 26
R513 10K_0402_5% USB_OC#3 D4 N3 USB20_P7 Mini Card(WLAN)
OC3# USBP7P USB20_P7 26
USB_OC#4 E5
USB_OC#5 OC4#
C3 OC5# / GPIO29
2
USB_OC#6 A2 D2 USBRBIAS 1 2
R670 USB_OC#7 OC6# / GPIO30 USBRBIAS# R160
B3 OC7# / GPIO31 USBRBIAS D1
100K_0402_5% 22.6_0402_1%
D33
1 2 CRT_DET# ICH7_BGA652~D Within 500 mils
1
A 17 CRT_DET A
1SS355_SOD323-2
5
Dr-Bios.com 4
Security Classification
Issued Date 2007/1/15
Compal Secret Data
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3 2
2007/12/25 Title
Date:
Compal Electronics, Inc.
ICH7M(3/4)-USB,GPIO,PCIE
JDW50/JDYL70 M/B LA-3771P
Monday, April 16, 2007
1
Sheet 20 of 44
Rev
0.2
5 4 3 2 1
+1.05VS U42E
+5VALW U42F A4 P28
VSS[0] VSS[98]
A23 VSS[1] VSS[99] R1
+ICH_V5REF G10 L11 0.1U_0402_16V4Z B1 R11
V5REF[1] Vcc1_05[1] VSS[2] VSS[100]
L12 B8 R12
Vcc1_05[2] VSS[3] VSS[101]
3
S
AD17 L14 1 B11 R13
G V5REF[2] Vcc1_05[3] VSS[4] VSS[102]
34 SBPWR_EN# 2 Vcc1_05[4]
L16 1 1 B14 VSS[5] VSS[103]
R14
+1.5VS +ICH_V5REF_SUS F6 L17 C792 C794 + C795 B17 R15
Q44 V5REF_Sus Vcc1_05[5] VSS[6] VSS[104]
1
D L18 B20 R16
1
C630 AO3413_SOT23-3 0.1U_0402_16V4Z Vcc1_05[6] 220U_D2_2VMR15 VSS[7] VSS[105]
AA22 Vcc1_5_B[1] Vcc1_05[7] M11 B26 VSS[8] VSS[106] R17
2 2 2
1 AA23 Vcc1_5_B[2] Vcc1_05[8]
M18 B28
VSS[9] VSS[107] R18
0.1U_0603_25V7K 1 1 1 AB22 P11 C2 T6
D 2 C793 + C796 C797 C798 Vcc1_5_B[3] Vcc1_05[9] VSS[10] VSS[108] D
AB23 P18 C6 T12
Vcc1_5_B[4] Vcc1_05[10] 1U_0603_10V4Z VSS[11] VSS[109]
AC23 T11 C27 T13
220U_D2_2VMR15 Vcc1_5_B[5] Vcc1_05[11] VSS[12] VSS[110]
+5V AC24 T18 D10 T14
2 2 2 2 Vcc1_5_B[6] Vcc1_05[12] VSS[13] VSS[111]
AC25 U11 D13 T15
Vcc1_5_B[7] Vcc1_05[13] VSS[14] VSS[112]
AC26 U18 D18 VSS[113] T16
0.1U_0402_16V4Z 0.1U_0402_16V4Z Vcc1_5_B[8] Vcc1_05[14] VSS[15]
AD26 V11 D21 VSS[114] T17
+5VS +3VS Vcc1_5_B[9] Vcc1_05[15] VSS[16]
AD27 V12 D24 U4
Vcc1_5_B[10] Vcc1_05[16] VSS[17] VSS[115]
AD28 V14 E1 U12
Vcc1_5_B[11] Vcc1_05[17] VSS[18] VSS[116]
Place closely pin D26 Vcc1_5_B[12] Vcc1_05[18]
V16 E2 VSS[19] VSS[117] U13
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
P23 B13 H5 AA24
1
C806
C804
C805
C159 R24 C10 H28 AB4
Vcc1_5_B[38] Vcc3_3[16] VSS[46] VSS[143]
R25 D15 J1 VSS[47] VSS[144] AB6
0.1U_0402_16V4Z Vcc1_5_B[39] Vcc3_3[17] 2 2 2
R26 F9 J2 AB11
1 +3VS Vcc1_5_B[40] Vcc3_3[18] VSS[48] VSS[145]
T22 G11 J5 VSS[146]
AB14
Vcc1_5_B[41] Vcc3_3[19] VSS[49]
T23
Vcc1_5_B[42] Vcc3_3[20]
G12 2005/09/12 J24
VSS[50] VSS[147]
AB16
T26 G16 J25 AB19
Vcc1_5_B[43] Vcc3_3[21] VSS[51] VSS[148]
T27 J26 VSS[149] AB21
Vcc1_5_B[44] VSS[52]
1 T28 W5 +RTCVCC K24 VSS[150] AB24
C807 Vcc1_5_B[45] VccRTC VSS[53]
U22 K27 AB27
Vcc1_5_B[46] VSS[54] VSS[151]
1U_0402_6.3V4Z
0.1U_0402_16V4Z
U23 P7 K28 VSS[152] AB28
0.1U_0402_16V4Z Vcc1_5_B[47] VccSus3_3[1] +3V VSS[55]
V22 1 1 1 1 L13 VSS[153] AC2
2 Vcc1_5_B[48] VSS[56]
C811
C810
V23 A24 C808 C809 L15 AC5
Vcc1_5_B[49] VccSus3_3[2] VSS[57] VSS[154]
W22 C24 L24 AC9
Vcc1_5_B[50] VccSus3_3[3] 0.1U_0402_16V4Z 0.1U_0402_16V4Z VSS[58] VSS[155]
W23 D19 L25 AC11
Vcc1_5_B[51] VccSus3_3[4] 2 2 2 2 VSS[59] VSS[156]
Y22 D22 L26 AD1
Vcc1_5_B[52] VccSus3_3[5] VSS[60] VSS[157]
Place closely pin AG28 within 100mlis. Y23 Vcc1_5_B[53] VccSus3_3[6] G19 M3 VSS[61] VSS[158] AD3
M4 VSS[159] AD4
+1.5VS R664 +1.5VS_DMIPLLR +1.5VS_DMIPLL VSS[62]
B27 K3 M5 VSS[160] AD7
0.5_0603_1% R665 Vcc3_3[1] VccSus3_3[7] +3V VSS[63]
K4 1 1 M12 VSS[161] AD8
VccSus3_3[8] VSS[64]
0.01U_0402_16V7K
N12 AF2
VSS[78] VSS[175]
+3VS AH11 T7 N13 VSS[176] AF4
Vcc3_3[2] Vcc1_5_A[21] VSS[79]
<BOM Structure>
0.1U_0402_16V4Z
1 ICH7_BGA652~D
C824
Dr-Bios.com
0.1U_0402_16V4Z
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH7M(4/4)-POWER&GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JDW50/JDYL70 M/B LA-3771P
Date: Monday, April 16, 2007 Sheet 21 of 44
5 4 3 2 1
A B C D E F G H
+5VS
Placea caps. near ODD CONN.
0.1U_0402_16V4Z 10U_0805_10V4Z
1 1 1 1 1
C197 C184 C194
+3VS
C183 C192
2 2 2 2 2 IDE_DD[0..15] C239
1 19 IDE_DD[0..15] 1
1 2 0.1U_0402_16V4Z
1000P_0402_50V7K 1U_0402_6.3V4Z 10U_0805_10V4Z IDE_DA[0..2]
19 IDE_DA[0..2]
5
U7
IDE_HRESET# 2
P
20 IDE_HRESET# B
4 IDE_RST#
PLT_RST# Y
6,18,20,24,28 PLT_RST# 1 A
G
NC7SZ08P5X_NL_SC70-5
3
JP25
1 2
3 4
IDE_RST# 5 6 IDE_DD8
IDE_DD7 7 8 IDE_DD9
IDE_DD6 9 10 IDE_DD10
IDE_DD5 11 12 IDE_DD11
IDE_DD4 13 14 IDE_DD12
IDE_DD3 15 16 IDE_DD13
IDE_DD2 17 18 IDE_DD14
IDE_DD1 19 20 IDE_DD15
IDE_DD0 21 22 IDE_DDREQ
IDE_DDREQ 19
23 24 IDE_DIOR#
IDE_DIOR# 19
IDE_DIOW# 25 26
19 IDE_DIOW#
IDE_DIORDY 27 28 IDE_DDACK#
19 IDE_DIORDY IDE_IRQ IDE_DDACK# 19
19 IDE_IRQ 29 30
IDE_DA1 31 32 IDE_PDIAG# 1 2 R200 +5VS
IDE_DA0 33 34 IDE_DA2 100K_0402_5%
19 IDE_DCS1# IDE_DCS1# 35 36 IDE_DCS3# IDE_DCS3# 19
IDE_LED# 37 38
28 IDE_LED#
+5VS 39 40 +5VS
2 2
41 42
43 44
45 46
1 2 IDE_CSEL 47 48
R169 475_0402_1% 49 50
51 52 +5VS
OCTEK_CDR-50JD1 0.1U_0402_16V4Z
CONN@
+3VS
IDE_CSEL 1
C196
1
C182
1
C193
Grounding for Master (When use SATA HDD) 1
Open or High for Slaver (Normal) C245
IDE_LED# 2 2 2
+5VS 2 1
R185 100K_0402_5% 0.1U_0402_16V4Z
1000P_0402_50V7K 1U_0402_6.3V4Z 2
SATA_DTX_C_IRX_N1 1 2 SATA_DTX_IRX_N1
19 SATA_DTX_C_IRX_N1
SATAX2@ C539 3900P_0402_50V7K 8
+3VS VCC3.3
9 VCC3.3
10
VCC3.3
11
GND
12
GND
13
GND
+5VS 14 VCC5
15
VCC5
16 VCC5
17 GND
18 RESERVED
19
GND
20 VCC12
21 VCC12
22
VCC12
30
4 GND1 4
31
GND2
Dr-Bios.com
OCTEK_SAS-22CA1G
CONN@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD & ODD Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JDW50/JDYL70 M/B LA-3771P
Date: Monday, April 16, 2007 Sheet 22 of 44
A B C D E F G H
A B C D E
C874 C875 C876 C877 C878 C879 C880 C881 pin 21 XD CE#
PCI_AD31 18 125
PCI_AD30 AD31 PMPWR_VCC 2 2 2 2 2 2 2 2
19 120
PCI_AD29
PCI_AD28
20
22
AD30
AD29 MR510 VCC8
VCC7 101
81 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
PCI_AD[0..31] PCI_AD27 AD28 VCC6
18 PCI_AD[0..31] 23 AD27 VCC5 69
PCI_AD26 24 52
PCI_CBE#[0..3] PCI_AD25 AD26 VCC4
18 PCI_CBE#[0..3] 25 AD25 VCC3 42
PCI_AD24 26 29
PCI_AD23 AD24 VCC2
33 AD23 NC24 11
PCI_AD22 34 113 +3V_MCVCC
PCI_AD21 AD22 VCC_SD2
35 AD21 VCC_SD1 10 1 1
PCI_AD20 36 AD20 1 R722 43K_0402_5%
2 +3VS 0.1U_0402_16V4Z C873 C882
PCI_AD19 39 0.1U_0402_16V4Z
PCI_AD18 AD19
40 AD18 PMPWR_ENI# 127 R696 1 @ 2 0_0402_5% SD_PW REN#
PCI_AD17 2 2
46 AD17 PMPWR_OUT 126
CLK_PCI_card CLK_48M_SD PCI_AD16 47
PCI_AD15 AD16
65 AD15
1
2
PCI_AD0 91 22_0402_1% U47 40mil
8.2K_0402_5%
AD0 XMDAT4B XMDAT4B R710 43K_0402_5%
MMDAT4 99 1 2 1
GND OUT 8
112 XMDAT5B/XDW PO# xDSMW E#/SDCLK 1 R711 43K_0402_5%
2 R702 2 7
MMDAT5/SMWP# IN OUT
1
PCI_CBE#0 74 111 XMDAT6B_XDBSY# XMDAT6B_XDBSY# 1 R712 43K_0402_5%
2 3 6 C885 1 C886 1 C887 1
PCI_CBE#1 C/BE0# MMDAT6/SMBAY# XMDAT7B_XDCe# XMDAT7B_XDCe# R713 43K_0402_5% MC_PW REN# IN OUT R714
60 98 1 2 4 5
1
PCI_CBE#2 C/BE1# MMDAT7/SMCE# EN# FLG 150K_0402_5%
48 C/BE2# xd signal 1
1
PCI_CBE#3 27 C890 TPS2061DRG4_SO8 4.7U_0805_10V4Z
0.1U_0402_16V4Z @
C/BE3# xDDATA4/SDDAT3 xDDATA4/SDDAT3 R715 43K_0402_5% @ R716 2 2 2
5 1 2
2
SDDAT3/SMDATA4 xDCLE/SDDAT2 xDCLE/SDDAT2 R717 43K_0402_5% 0.1U_0402_16V4Z SDOC# 300_0603_5% 0.1U_0402_16V4Z
18 PCI_GNT#0 17 PCIGNT# SDDAT2/SMCLE 4 1 2
xDDATA0/SDDAT1 xDDATA0/SDDAT1 R718 43K_0402_5% 2
18 PCI_REQ#0 16 PCIREQ# SDDAT1/SMDATA0 9 1 2
18 PCI_PAR 59 8 xDDATA7/SDDAT0 xDDATA7/SDDAT0 1 R719 43K_0402_5%
2
1 2
PAR SDDAT0/SMDATA7 xDALE/SDCMD xDALE/SDCMD R720 43K_0402_5%
18 PCI_SERR# 58 SERR# SDCMD/SMALE 6 1 2 D
18 PCI_PERR# 57 7 1 R721 2xDSMW E#/SDCLK
PERR# SDCLK/SMWE# 22_0402_1% MSSMXD_PW REN# R699 20_0402_5%
MC_PW REN#2 Q55
18 PCI_STOP# 56 STOP# SD signal 1
SD_PW REN# 1 G 2N7002_SOT23
18 PCI_DEVSEL# 55 DEVSEL# SDCLKI 41 CLK_48M_SD 14 2
18 PCI_TRDY# 54 R701 0_0402_5% S
3
TRDY#
18 PCI_IRDY# 53 IRDY#
18 PCI_FRAME# 49 1 SD_PW REN#
FRAME# SDPWREN33#
18,26,27 PCI_RST# 37 PCIRST# SDWP/SMWPD# 121 SMW PD#/SDW P 1 R723 43K_0402_5%
2 +3VS
14 CLK_PCI_Card 38 PCICLK SDCD# 122 SDCD# 1 R724 43K_0402_5%
2
89 xDSMCD# R725 1 2 8.2K_0402_5%
PCI_AD16
R726 100_0402_5%
1 2 28
SMCD#
4 IN 1 Socket Push Type(New)
3 IDSEL 3
+3VS 2 R727 1 10K_0402_5%
GND_SD1 3
109 xD PU and PD. Close to Socket JP30
GND_SD2
27,28,30,34,40 SUSP# 2 @ R728 1 0_0402_5% 108 SUSPEND# NC23 12 +3V_MCVCC 33 XD-VCC SD-VCC 23 +3V_MCVCC
+3VS 1 2 93 RIOUT#_PME# GND7 119 MS-VCC 14
R73143K_0402_5% 97 xDDATA0/SDDAT1 8
R732 1 GND6 xDDATA1/MSBS XD-D0 xDSMW E#/SDCLK
+3VS 2 GND5 92 9 XD-D1 4 IN 1 CONN SD_CLK 24
10K_0402_5% 110 80 xDDATA2/MSDATA0 26 25 xDDATA7/SDDAT0
SDOC# MFUNC7 GND4 xDDATA3/MSDADTA3 XD-D2 SD-DAT0 xDDATA0/SDDAT1
107 MFUNC6 GND3 61 27 XD-D3 SD-DAT1 29
5IN1_LED# 106 43 xDDATA4/SDDAT3 28 10 xDCLE/SDDAT2
28 5IN1_LED# MFUNC5 GND2 XD-D4 SD-DAT2
R729 1 10K_0402_5%
2 105 21 xDDATA5/MSDADTA2 30 11 xDDATA4/SDDAT3
MFUNC4 GND1 xDDATA6/MSDATAT1 XD-D5 SD-DAT3 xDALE/SDCMD
103 MFUNC3 31 XD-D6 SD-CMD 12
102 xDDATA7/SDDAT0 32 36 SDCD#
R730 1 10K_0402_5% MFUNC2 XD-D7 SD-CD-SW
2 100 MFUNC1
94 xDSMW E#/SDCLK 6 35 SMW PD#/SDW P
18 PCI_PIRQE# MFUNC0 XD-WE SD-WP-SW
128 XMDAT5B/XDW PO# 7
NC22 xDALE/SDCMD XD-WP
NC21 124 5 XD-ALE
2 123 xDSMCD# 34 15 xDSMRE#/MSCLK
NC1 NC20 XMDAT6B_XDBSY# XD-CD MS-SCLK xDDATA2/MSDATA0
13 NC2 NC19 79 1 XD-R/B MS-DATA0 19
14 78 xDSMRE#/MSCLK 2 20 xDDATA6/MSDATAT1
NC3 NC18 XMDAT7B_XDCe# XD-RE MS-DATA1 xDDATA5/MSDADTA2
MFUN0 15 NC4 NC17 77 3 XD-CE MS-DATA2 18
30 76 xDCLE/SDDAT2 4 16 xDDATA3/MSDADTA3
NC5 NC16 XD-CLE MS-DATA3
MFUN1 w/o eerom pull low 31 NC6 NC15 75 MS-INS 17 MS_INS#
32 64 Reserve for SD,MS CLK. 13 21 xDDATA1/MSBS
NC7 NC14 4IN1 GND MS-BS
MFUN2 44 NC8 NC13 63 22 4IN1 GND
45 62 Close to Socket
NC9 NC12
MFUN3 50 NC10 NC11 51
xDSMW E#/SDCLK 1 2
MFUN4 w/o eerom pull low C888 10P_0402_50V8K 37 4IN1 GND
4 38 4IN1 GND 4
MFUN5 xDSMRE#/MSCLK 1 2
MR510QFA1_LQFP128_14X14 C889 10P_0402_50V8K TAITW _R015-312-LM
Dr-Bios.com
MFUN6 CONN@
MFUN7
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/1/15 Deciphered Date 2007/12/25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
R5C833 5IN1 & IEEE1394
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JDW50/JDYL70 M/B LA-3771P
Date: Monday, April 16, 2007 Sheet 23 of 44
A B C D E
5 4 3 2 1
+3VALW
U35 60mil
+3V_LAN +3V_LAN
+3V_LAN R23 1 2 1_1206_1%
+3V_LAN_R
60mil LAN BCM5787M
8 1 R24 1 2 1_1206_1%
D S
1 7 D 2 1 1 1 1
C24 S C28 C30 C25 C26
6 D 3 1 1 1 1
S
3
5 4 C29 C58 C89 C111
4.7U_0805_10V4Z D G 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 AO4468_SO8 4.7U_0805_10V4Z 0.1U_0402_16V4Z LAN_REGCTL25 1 2 2 LAN_REGCTL12 1 2 2
@ 2 2 2 2 4.7U_0805_10V4Z 4.7U_0805_10V4Z
0.1U_0402_16V4Z 0.1U_0402_16V4Z Q18 +2.5V_LAN Q6 +1.2V_LAN
+VSB 2 13VLAN_GATE MMJT9435T1G_SOT223 20mil MMJT9435T1G_SOT223 60mil
2
4
2
4
@ R508
200K_0402_5% 1
D C634 D
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1
D @ C447 C52 C449 C110 C31 C448 C80 C42 C91 C112 C39 C457 C450 C41 C464
2 0.1U_0603_25V7K
26,27,34 SYSON# 2
G 10U_0805_10V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
Q40 S @ 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
3
2N7002_SOT23 0.1U_0402_16V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
+3V_LAN
+3VALW 1 2 +3V_LAN
R19 0_1206_5% U3
SPROM_DOUT 1 8 SPROM_DIN
SPROM_CLK SI SO
2 SCK GND
7
3 6 +3V_LAN
SPROM_CS RESET# VCC
4 CS# WP# 5 1
C114
AT45DB011B-SU_SO8 0.1U_0402_16V4Z
U2 @ @
41 LAN_MIDI0- 2
TRD0_N LAN_MIDI0- 25
28 40 LAN_MIDI0+ Use Flash if support ASF2.0
14 CLK_PCIE_LAN# PCIE_REFCLK_N TRD0_P LAN_MIDI0+ 25
42 LAN_MIDI1-
TRD1_N LAN_MIDI1- 25
29 43 LAN_MIDI1+
14 CLK_PCIE_LAN PCIE_REFCLK_P TRD1_P LAN_MIDI2- LAN_MIDI1+ 25 +3V_LAN +3V_LAN
48 LAN_MIDI2- 25
R741 0_0402_5% TRD2_N LAN_MIDI2+
11 CLKREQ TRD2_P
47 LAN_MIDI2+ 25 +3V_LAN
28 LAN_LOWPWR 1 2 49 LAN_MIDI3- 1
TRD3_N LAN_MIDI3- 25
50 LAN_MIDI3+ C136
TRD3_P LAN_MIDI3+ 25
2
2
R71 1 2 10K_0402_5% 3 0.1U_0402_16V4Z R128 R102
C @ LOW PWR R748 0_0402_5% 2 C
4.7K_0402_5% 4.7K_0402_5%
+3VS R88 1 2 1K_0402_5% 53 2 1 2 U4
VMAIN_PRSNT LINKLED LAN_LINK# 25
1 1 8
1
1
R89 SPD100LED A0 VCC SPROM_WP
+3V_LAN 1 2 1K_0402_5% 54 67 R747 0_0402_5% 2 7
VAUX_PRSNT SPD1000LED A1 WP
+3V_LAN 2 1 LAN_PME# TRAFFICLED 66 1 2 3 6 SPROM_CLK
R514 LAN_ACTIVITY# 25 A2 SCL SPROM_DOUT
4 GND 5
100K_0402_5% SDA
59 65 SPROM_CLK @ AT24C64AN-10SU-2.7_SO8
28 ENERGY_DET ENERGY_DET SCLK(EECLK)
2
63 SPROM_DIN R78 1 2 4.7K_0402_5%
+LAN_GPHYPLLVDD SI SPROM_DOUT R740
35 64
GPHY_PLLVDD SO(EEDATA) SPROM_CS R77
62 1 2 4.7K_0402_5% 4.7K_0402_5%
PCIE_ITX_C_PRX_N3 32 CS @
20 PCIE_ITX_C_PRX_N3 PCIE_RXD_N Change to SA000003510(AT24C64)
1
PCIE_ITX_C_PRX_P3 31 Unpop if use Flash
20 PCIE_ITX_C_PRX_P3 PCIE_RXD_P LAN_REGCTL12
REGCTL12 14
C38 1 2 0.1U_0402_16V7K PCIE_PTX_IRX_N3 25 18 LAN_REGCTL25
20 PCIE_PTX_C_IRX_N3 PCIE_TXD_N REGCTL25
37 LAN_RDAC 1 2 Unpop if use Flash
C37 PCIE_PTX_IRX_P3 RDAC
20 PCIE_PTX_C_IRX_P3 1 2 0.1U_0402_16V7K 26 R62 1K for BCM5906M
PCIE_TXD_P 1.24K_0402_1%
20mil L7 20mil
23 +LAN_XTALVDD 1 2 L33
XTALVDD +2.5V_LAN
R67 1 2 0_0402_5% LAN_RESET# 10 6 +3V_LAN BLM18AG601SN1D_0603 +LAN_PCIEPLLVDD 1 2 +1.2V_LAN
6,18,20,22,28 PLT_RST# PERST VDDIO
15 1 1 1 BLM18AG601SN1D_0603
R66 1 0_0402_5% LAN_PME# VDDIO
20,26,27 ICH_PCIE_WAKE# 2 @ 12 19 C43 C452 C451
R511 1 0_0402_5% WAKE VDDIO 0.1U_0402_16V4Z
28 EC_PME# 2 56
VDDIO 0.1U_0402_16V4Z
VDDIO 61
2 2 2
LAN_SMBCLK 58 17 +2.5V_LAN 4.7U_0805_10V4Z
SMB_CLK VDDP
68
+3V_LAN LAN_SMBDATA VDDP
R130
57 SMB_DATA 20mil L34
VDDC 5 +1.2V_LAN
4.7K_0402_5% 13 +LAN_PCIEVDD 1 2 +1.2V_LAN
VDDC
2
B BLM18AG601SN1D_0603 B
G
1 2 +3V_LAN AVDD 52
XTALO 22 0.1U_0402_16V4Z
LAN_SMBCLK XTALO +LAN_AVDDL 2 2
14,20,26,27 ICH_SMBCLK 1 3 39
AVDDL
1
44 0.1U_0402_16V4Z
D
Y2 BCM5787MKML_QFN68 1 1 BLM18AG601SN1D_0603
1 2 LAN_XTALO C95 C463
1 25MHZ_20P 1 0.1U_0402_16V4Z
2 2
C35 C34 4.7U_0805_10V4Z
27P_0402_50V8J 27P_0402_50V8J
2 2
20mil L35
+LAN_GPHYPLLVDD 1 2 +1.2V_LAN
1 1 BLM18AG601SN1D_0603
C453 C456
A A
0.1U_0402_16V4Z
2 2
Dr-Bios.com
4.7U_0805_10V4Z
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN BCM5787M
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JDW50/JDYL70 M/B LA-3771P
Date: Monday, April 16, 2007 Sheet 24 of 44
5 4 3 2 1
5 4 3 2 1
LAN_LINK# LAN_ACTIVITY#
LAN BCM5787M
3
@ @
PSOT24C-LF-T7_SOT23-3 PSOT24C-LF-T7_SOT23-3
D30 D31
1
D D
1 2
C94
+2.5V_LAN 220P_0402_50V7K
JP18
+3V_LAN 2 1 12 Amber LED+
2
R70 1K_0402_5%
L12 LAN_ACTIVITY# 11
24 LAN_ACTIVITY# Amber LED-
BLM18AG601SN1D_0603 SHLD2 16
RJ45_MIDI3- 8 Guide Pin
PR4-
SHLD1 15
RJ45_MIDI3+ 7
1
T4 PR4+
1 24 RJ45_MIDI1- 6
LAN_MIDI0+ TCT1 MCT1 RJ45_MIDI0+ PR2-
24 LAN_MIDI0+ 2 TD1+ MX1+ 23
24 LAN_MIDI0- LAN_MIDI0- 3 22 RJ45_MIDI0- RJ45_MIDI2- 5
TD1- MX1- PR3-
4 TCT2 MCT2 21
24 LAN_MIDI1+ LAN_MIDI1+ 5 20 RJ45_MIDI1+ RJ45_MIDI2+ 4
LAN_MIDI1- TD2+ MX2+ RJ45_MIDI1- PR3+
24 LAN_MIDI1- 6 TD2- MX2- 19
7 18 RJ45_MIDI1+ 3
LAN_MIDI2+ TCT3 MCT3 RJ45_MIDI2+ PR2+
24 LAN_MIDI2+ 8 TD3+ MX3+ 17
24 LAN_MIDI2- LAN_MIDI2- 9 16 RJ45_MIDI2- RJ45_MIDI0- 2
C TD3- MX3- PR1- C
10 TCT4 MCT4 15 SHLD2 14
24 LAN_MIDI3+ LAN_MIDI3+ 11 14 RJ45_MIDI3+ RJ45_MIDI0+ 1
LAN_MIDI3- TD4+ MX4+ RJ45_MIDI3- PR1+
24 LAN_MIDI3- 12 TD4- MX4- 13 SHLD1 13
LAN_LINK# 10
350uH_GSL5009LF 24 LAN_LINK# Green LED-
1
1
1
R152 R148 @ @ 1 2
49.9_0402_1% 49.9_0402_1%
@ @ R101 R115 C151
2
2
2
1
1 1
C146 C134 1 1 1 1 R132 R153 RJ45_GND 1 2 LANGND 40mil
0.1U_0402_16V4Z 0.1U_0402_16V4Z C138 C121 C152 C106 75_0402_1% 75_0402_1% 1 1
@ 2 @ 2 C154
2
1000P_1206_2KV7K C108 C96
2 2 2 2 RJ45_GND 4.7U_0805_10V4Z
2 2
0.1U_0402_16V4Z 0.1U_0402_16V4Z 40mil
Pop for BCM5906 0.1U_0402_16V4Z
LAN_LINK# 1 2
C187
220P_0402_50V7K
@
A A
5
Dr-Bios.com 4
Security Classification
Issued Date 2006/12/25
Compal Secret Data
Deciphered Date 2007/12/25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3 2
Title
Size
B
Date:
Document Number
Compal Electronics, Inc.
LAN Magnetic & RJ45/RJ11
JDW50/JDYL70 M/B LA-3771P
Monday, April 16, 2007 Sheet
1
25 of 44
Rev
0.2
A B C D E
1 1 1 1 1 1 1 1
C906 C139 C480 C147 C140 C133 C137 C907
1 1
15 CLK_PCI_Dbg 14
16 SIRQ
FOX_AS0B226-S99N-7F 16 SERIRQ 20,28
For MINICARD Port80 Debug 17
53
54
55
56
CONN@ 17
18 18
19
19
20 20 close to RAM Door
@ ACES_85201-2005
+3VS 1 @ 2 +3VAux_WL
Mini Card Power Rating R756 0_0805_5%
1 2 20 mil
+3V
Power Primary Power (mA) Auxiliary Power (mA) R757 0_0805_5%
To USB/B Connector
3 JP11 3
1 1 +5VALW
2 2
3 3 +5VALW
4 4
5
5 USB20_N4
6 USB20_N4 20
6 USB20_P4
7 7 USB20_P4 20
C368
1
8
8 USB20_N6
9 9 USB20_P6
USB20_N6 20
4.7U_0805_10V4Z
10 10 USB20_P6 20 2
11 11
12 12 SYSON# 24,27,34
GND1 13
14
GND2
ACES_87213-1200G
CONN@
4 4
A
Dr-Bios.com B
Security Classification
Issued Date 2007/1/15
Compal Secret Data
Deciphered Date 2007/12/25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C D
Title
Size
B
Date:
Compal Electronics, Inc.
MINI CARD (WLAN & TV-Tuner)
Document Number
JDW50/JDYL70 M/B LA-3771P
Monday, April 16, 2007
E
Sheet 26 of 44
Rev
0.2
A B C D E
GND
20 CP_PE#
NC1
NC2
NC3
NC4
NC5
CPPE#
1
+3VS 1 18
14 CLK_PCIE_CARD# REFCLK-
R336 C357 19
14 CLK_PCIE_CARD REFCLK+
TPS2231PWPR_PWP24 10K_0402_5% 20
11
1
10
12
13
24
GND
1
0.1U_0402_16V4Z 21
2 20 PCIE_PTX_C_IRX_N1 PERn0
R338 22
20 PCIE_PTX_C_IRX_P1
2
PERp0
5
10K_0402_5% U15 23
CLKREQ1# GND
2 24
G Vcc
B 20 PCIE_ITX_C_PRX_N1 PETn0
4 EXP_CLKREQ# 14 20 PCIE_ITX_C_PRX_P1 25
2
Y PETp0
1 A
26 GND
1
D NC7SZ32P5X_NL_SC70-5 27 29
3
RCLKEN1 2 Q15 GND GND
28 GND GND 30
G 2N7002_SOT23
+3VS +3V +1.5VS S FOX_1CH4110C_LT
3
CONN@
1 1 1
C363 C362 C365
2 2
10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z
2 2 2
+USB_VCCA
W=80mils
D12
+3VALW +3VS 1 4
1 GND VCC +USB_VCCA
1 1
C173 + C164 C167
USB20_P0_R 2 3 USB20_N0_R
I/O I/O
1 150U_Y_6.3VM <BOM Structure> 470P_0402_50V7K
C592 C600 2 2 2 @ PRTR5V0U2X_SOT143
470P_0402_50V7K
0.1U_0402_16V4Z 1U_0603_10V4Z JP23
3
2
S
R733 0_0402_5% 1
G
USB20_N2 1 VCC
28 BT_ON# 1 2 2 Q32
20 USB20_N2 2 USB20_N2_R 2
D0-
D11
3 USB20_P2 1 3
R482 10K_0402_5% AO3413_SOT23-3
20 USB20_P2 2 USB20_P2_R 3 1 4 +USB_VCCA
R734 0_0402_5% D0+ GND VCC
D 4
1
GND
C597 W=40mils R736 0_0402_5% 5 USB20_P2_R 2 3 USB20_N2_R
USB20_N0 1 VCC I/O I/O
+BT_VCC 20 USB20_N0 2 USB20_N0_R 6
D1-
0.1U_0402_16V4Z USB20_P0 1 2 USB20_P0_R 7 @ PRTR5V0U2X_SOT143
20 USB20_P0 D1+
1 8
GND
1
+BT_VCC CONN@
+3V
1
D
2 Q34 80mil
1
G 2N7002_SOT23 R742 D
+5VALW
1
S 1 @ 22 @ Q51 +USB_VCCA
3
G 2N7002_SOT23 U6
10K_0402_5% S 1 8 R164
3
2
+BT_VCC IN OUT R162 1
1 4 5 2 10K_0402_5% USB_OC#0 20
C171 EN# FLG
JP12 TPS2061DRG4_SO8
1 9 4.7U_0805_10V4Z R167 1 2 10K_0402_5%
1 GND 2 USB_OC#2 20
2 2 1
3 1 C161
20 USB20_P5 3
4 C169
20 USB20_N5 4
5 0.1U_0402_16V4Z
5 24,26,34 SYSON# 2
6 0.1U_0402_16V4Z
26 WLAN_BT_DATA 6 2
26 WLAN_BT_CLK 7
4 7 4
8 10
8 GND
ACES_87213-0800G
Dr-Bios.com
CONN@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NEW CARD & USB Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JDW50/JDYL70 M/B LA-3771P
Date: Monday, April 16, 2007 Sheet 27 of 44
A B C D E
5 4 3 2 1
111
125
22
33
96
67
1 1
9
U28 2 E51RXD_P80CLK
2 E51TXD_P80DATA
3
VCC
VCC
VCC
VCC
VCC
VCC
AVCC
3
4 4
ACES_85205-0400
1 21 INVT_PW M @
19 EC_GA20 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F INVT_PW M 16
2 23 BEEP#
19 EC_KBRST# KBRST#/GPIO01 BEEP#/PWM2/GPIO10 BEEP# 31
20,26 SERIRQ 3 SERIRQ# FANPWM1/GPIO12 26 ENCODER_DIR 32
19,26 LPC_FRAME# 4 LFRAME# ACOFF/FANPWM2/GPIO13 27 ACOFF 35,37
C555 LPC_AD3 5 2 1 ECAGND 3S/4S# 1 2
19,26 LPC_AD3 LAD3
@ 22P_0402_50V8J LPC_AD2 7 PWM Output C567 0.01U_0402_16V7K R521 4.7K_0402_5%
19,26 LPC_AD2 LAD2
2 1 R447 2 1 @ 33_0402_5% LPC_AD1 8 63 BATT_TEMP
19,26 LPC_AD1 LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMP 38
LPC_AD0 BATT_OVP
19,26 LPC_AD0 10 LAD0 LPC & MISC BATT_OVP/AD1/GPIO39 64 BATT_OVP 37
ADP_I/AD2/GPIO3A 65 ADP_I 37
12 AD Input 66 AD_BID0
14 CLK_PCI_LPC PCICLK AD3/GPIO3B
6,18,20,22,24 PLT_RST# 13 PCIRST#/GPIO05 AD4/GPIO42 75 ENERGY_DET 24
37 ECRST# SELIO2#/AD5/GPIO43 76 POUT 42
EC_SCI# 20
20 EC_SCI# SCI#/GPIO0E +3VALW
+3VALW 2 1 20 PM_CLKRUN# 38 CLKRUN#/GPIO1D
R441 47K_0402_5% 68 DAC_BRIG
DAC_BRIG/DA0/GPIO3C DAC_BRIG 16
2 1 70 EN_DFAN1 65W /90W # 2 1
EN_DFAN1/DA1/GPIO3D EN_DFAN1 33
C548 0.1U_0402_16V4Z DA Output 71 IREF R449 100K_0402_5%
IREF/DA2/GPIO3E IREF 37
KSI0 55 72
KSI0/GPIO30 DA3/GPIO3F CHGSEL 37
+3VALW KSI1 56
KSI2 KSI1/GPIO31
57 KSI2/GPIO32
KSI3 58 83 EC_MUTE
KSI3/GPIO33 PSCLK1/GPIO4A EC_MUTE 32
2
2
1 2 TP_CLK KSO13 52 KSO13/GPIO2D
R448 4.7K_0402_5% KSO14 53 R465
KSO14/GPIO2E
1 2 TP_DATA KSO15 54 KSO15/GPIO2F CIR_RX/GPIO40 73 EC_RCIRRX Ra @ 100K_0402_5%
R444 4.7K_0402_5% KSO16 81 74
KSO16/GPIO48 CIR_RLC_TX/GPIO41 ENCODER_PULSE 32
KSO17 82 89 FSTCHG
FSTCHG 37
1
KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 BATT_GRN_LED# AD_BID0
BATT_CHGI_LED#/GPIO52 90 BATT_GRN_LED# 29
91 CAPS_LED#
CAPS_LED#/GPIO53 CAPS_LED# 29
2
EC_SMB_CK1 77 GPIO 92 BATT_AMB_LED# BATT_AMB_LED# 29 1
15,29,38 EC_SMB_CK1 SCL1/GPIO44 BATT_LOW_LED#/GPIO54
EC_SMB_DA1 78 93 PW R_LED PW R_LED 29 R464 C565
15,29,38 EC_SMB_DA1 SDA1/GPIO45 SUSP_LED#/GPIO55
+5VALW 4 EC_SMB_CK2
EC_SMB_CK2 79 SCL2/GPIO46 SM Bus SYSON/GPIO56 95 SYSON
SYSON 27,34,40 Rb
EC_SMB_DA2 80 121 VR_ON 18K_0402_5%
4 EC_SMB_DA2 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON 42 2
127 0.1U_0402_16V4Z
1
B EC_SMB_CK1 AC_IN/GPIO59 ACIN 20,38 B
1 2
R460 4.7K_0402_5%
1 2 EC_SMB_DA1 PM_SLP_S3# 6 100
20 PM_SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 EC_RSMRST# 20
R458 4.7K_0402_5% PM_SLP_S5# 14 101 EC_LID_OUT#
20 PM_SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_LID_OUT# 20
1 2 EC_SMB_CK2 EC_SMI# 15 102 EC_ON EC_CRY1 EC_CRY2
20 EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXO05 EC_ON 30,37
R456 4.7K_0402_5% LID_SW # 16 103
29 LID_SW # LID_SW#/GPIO0A EC_SWI#/GPXO06 EC_SW I# 20
1 2 EC_SMB_DA2 SUSP# 17 104 EC_PW ROK 1 1
23,27,30,34,40 SUSP# SUSP#/GPIO0B ICH_PWROK/GPXO06 EC_PW ROK 30
R454 4.7K_0402_5% PBTN_OUT# 18 GPO 105 BKOFF# C538 C540
20 PBTN_OUT# PBTN_OUT#/GPIO0C BKOFF#/GPXO08 BKOFF# 16
4
EC_PME# 19 GPIO 106 W L_OFF#
24 EC_PME# EC_PME#/GPIO0D WL_OFF#/GPXO09 W L_OFF# 26
25 107 MEDIA_LED# 10P_0402_50V8J 10P_0402_50V8J
IN
OUT
20 EC_THERM# EC_THERM#/GPIO11 GPXO10 MEDIA_LED# 29 2 2
FAN_SPEED1 28 108
33 FAN_SPEED1 FAN_SPEED1/FANFB1/GPIO14 GPXO11 CALIBRATE 37
BT_ON# 29
27 BT_ON# FANFB2/GPIO15
E51TXD_P80DATA 30
E51RXD_P80CLK EC_TX/GPIO16
NC
NC
31 EC_RX/GPIO17 PM_SLP_S4#/GPXID1 110 PM_SLP_S4# 20
ON/OFF 32 112 ENBKL ENBKL 8,15
30 ON/OFF ON_OFF/GPIO18 ENBKL/GPXID2
29 PW R_SUSP_LED PW R_SUSP_LED 34 114 EAPD
EAPD 31
3
NUM_LED# PWR_LED#/GPIO19 GPXID3 SATA_LED#
29 NUM_LED# 36 NUMLED#/GPIO1A GPI GPXID4 115 SATA_LED# 19
GPXID5 116 5IN1_LED# 23
117 IDE_LED# X2
GPXID6 IDE_LED# 22 32.768KHZ_12.5P_MC-306
GPXID7 118 ARCADE# 29
EC_CRY1 122
EC_CRY2 XCLK1
123 XCLK0 V18R 124
1
AGND
KB926QFA1_LQFP128_14X14 2 C892
94
113
69
11
24
35
20milStructure> L48
<BOM 0.1U_0402_16V4Z BATT_TEMP 1 2 100P_0402_50V8J
A A
ECAGND 2 1 C893
FBM-L11-160808-800LMT_0603 BATT_OVP 1 2 100P_0402_50V8J
5
Dr-Bios.com 4
Security Classification
Issued Date 2007/1/15
Compal Secret Data
Deciphered Date 2007/12/25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3 2
Title
Size
B
Date:
Compal Electronics, Inc.
Document Number
JDW50/JDYL70 M/B LA-3771P
Monday, April 16, 2007
EC ENE KB926
Sheet
1
28 of 44
Rev
0.2
+3VALW
1
C550 1 2 0.1U_0402_16V4Z
R442 @ MX25L8005M2C-15G_SOP8 +5VS 6
C551 1 TP_DATA 5
2 0.1U_0402_16V4Z 28 TP_DATA
100K_0402_5% TP_CLK 4
28 TP_CLK 3
U26
2
2
8 VCC 1
A0 1
7 2 1 1
WP A1 U27 C130 ACES_85201-0605
15,28,38 EC_SMB_CK1 6 SCL A2 3
5 4 EC_SPICS#/FSEL# 1 8 C129 CONN@
15,28,38 EC_SMB_DA1 SDA GND 28 EC_SPICS#/FSEL# CE# VDD
3 6 SPICLK R443 1 2 0_0402_5% 100P_0402_50V8J 100P_0402_50V8J
WP# SCK EC_SPICLK 28 2 2
AT24C16AN-10SI-2.7_SO8 2 1 7 5 EC_SO_SPI_SI_R R445 1 2 0_0402_5%
HOLD# SI EC_SI_SPI_SO_R R438 1 EC_SO_SPI_SI 28
R739 4 2 2 0_0402_5%
VSS SO EC_SI_SPI_SO 28 TP_DATA
1K_0402_5%
1
MX25L8005M2C-15G_SOP8
R437 +5VS TP_CLK
ENE suggestion SPI Frequency over 66MHz
3
100K_0402_5%
SST: 50MHz C149
2
MXIC: 70MHz D9
0.1U_0402_16V4Z @
ST: 40MHz PSOT24C_SOT23
1
KSI[0..7]
INT_KBD Conn. KSO[0..17]
KSI[0..7] 28
KSO[0..17] 28
JP5
(Left) KSO0
KSO1
26
25
26 G2
28
27
To BTN/B Conn.
KSO2 25 G1
24 24
KSO3 23
KSO4 23 +3VS +5VS
22 22
KSO5 21 JP2 +5VS
KSO6 21 +5VALW
20 20 1
KSO7 1
19 2
KSO8 19 2 C21
18 18 3 1 2 +3VALW
KSO9 3 R16 100K_0402_5%
17 4
KSO10 17 4 PWR_LED# 0.1U_0402_16V4Z D6
16 16 5
KSO11 5
15 15 6 ON/OFFBTN# 30 2 ARCADE# 28
KSO12 6 WL_R_LED# ARCADE_BTN# 1
14 14 7
KSO13 7 BT_LED# 51ON#
13 8 BT_LED# 27,28 3 51ON# 30,35
KSO14 13 8 PWR_SUSP_LED#
12 9
KSO15 12 9 KSO0 DAN202UT106_SC70-3
11 11 10
KSO16 10 KSI1 +3VALW
10 10 11
KSO17 11 KSI2
9 12
KSI0 9 12 KSI3
8 8 13
KSI1 13 KSI4 C22
7 14
KSI2 7 14
6 6 17 15
KSI3 G17 15 0.1U_0402_16V4Z PWR_LED# PWR_SUSP_LED#
5 18 16
KSI4 5 G18 16
4
KSI5 4 ACES_85201-16051
3 3
KSI6 2 CONN@
KSI7 2
1 1
(Right)
1
JP36 D D
ACES_85201-26051 28 PWR_LED 2 28 PWR_SUSP_LED 2
1 G G
2
CONN@ +5VS S Q4 S Q37
3
3 2N7002_SOT23 2N7002_SOT23
4 +3VALW
5 LID_SW# 28
KSO15 C74 1 2 100P_0402_50V8J KSO7 C66 1 2 100P_0402_50V8J KSI5
6 KSO0
KSO14 C73 100P_0402_50V8J KSO6 C65 100P_0402_50V8J 7 ARCADE_BTN#
1 2 1 2
8
9 NUM_LED# 28
KSO13 C72 1 2 100P_0402_50V8J KSO5 C64 1 2 100P_0402_50V8J
10 CAPS_LED# 28
MEDIA_LED# 28 @ R584
KSO12 C71 100P_0402_50V8J KSO4 C63 100P_0402_50V8J 11 WL_R_LED#
1 2 1 2 1 2 WL_LED# 28
12 0_0402_5%
ACES_85201-1205 1 2 MINI1_LED# 26
KSI0 C75 1 2 100P_0402_50V8J KSO3 C62 1 2 100P_0402_50V8J CONN@ R669 0_0402_5%
HT-297DQ/GQ_AMB/YG_0603
Dr-Bios.com
R357 LED2
300_0402_5%
+5VALW 1 2 3 YG 1 BATT_GRN_LED# BATT_GRN_LED# 28
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/1/15 Deciphered Date 2007/12/25 Title
R494
+5VALW 1 2 4 A 2 BATT_AMB_LED#
BATT_AMB_LED# 28 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BIOS, I/O Port & K/B Connector
453_0402_1% Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.2
HT-297DQ/GQ_AMB/YG_0603
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JDW50/JDYL70 M/B LA-3771P
Date: Monday, April 16, 2007 Sheet 29 of 44
A B C D E
Power Button
ON/OFF switch TOP Side HDA MDC Conn.
1 2
R749 @ 10K_0603_5%
1 2
R750 @ 10K_0603_5% +3VALW
+3V
Bottom Side
1 1
1
2
20mil C127
R434 JP17
1U_0603_10V4Z
100K_0402_5% 1 2 2
GND1 RES0 1 2
3 4 R522 0_0402_5%
19 HDA_SDOUT_MDC
1
D27 IAC_SDATA_OUT RES1
5 6 +3V
GND2 3.3V
2 ON/OFF 28 19 HDA_SYNC_MDC 7 8
ON/OFFBTN# HDA_SDIN1_MDC IAC_SYNC GND3
29 ON/OFFBTN# 1 19 HDA_SDIN1 1 2 9 10
51ON# R117 39_0402_5% IAC_SDATA_IN GND4
3 51ON# 29,35 19 HDA_RST_MDC# 11 12 HDA_BITCLK_MDC 19
IAC_RESET# IAC_BITCLK
1
DAN202UT106_SC70-3
R509
GND
GND
GND
GND
GND
GND
0_0402_5%
ACES_88018-124G
13
14
15
16
17
18
2
1
2 CONN@ 1
C545 D26 C128
Connector for MDC Rev1.5
1000P_0402_50V7K RLZ20A_LL34 22P_0402_50V8J
1 2
2
For EMI
1
D
EC_ON 2 Q27
28,37 EC_ON
G
2
S 2N7002_SOT23
R428 3
10K_0402_5%
2 2
1
Power ON Circuit
+3VS
+3VALW +3VALW
1
U14A U14B
R331 SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14
14
14
180K_0402_5%
P
P
2
1 I 2 3 4 1 2 SYS_PWROK 6,20
O I O R324 @ 0_0402_5%
G
G
1
D
2
+RTCBATT
34,39 SUSP 2 For South Bridge
7
G C300
Q13 S 1U_0805_25V4Z
3
2N7002_SOT23 1 1 2
28 EC_PWROK
R318 0_0402_5%
2
3 3
R15
+3VS 1K_0402_5%
+3VALW +3VALW
1 1
1
D5
R328
U14C U14D
14
14
SUSP# 1 2 5 6 9 8
23,27,28,34,40 SUSP# VS_ON 41
2
I O I O
2
G
G
RB751V_SOD323 C333
For +VCCP/+1.05VS BAS40-04_SOT23-3
7
+CHGRTC
7
0.1U_0402_16V4Z 1
1 C20
0.1U_0402_16V4Z
2
+3VALW
C319
+3VALW
1 2 0.1U_0402_16V4Z
Change BATT1 P/N : SP093PA0200 (Panasonic)
U14E U14F
14
14
SP093MX0000 (MAXELL)
SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14
R307 PM@ 200K_0402_5%
P
P
SUSP# 1 2 11 10 13 12 1 2
I O I O VGA_ON 15
R761 PM@ 0_0402_5%
G
G
+3VS 1 2
7
7
4 4
SUSP# 1 2
D16 RB751V_SOD323 R762 @ 0_0402_5%
2
Dr-Bios.com
PM@ C330
PM@
0.1U_0402_16V4Z
1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power OK, Reset and RTC Circuit, TP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JDW50/JDYL70 M/B LA-3771P
Date: Monday, April 16, 2007 Sheet 30 of 44
A B C D E
A B C D E F G H
+VDDA
28.7K for Module Design (VDDA = 4.702)
1
R478 +5VAMP (output = 250 mA)
10K_0402_5% 60mil U32
+5VS L49 1 2 4
VIN VOUT 5 40mil +VDDA
KC FBM-L11-201209-221LMAT_0805
2
1 1 2
DELAY SENSE or ADJ
6 1 4.85V
1 2 L50 1 2 C581 C588 R467
C591 1U_0402_6.3V4Z KC FBM-L11-201209-221LMAT_0805 7 1 30K_0402_1% C576
ERROR CNOISE
1
10U_0805_10V4Z 10U_0805_10V4Z
R483 2 2
0.1U_0402_16V4Z 8 3
2
1
1
10K_0402_5% SD GND C587
1 SI9182DH-AD_MSOP8 <BOM Structure> 1
1
2
C599 2
1 2 MONO_IN R470
1U_0402_6.3V4Z 0.1U_0402_16V4Z 10K_0402_1%
2
1
C 1 2
C604 1 R490 Q33 R485 2.4K_0402_1%
28 BEEP# 2 1 2 2
1U_0402_6.3V4Z B
560_0402_5% E 2SC2411K_SOT23
3
C609 1 R491
2 1 2
20 SB_SPKR 1U_0402_6.3V4Z
1
560_0402_5%
D29
R493 RB751V_SOD323
10K_0402_5%
2
HD Audio Codec
L51
+AVDD_HDA MBK1608121YZF_0603
20mil 0.1U_0402_16V4Z +3VS_DVDD 1 2 +3VS
L47 1 2 0.1U_0402_16V4Z
40mil
+VDDA 1 1 1
FBM-L11-160808-800LMT_0603 1 1 1 C595 C594 C593
C573 C569
C572 10U_0805_10V4Z
2 10U_0805_10V4Z <BOM Structure> 2 2 2 2
25
38
9
2 2 2 U33
0.1U_0402_16V4Z 0.1U_0402_16V4Z
DVDD_IO
AVDD1
AVDD2
DVDD
<BOM Structure>
<BOM Structure>
14 35 HP_LEFT
NC LINE_OUT_L HP_LEFT 32
15 36 HP_RIGHT
NC LINE_OUT_R HP_RIGHT 32
1 2 MIC2_C_L 16 39 AMP_LEFT
MIC2_L HP_OUT_L AMP_LEFT 32
C589 4.7U_0805_10V4Z
32 INT_MIC_R
1 2 MIC2_C_R 17 41 AMP_RIGHT
MIC2_R HP_OUT_R AMP_RIGHT 32
C586 4.7U_0805_10V4Z
LINE_L 1 2 LINE_C_L 23 45
32 LINE_L LINE1_L NC
C580 4.7U_0805_10V4Z
LINE_R 1 2 LINE_C_R 24 46
32 LINE_R LINE1_R DMIC_CLK
C577 4.7U_0805_10V4Z For EMI
18 CD_L NC
43
20
CD_R NC
44 1 2 1 2 C596
R507 0_0402_5% 22P_0402_50V8J
19
CD_GND
6 HDA_BITCLK_AUDIO 19
MIC1_L MIC1_C_L BIT_CLK
32 MIC1_L 1 2 21
C583 4.7U_0805_10V4Z MIC1_L
MIC1_R 1 2 MIC1_C_R 22 8 HDA_SDIN0_AUDIO 1 2 HDA_SDIN0 19
32 MIC1_R MIC1_R SDATA_IN
C579 4.7U_0805_10V4Z R486 33_0402_5%
MONO_IN 12 37
PCBEEP MONO_OUT WOOFER_MONO
29
LINE1_VREFO
19 HDA_RST_AUDIO# 11
3 RESET# 3
GPIO1 31
19 HDA_SYNC_AUDIO 10 SYNC 10mil
MIC1_VREFO_L 28 MIC1_VREFO_L
19 HDA_SDOUT_AUDIO 5 SDATA_OUT
32 MIC1_VREFO_R
MIC1_VREFO_R
2
GPIO0
3 GPIO3 MIC2_VREFO
30 MIC2_VREFO
R481 2 1 5.1K_0402_1% SENSE_A 13
32 HP_PLUG# SENSE A CODEC_VREF
34
SENSE B VREF
27 10mil
R484 1 2 10K_0402_1% 1
32 LINEIN_PLUG#
R479 2 1 20K_0402_1% 47 40
32 MIC_PLUG# 28 EAPD EAPD JDREF C571
1
1 2 SPDIF_R 48 SPDIFO NC 33 10U_0805_10V4Z
32 SPDIF R480 0_0402_5% R476 2
4 26 <BOM Structure>
20K_0402_1%
DVSS1 AVSS1
7 42
DVSS2 AVSS2
2
ALC268-GR_LQFP48_9X9
Sense Pin Impedance Codec Signals 1
R751
2
0_0805_5%
1
R489
2
0_0805_5%
Dr-Bios.com
20K PORT-F (PIN 16, 17)
SENSE B
10K PORT-G (PIN 43, 44)
Security Classification Compal Secret Data Compal Electronics, Inc.
5.1K PORT-H (PIN 45, 46) Issued Date 2006/12/25 Deciphered Date 2007/12/25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HD Audio Codec ALC268
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JDW50/JDYL70 M/B LA-3771P
Date: Monday, April 16, 2007 Sheet 31 of 44
A B C D E F G H
A B C D E
11
19
20
10
1
1 2 AMP_LEFT_C-1 1 2 AMP_LEFT_C U31 R28 FBMA-L11-160808-121LMT_0603 JP34
31 AMP_LEFT C584 C585 1U_0402_6.3V4Z SPKR+ SPK_R+
1 2 1
CVDD
HVDD
PVDD
PVDD
VDD
1
1
0.47U_0603_16V4Z SPKR- 1 2 SPK_R- 2
1 R477 R475 R26 FBMA-L11-160808-121LMT_0603 2 1
Right
560_0402_5% 560_0402_5% 3 22 SPKR+ 3
INR_A ROUT+ SPKR- G1
5 21 4
2
INL_A ROUT- G2
HPF Fc = 604Hz SPKL+
R473 1 2 100K_0402_5% 27 8 ACES_88266-02001
/AMP EN LOUT+ SPKL- CONN@
9
R469 1 LOUT- +5VAMP +5VAMP
+5VAMP 2 100K_0402_5% 24 HP EN HPOUT_R
HP_R 17
+5VAMP HP_RIGHT 1 2 HP_RIGHT_C 1 2 HP_RIGHT_R 4 18 HPOUT_L
31 HP_RIGHT C574 2.2U_0805_10V6K R471 39K_0402_5% HP_LEFT_R INR_H HP_L HP_PLUG#
6 INL_H
2
HP_LEFT 1 2 HP_LEFT_C 1 2
31 HP_LEFT
1
2
C570 2.2U_0805_10V6K R468 39K_0402_5% VOL_AMP 26 R760
R472 /SD R350
CVSS 15 100K_0402_5%
1
30K_0402_5% D
28 BEEP 100K_0402_5%
16 2
1 1
VSS G
12
Gain= 14dB 1 1
2
1
CP+
3
C563
S D Q59
14 2 S
3
C561 CP- GND G
SPDIF_PLUG# SPDIF_PLUG# 2
23 1U_0603_10V4Z 2
VOL_AMP BIAS PGND G 2N7002_SOT23
1U_0603_10V4Z 25 7
BIAS PGND
1
D 2 2 Q17 Q60
1 13 D S
3
CGND
1
2
0.01U_0402_16V7K 2N7002_SOT23 2.2U_0805_10V6K
2
2
1
+5VAMP
R51 C416 9
2.2K_0402_5%
C612 2 SINGA_2SJ-E373-T01
15mil
JP4 R523 FBMA-L11-160808-121LMT_0603 100P_0402_50V8J CONN@
2
0.1U_0402_16V4Z 1 INT_MIC_R2
1 2 INT_MIC_R
1 INT_MIC_R 31
2 1 2
2 R524 FBMA-L11-160808-121LMT_0603
3
1
C36 LINE-IN JACK
+3VALW G1 220P_0402_50V7K JP33
4
G2 2
8
ACES_88266-02001 7
C614 CONN@
0.1U_0402_16V4Z LINEIN_PLUG# 5
31 LINEIN_PLUG#
3 INT_MIC_R2 3
4
L54 FBM-11-160808-700T_0603
LINE_R 1 2 LINE_R_R 3
31 LINE_R
2
3
6
@ LINE_L 1 2 LINE_L_R 2
31 LINE_L
L55 FBM-11-160808-700T_0603 1
Volume Control Circuit +3VS
PSOT24C-LF-T7_SOT23-3
D32
1 1
SINGA_2SJ-E351-S03
+3VS C613 C601 CONN@
1
220P_0402_50V7K 220P_0402_50V7K
(HDA Jack)
1
C347 2 2
+3VS 2 1 R330
1
1
100K_0402_5%
R450 R435 0.1U_0402_16V4Z FOR EMI
MIC JACK
4
+3VS
GND
U12 1 JP32
2
2
NC
2 1 2 2 4 0.1U_0402_16V4Z 7
A R436 10K_0402_5% A Y
G
1
2
1 NC7SZ14P5X_NL_SC70-5 U13 MIC_PLUG# 5
3
COM 31 MIC_PLUG#
1 14 R488 R487
CD1# VCC 2.2K_0402_5% 2.2K_0402_5%
2 13 4
D1 CD2#
3 1 2 3 12
2
B R446 10K_0402_5% CP1 D2 MIC1_R_1
4
SD1# CP2 11 31 MIC1_R 1 2 FBM-11-160808-700T_0603 3
1 1 5 10 L52 6
GND
Q1 SD2#
0.01U_0402_16V7K
0.01U_0402_16V7K
2 2 TC74LCX74FT_TSSOP14 SINGA_2SJ-E351-S01
0.1U_0402_16V4Z
2 C603 C602 CONN@
4 220P_0402_50V7K 220P_0402_50V7K 4
2 2
(HDA Jack)
Dr-Bios.com
ENCODER_DIR 28
ENCODER_PULSE 28
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Amplifier & Audio Jack
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JDW50/JDYL70 M/B LA-3771P
Date: Monday, April 16, 2007 Sheet 32 of 44
A B C D E
H29 H20 H3 H18 H2 H11 H10 H30 H4
H_S354D138 H_S354D138 H_S354D138 H_S354D138 H_S354D138 H_S354D138 H_S354D138 H_S354D138 H_S354D138
FAN1 Conn @ @ @ @ @ @ @ @ @
1
+5VS
C443 10U_0805_10V4Z +5VS
1 2 H15 H19 H1 H24 H28
H_S354D138 H_C315BC236D138 H_C315BC236D138 H_S354BC140D138 H_C335BC140D138
1
U20 D22
1 8 1SS355_SOD323-2 @ @ @ @ @
1
VEN GND
2 VIN GND 7
+VCC_FAN1 3 6
2
EN_DFAN1 VO GND D21 H6 H16 H17 H7
28 EN_DFAN1 4 5
VSET GND H_C236BC168D165 H_C236BC168D165 H_C236BC168D165 H_C236BC168D165
G993P1UF_SOP8
1 2 Change to SC1BAS16000
BAS16_SOT23-3 For CPU Support Breket
C446 @ @ @ @
1
10U_0805_10V4Z
1 2
+3VS C445 H13 H14 H32 H33 H31
1000P_0402_50V7K H_C236BC131D128 H_C236BC131D128 H_C236BC131D128 H_C236BC131D128 H_C236BC131D128
1 2
For FAN and MXM
1
R365 @ @ @ @ @
1
10K_0402_5%
40mil
JP16
2
+VCC_FAN1 H21 H8
1 H_C236BC131D128 H_C236BC131D128 H5 H27
28 FAN_SPEED1 2 H_C158D158N H_O197X158D197X158N
3
1
C442 ACES_85205-03001 @ @ For MDC
1
1000P_0402_50V7K CONN@ @ @
1
2
1
FD1 FD2 FD3 FD4 FD5 FD6
@ @ @ @ @ @
1
1
FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80
@ @ @ @ @
1
1
1
FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80
@ @ @ @ @
1
1
1
FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Size
B
Date:
Compal Electronics, Inc.
Document Number
FAN & Screw Hole
JDW50/JDYL70 M/B LA-3771P
Monday, April 16, 2007 Sheet 33 of 44
Rev
0.2
A B C D E
2
U22 U34 R455
8 1 8 1 100K_0402_5%
D S D S
7 2 7 2
D S D S
2
6 3 1 1 6 3 1 1
1
D S C503 C495 R411 D S C633 C629 R506 SYSON#
1 1 5 4 1 5 4 24,26,27 SYSON#
C498 C504 D G 470_0603_5% C631 D G 470_0603_5%
AO4468_SO8 10U_0805_10V4Z AO4468_SO8 10U_0805_10V4Z
1
10U_0805_10V4Z 2 2
1U_0603_10V4Z 2 2
1U_0603_10V4Z D
1
1 2 2
10U_0805_10V4Z 2
10U_0805_10V4Z SYSON Q29 1
27,28,40 SYSON 2
G 2N7002_SOT23
1
D D
S
3
1
2 SUSP 2 SBPWR_EN#
G G R440
+VSB 2 1 5VS_GATE S Q23 +VSB 2 1 3V_GATE S Q38 100K_0402_5%
3
R412 2N7002_SOT23 R505 2N7002_SOT23
200K_0402_5% 1 200K_0402_5% 1
2
1
D C506 C632
1
SUSP D
2
Q24G 0.1U_0603_25V7K SBPWR_EN# 2 0.1U_0603_25V7K
2N7002_SOT23 S 2 Q39G 2 +5VALW
3
2N7002_SOT23 S
2
R462
100K_0402_5%
1
SUSP
+3VALW TO +3VS 30,39 SUSP
1
+3VALW +3VS D
2 Q31
23,27,28,30,40 SUSP#
U10 G 2N7002_SOT23
8 1 S
3
D S
1
7 2
D S
2
6 3 1 1 R457
D S C301 C299 R306 100K_0402_5%
1 1 5 D 4
C344 C343 G 470_0603_5%
AO4468_SO8 10U_0805_10V4Z
2
10U_0805_10V4Z 2 2
1U_0603_10V4Z
2 2 2
10U_0805_10V4Z 1 1 2
D
2 SUSP
G
S Q12
3
5VS_GATE 2N7002_SOT23
+5VALW
2
+1.8V to +1.8VS R379
100K_0402_5%
+1.8V +1.8VS
1
U24
8 D 1
S SBPWR_EN#
7 2 1 1 21 SBPWR_EN#
D S
2
6 3 C533 C531
D S R427
1 1 5 D 4
C553 C547 G 10U_0805_10V4Z 470_0603_5%
1
SI4856ADY_SO8 PM@ 2 2
1U_0603_10V4Z PM@ D
10U_0805_10V4Z PM@ PM@ 28 SBPWR_EN 2
1
PM@ 2 2
10U_0805_10V4Z G
PM@ SI4856/AO4430 Q43 S
3
1
1
D 2N7002_SOT23
2 SUSP R510
G 100K_0402_5%
2 1 1.8VS_GATE S Q26
+VSB
3
R439 2N7002_SOT23
2
510K_0402_5% 1 PM@
3 PM@ C542 3
1
D
SUSP 2 0.1U_0603_25V7K
G 2 PM@
Q28 S
3
2N7002_SOT23
PM@
2
2
2
1
1
1
1
1
1
D D D D D
2 SUSP 2 SUSP 2 SUSP 2 SUSP 2 SYSON#
G G G G G
S Q11 S Q19 S Q22 S Q16 S Q25
3
3
3
A
Dr-Bios.com B
Security Classification
Issued Date 2007/1/15
Compal Secret Data
Deciphered Date 2007/12/25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C D
Title
Size
B
Date:
Compal Electronics, Inc.
Document Number
DC Interface
JDW50/JDYL70 M/B LA-3771P
Monday, April 16, 2007
E
Sheet 34 of 44
Rev
0.2
A B C D
PJP1 PL1
6 ADPIN VIN
G2 FBMA-L18-453215-900LMA90T_1812
G1 5 1 2
1
PR1
560P_0402_50V7K
12P_0402_50V8J
4 10_1206_5%
12P_0402_50V8J
560P_0402_50V7K
4
1
PC1
PC2
PC3
PC4
1 PR2 1
1 2
3 1K_1206_5%
2
3
1 2
PD1
2 RLZ24B_LL34 PQ1
2 PR3 TP0610K-T1-E3_SOT23-3
VIN PD2 1K_1206_5%
B+
2
1 1 2 1 1 2 3 1
RLS4148_LLDS2 PR4
E&T_4510-E04C-01R 1K_1206_5%
1 2
100K_0402_5%
100K_0402_5%
1
1
PR5
PR7
PR6
1K_1206_5%
2
1 2
2
VIN
1
PD3
RLS4148_LLDS2 PR8
1
PD4 100K_0402_5%
RB751V-40TE17_SOD323-2 PQ2
1 1
2 1 DTC115EUA_SC70-3
1 2
BATT+
2 PR9 28,37 ACOFF 2 2
33_1206_5% VS PQ3
PQ4 DTC115EUA_SC70-3
TP0610K-T1-E3_SOT23-3
2 2
3
CHGRTCP 3 1
0.22U_1206_25V7K
1
3
1
PR10
PC5
100K_0402_5% PC6
0.1U_0603_25V7K
2
PR11
B+
2
2
22K_0402_5% PR12
29,30 51ON# 1 2 VL 2.2M_0402_5%
2 1
1
VS PR13
499K_0402_1%
1
1
PR14
2
RTCVREF PR15 100K_0402_1%
200_0805_5% PU2A
3.3V PU1 LM393DT_SO8
8
G920AT24U_SOT89-3 19,36,38 MAINPWON PD5
2
PR16 PR17 2 3
P
3 3
+
1 2 1 2 3 OUT IN 2 1 1 O
+CHGRTC 37 ACON 3 2
0.01U_0402_25V7K
-
G
1
1
560_0603_5% 560_0603_5%
4.7U_0805_6.3V6K
1
1
GND
32.8
PC9
PC8
1000P_0402_50V7K
4
1
1
1U_0805_25V4Z 191K_0402_1%
2
1 PC10
PC11
PR19
2
2
0.1U_0603_25V7K 499K_0402_1%
PRG++ 2
2
2
ACIN
PR20 PQ5 PR21
Precharge detector D
1
34K_0402_1% RHU002N06_SOT323-3 47K_0402_5%
Min. typ. Max. RTCVREF 2 1
G
2 2 1
PACIN 37,38
1
H-->L 14.589V 14.84V 15.243V S
3
PQ6
1
DTC115EUA_SC70-3
L-->H 15.562V 15.97V 16.388V @ PR22
- PBJ1 + +RTCBATT 66.5K_0402_1% 2 +5VALW
2 1 +RTCBATT BATT ONLY
2
Precharge detector
3
ML1220T13RE Min. typ. Max.
4
45@
H-->L 6.138V 6.214V 6.359V 4
A
Dr-Bios.com B
Security Classification
Issued Date 2007/01/16
Compal Secret Data
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2008/01/16 Title
Size
B
Date:
Compal Electronics, Inc.
Document Number
JDW50/JDY70
Monday, April 16, 2007
DCIN/DECTOR
D
LA3771P
Sheet 35 of 44
Rev
0.2
A B C D
MAX8744_B+
MAX8744_B+
B+
PL2
FBMA-L18-453215-900LMA90T_1812
1 2
2200P_0402_50V7K
2200P_0402_50V7K
4.7U_1206_25V6K
4.7U_1206_25V6K
4.7U_1206_25V6K
1
1
1
PC13
PC12
PC16
8
7
6
5
5
6
7
8
PC14
PC15
1 1
D
D
D
D
D
D
D
D
2
2
PQ8
PQ7 SI4800BDY-T1-E3_SO8
SI4800BDY-T1-E3_SO8
G
S
S
S
S
S
S
1
2
3
4
4
3
2
1
PL3 PU3
10UH_SIL104R-100PF_4.4A_30% MAX8744ETJ+_TQFN32_5X5
PC17
1 2 1U_1206_25V7K
+3VALWP 33 21 1 2
EP IN
2.2_1206_5%
SI4810BDY-T1-E3_SO8
2
D 5
6
7
D 8
DH3 DH5
2.2_1206_5%
25 16
2.61K_0402_1%
DH3 DH5
8
7
6
5
PR24 PR25
PR23
@ PR195
@ PR196
D
D
SI4810BDY-T1-E3_SO8
PQ9
2 1 BST3A 26 15 BST5A 2 1
6.81K_0402_1%
D
D
D
D
330U_D3L_6.3VM_R25M
BST3 BST5
2
1 0_0603_5%
1 2
2
2
PC19 0_0603_5% PC20 PR27
PR26
G
S
2 S
1 S
10UH_SIL104R-100PF_4.4A_30%
+
PQ10
0.1U_0603_25V7K 2.61K_0402_1%
G
S
S
S
PR28 0.1U_0603_25V7K
PC18
2 1
680P_0402_50V7K
1
4
3
1
6.49K_0402_1% LX3 LX5
PC162
24 17
680P_0402_50V7K
1
1
2
3
4
2
2 LX3 LX5
PC161
2 1
0.22U_0603_16V7K
2
2
DL3 23 18 DL5 @
6.49K_0402_1%
DL3 DL5
2
1 2 @
PL4
PR29
2
PC21
PC22
10K_0402_1%
PGND 19
0.22U_0603_16V7K CSH3
PR30
2 29 2
1
CSH3
1
1
CSL3 28 12 CSH5
CSL3 CSH5
1
13 CSL5
CSL5
1
PC23 FB3 30
1000P_0402_50V7K FB3 +5VALWP
15.4K_0402_1%
2VREF_8744
1
PC25
2
1 2 7 11 FB5 1000P_0402_50V7K
REF FB5 PC26
PR31
2
PC24 0.22U_0603_10V7K VL 4.7U_0805_6.3V6K
2 20 1 2
150U_D2_6.3VM
DRVA LDO5
1
@ PR32 0_0402_5% 1
SKIP 10 2 12VREF_8744
2
+
PC27
+3VALWP Ipeak = 5.5A; Imax = 4A 32 OUTA PR182 0_0402_5%
PR33
10K_0402_1%
PGOODA 22 1 2
PZD1 2
31 FBA
RLZ5.1B_LL34 PR34
DCR = 35m ohm(max) ; Rcs = 24.96m ohm
1
VS 100K_0402_5% 27
PGOOD3 SPOK 38
1 21 2 4 SHDN
DCR = 29m ohm(typical) ; Rcs = 20.68m ohm
2
200K_0402_5%
PGOOD5 14
2
PC28 PR36
PR35
6 ON5
0.22U_0603_25V7K 0_0402_5%
Ilimit = 185mV/24.96m ~ 215mV/20.68m 3 ILM 2 12VREF_8744
1
ILIM
= 7.41A ~ 10.39A
FSEL
5
GND
ONA
1
ON3
2
+5VALWP Ipeak = 5.5A ; Imax = 4A
499K_0402_1%
2
@ PR37
3
Iocp(mean) = Ilimit -Delta I/2 =6.956A~9.936A 3
2
@ PR38
0_0402_5%
8
0_0402_5%
DCR = 35m ohm(max) ; Rcs = 24.96m ohm
PR39
1
2
PR179
Delta I=((Vin-Vo)*D)/(F*L)
0_0402_5%
2VREF_8744
1
0_0402_5%
PR40
19,35,38 MAINPW ON 2VREF_8744 1
DCR = 29m ohm(typical) ; Rcs = 20.68m ohm
=((19-3.3)*(3.3/19))/(300K*10U) 2 1 1 2
PR41
=0.908A Ilimit = 185mV/24.96m ~ 215mV/20.68m
1
@ 47K_0402_5%
= 7.41A ~ 10.39A
0.047U_0402_16V7K
1
1
PC30
Notes : PC29
Iocp(mean) = Ilimit -Delta I/2
1U_0603_6.3V6M
=6.796A~9.776A
2
2
fESR<=fOSC/π ; fESR=1/(2*π*RESR*COUT)
ON3 = REF --->3.3V starts up delay 2ms after 5V starts up @
Delta I=((Vin-Vo)*D)/(F*L)
=((19-5)*(5/19))/(300K*10U)
1.228A
4 4
A
Dr-Bios.com B
Security Classification
Issued Date 2007/01/16
Compal Secret Data
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
C
2008/01/16 Title
Date:
JDW50/JDY70
Compal Electronics, Inc.
+5VALWP/+3VALWP
Iada=0~4.74A(90W)
ADP_I = 19.9*Iadapter*Rsense
CP = 85%*Iada ; CP = 4.07A
PQ29 P2 PQ30
AO4407_SO8 AO4407_SO8 P3
PR151
0.02_2512_1%
B+ PL15
CHG_B+
PQ31
AO4407_SO8
VIN 8 1 1 8 FBMA-L18-453215-900LMA90T_1812 1 8
7 2 2 7 1 4 1 2 2 7
6 3 3 6 3 6
5 5 2 3 CSIN 5
1 1
CSIP
10U_1206_25V6M
10U_1206_25V6M
2200P_0402_25V7K
0.1U_0603_25V7K
4
4
PQ43
1
1
1
TP0610K-T1-E3_SOT23-3
PC123
PC124
1
PC125
PC126
PR154
5600P_0402_25V7K
PR152 DCIN 47K_0402_1%
0.1U_0603_25V7K
VIN 3 1
2
2
2
1
2
47K_0402_1% PR153 1 2
VIN
1
PC127
PC128
200K_0402_1% PC129
100K_0402_1%
0.1U_0603_25V7K PQ44
2
1
PR184
DTC115EUA_SC70-3 PD11
2
1SS355TE-17_SOD323-2
PD17 PR155 1 2 ACOFF
2
3
2
DTA144EUA_SC70-3 PD16 2 1 21
1SS355TE-17_SOD323-2 3 EC_ON
1
2 1 2 6251VDD 100K_0402_1% EC_ON 28,30 PR156
RB715F_SOT323-3 200K_0402_1%
2.2U_0603_6.3V6K
PC130
PR157 1 2 VIN
3
1
10K_0402_5%
1
2 1 PU10 PC131
28 FSTCHG
1
0.1U_0603_25V7K
1
2
1 2 1 24 DCIN 2 1 PD13
VDD DCIN
1
6251VDD 1 PC153 BATT+ PQ33 1SS355TE-17_SOD323-2
100K_0402_1%
2
0.1U_0402_16V7K DTC115EUA_SC70-3 2 1 2
PR159
2 PR158 2 23
PQ34 47K_0402_5% PQ35 ACSET ACPRN PR197 PQ36
1
DTC115EUA_SC70-3 DTC115EUA_SC70-3 20_0603_5% D RHU002N06_SOT323-3
1
6251_EN CSON 2 PACIN
0.1U_0603_25V7K
3 22 1 2
3
EN CSON
1
2
D
PC132
2 @ PC134 PC133 G
28 3S/4S#
3
5
6
7
8
2 PR160 680P_0402_50V7K 0.047U_0603_16V7K S
3
G 150K_0402_1% CSON 1 2 4 21 1 2 CSOP
D
D
D
D
1
CELLS CSOP
S PQ37 PR161
3
2
RHU002N06_SOT323-3 PC135 6800P_0402_25V7K 20_0603_5% PQ38 2
3
2
1 2 5 20 2 1 SI4800BDY-T1-E3_SO8
ICOMP CSIN
G
2
S
S
S
PR162 20_0603_5%
PC137 PR163 10K_0402_1% PC136 0.1U_0603_25V7K
4
3
2
1
1 2 1 2 6 19 1 2 PR165
1
PR164 VCOMP CSIP PR198 PL16 0.02_2512_1%
0.01U_0402_25V7K 2
1 100_0402_1% 2.2_0603_5% 10UH_PCMB104T-100MS_6A_20% BATT+
PR166 PC138 1 2 7 18 LX_CHG 1 2 CHG 1 4
ICM PHASE
1
22K_0402_5% D 100P_0402_50V8J
PACIN 1 2 2 PQ39 2 3
35,38 PACIN
1
RHU002N06_SOT323-3 6251VREF DH_CHG
4.7_1206_5%
G 8 17
SI4800BDY-T1-E3_SO8
28 ADP_I VREF UGATE
PR199
S PC139 PR167 PC140
3
5
6
7
8
PR168 2.2_0603_5% 0.1U_0603_25V7K
10U_1206_25V6M
1 2
PQ40
80.6K_0402_1% BST_CHG 1 BST_CHGA 2
10U_1206_25V6M
9 16 2 1
D
D
D
D
CHLIM BOOT
1
ACON 2 1 0.1U_0402_16V7K
35 ACON
2
28 IREF
1
1
PC142
PC141
PD14
0.01U_0402_25V7K
680P_0402_50V7K
10 ACLIM VDDP 15
G
1
S
S
S
2
2
1
1
PC163
PC143
4
3
2
1
DTC115EUA_SC70-3 100K_0402_1% 11 14 DL_CHG
VADJ LGATE
2
PR171
2
2
ACOFF 2 4.7_0603_5%
28,35 ACOFF
2
12 13 PC144
1
GND PGND 4.7U_0805_6.3V6K
PR173
274K_0402_1% ISL6251AHAZ-T_QSOP24
3
6251VREF 3 1 2
D
PQ42
1
SI2301BDS-T1-E3_SOT23-3
G
2
PR174
3 CP mode 100K_0402_1% PR183 3
Iinput=(1/0.02)((0.05*Vaclm)/2.39+0.05) 274K_0402_1%
6251VREF
where Vaclm=1.502V, Iinput=4.07A OVP voltage :
2
1
Vaclim=2.39*((10K//152K)/((5.76K//152K)+(10K//152K))) LI-4S :18.0V--BATT-OVP=2.677V
@PR186 VS BATT+
1
D 100K_0402_1% 6251_EN
=1.502V BATT-OVP=0.1487*BATT+
2 PQ45
1
G RHU002N06_SOT323-3 C LI-3S :13.50V--BATT-OVP=2.007V
2
28 CALIBRATE
1
28 CHGSEL S 2 @ PQ46
3
0.01U_0402_25V7K
CC=0.6~4.48A 0.01U_0402_25V7K
E 845K_0603_1%
3
1
1
PC154
PC145
IREF=0.7224*Icharge
2
2
@ @ PR187
1
CSON 20K_0402_1% PR192
IREF=0.43V~3.24V
2
PR176 11.5K_0402_1%
300K_0603_0.1% 6251VREF 1 2 6251aclim
PU11A
2.37K_0402_1%
UMA@ PR193
PR177 LM358ADT_SO8
1
10K_0402_5%
Charging Voltage + 3
P
1 2 1 PR194
BATT Type 3S/4S# CHGSEL CV mode 0 20K_0402_1%
(0x15) 28 BATT_OVP - 2
G
VS
0.01U_0402_25V7K
1
4
2
1
1
PC146
1
8
D
2
2
5 2
P
2
+ 28 65W/90W# G
7
2800mAH 3S pack 13050mV HIGH LOW 12.90V 0
6 S
3
-
G
4 4
Dr-Bios.com
4
VL
1
SUYIN_200275MR007G161ZL
BATT++ VS VL
1
PJP2 PL5
FBMA-L18-453215-900LMA90T_1812
2
BATT++
1 1 2 BATT+
1
PC31 PR44 PR42
2 TSA 0.1U_0603_25V7K 442K_0603_1% 150K_0402_1%
3 EC_SMC1 PR43 1 2
2
4 EC_SMD1 9.76K_0402_1%
1
5
2
6 PR45 PU2B
7
8
82.5K_0603_1% LM393DT_SO8
PC32 PC33 1 2 5
P
1000P_0603_50V7K 0.01U_0603_50V7K + MAINPW ON 19,35,36
100_0603_1%
<BOM Structure> 7
2
O
1
TM_REF1 6
100K_0603_1%_TH11-4H104FT
-
G
PR46
4
PH1
2
1
100_0603_1%
PR48
1U_0805_16V7K
2
1
1
6.49K_0603_1% PC34 PR49
PR47
PC35
1 2 1000P_0402_50V7K 150K_0402_1%
+3VALW P
2 1 VL
2
2
1
PR50
1
1K_0603_1%
2 PR51 2
150K_0402_1%
2
2
BATT_TEMP BATT_TEMP 28
EC_SMB_CK1 15,28,29
EC_SMB_DA1 15,28,29
PR52
1M_0402_1%
1 2
VIN VIN
PR54
1
10K_0402_5% PR55
PR53 VS 10K_0402_5%
84.5K_0402_1% 1 2 ACIN
ACIN 20,28
PR56
2
8
22K_0402_5% PU4A
1 2 3 LM393DT_SO8
P
3 3
+ PACIN
O 1 PACIN 35,37
20K_0402_1%
2 -
G
1
1
1
1
1
PC36
PR57
4
PQ11 1000P_0402_50V7K PC37 PZD2 PR58
TP0610K-T1-E3_SOT23-3 0.1U_0603_25V7K RLZ4.3B_LL34 10K_0402_5%
2
2
2
B+ 3 1 +VSBP
2
2
PR60
1
10K_0402_5%
1
PR59 2 1
100K_0402_5% PC38 PC39 RTCVREF
0.22U_1206_25V7K 0.1U_0603_25V7K
2
PR61
2
22K_0402_5%
VL 1 2 PU4B
8
LM393DT_SO8
5
P
+
2
G
100K_0402_5%
Min. typ. Max.
4
PR63
H-->L 16.976V 17.257V 17.728V
1
D
1
0_0402_5%
PQ12
36 SPOK
1 2 2
G RHU002N06_SOT323-3 L-->H 17.430V 17.901V 18.384V
S
3
1
4 4
@ PC40
0.1U_0402_16V7K
Dr-Bios.com
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BATTERY CONN. / OTP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B JDW50/JDY70 LA3771P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, April 16, 2007 Sheet 38 of 44
A B C D
5 4 3 2 1
+3VALW
1
PJP3
1
JUMP_43X118
+1.8V
2
2
1
2
10U_0805_6.3V6M
PJP4
PC73
D JUMP_43X118 D
+5VALW
1
2
RTCVREF
+1.8V
2
PU7
PU6 CM8562IS_PSOP8
1 6
VIN VCNTL +3VALW 1 8
VIN PGND
2 GND NC 5
1
1
2
1U_0603_16V6K
PC74 PC75
3 REFEN NC
7
+2.5VSP 2
VFB AGND 7
PC76
10U_0805_6.3V6M 1U_0603_6.3V6M
2
PR110 4 8
1
1K_0402_1% VOUT NC
3 6
VTT VCCA
10_0603_1%
PR111
9
2
GND
AGND
RT9173DPSP_SO8 4 5
VTT REFEN
RHU002N06_SOT323-3
2 1
1K_0402_1%
0.1U_0402_16V7K
PR113
9
+0.9VSP
1
2
0_0402_5% D PC77 PR112
2
1
200K_0402_1%
PQ19
PR114
PC78
PR115
SUSP 1 2 2 22U_1206_10V6M 60.4K_0402_1%
2
30,34 SUSP
0.1U_0603_25V7K
G
2
S PC79 PC80
3
PC81
22U_1206_10V6M 0.047U_0402_16V7K
2
1
1
2
PQ20 PR116
1
D RHU002N06_SOT323-3 0_0402_5%
2 1 2 SUSP
G
C C
S
3
PJP5 PJP6
2 1 2 1
+3VALWP 2 1
+3VALW +1.8VP 2 1
+1.8V
JUMP_43X118 JUMP_43X118
PJP7 PJP8
2 1 2 1
+5VALWP 2 1
+5VALW +2.5VSP 2 1
+2.5VS
JUMP_43X118 JUMP_43X118
PJP9 PJP10
2 1 2 1
+0.9VSP 2 1
+0.9VS +1.5VSP 2 1
+1.5VS
JUMP_43X118 JUMP_43X118
B PJP13 PJP12 B
2 1 2 1
+1.05VSP 2 1
+1.05VS +VSBP 2 1
+VSB
JUMP_43X118 JUMP_43X118
PJP14
2 1
+1.05VSP 2 1
+1.05VS
JUMP_43X118
A A
5
Dr-Bios.com 4
Security Classification
Issued Date 2007/01/16
Compal Secret Data
Deciphered Date 2008/01/16
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3 2
Title
Date:
Compal Electronics, Inc.
+0.9VSP/+2.5VSP
Size Document Number
Custom JDW50/JDY70
1
Sheet 39 of
0.1
44
Rev
5 4 3 2 1
+5VALW
D D
1
1
PR180
1
PC82 10_0603_5%
2.2U_0603_6.3V6K PR117 PD9
2
10_0603_5% VCCA_1.8V CHP202UPT_SOT323-3
1 2
B+
1U_0603_10V6K
VCCA_1.5V
PC149
1 2
B+_1.8/1.5
1U_0603_10V6K
1
PL9
PC83
2
FBMA-L11-322513-151LMA50T_1210 PR118
1 2 BST_1.5V-1 100K_0402_5%
2
4.7U_1206_25V6K
4.7U_1206_25V6K
2
1
1
PC85
BST_1.8V-1
8
7
6
5
PU8
PC86
PQ21
D
D
D
D
2
DL_1.8V 2 27 PGOOD1_1.8V
G DL1 PGD1
S
S
S
PR119 PC87
Maximum continuous current=>6A 0_0603_5% 1 2 +5VALW 3 26 FB_1.8V B+_1.8/1.5
1
2
3
4
4.7U_1206_25V6K
+1.8VP
1
PL10 1 2 ILIM_1.8V4 25 VCCA_1.8V 1000P_0402_50V7K
4.7U_1206_25V6K
ILIM1 VCCA1 PQ22
1UH_SIL104-1R0-R_11A_30% PR120 34.8K_0402_1%
PC89
PC90
1 2
Vout_1.8V 1 2 LX_1.8V 5 24 Vout_1.8V 8 1
2
LX1 VOUT1 PR121 G2 D2
7 2
DH_1.5V-1
DH_1.8V D1/S2/K D2
6 DH1 TON1 23 2 1 B+_1.8/1.5 6 D1/S2/K G1 3
1
D1/S2/K S1/A
1
AO4916_SO8
8
7
6
5
2 1 9 TON2 DH2 20 1 2
PQ23
SI4810BDY-T1-E3_SO8 PR125 Vout_1.5V 10 19 LX_1.5V
2.2UH_SIQB74B-2R2-R_6.5A_20%
1 2 Vout_1.5V
+1.5VSP
VOUT2 LX2
G
1
2
S
S
S
1M_0402_5% PR128
1
PR127 VCCA_1.5V ILIM_1.5V1
20K_0402_1%
11 18 2
1
2
3
4
VCCA2 ILIM2
1
10K_0402_1% PC96 29.4K_0402_1%
1000P_0402_50V7K FB_1.5V +5VALW PC97
PR129
12 17 1
330U_D2E_2.5VM
2
FB2 VDDP2 33P_0402_50V8K
2
2
DL_1.5V +
PC98
13 PGD2 DL2 16
2
14 15 FB_1.5V
VSSA2 PGND2
1
2
1
PR131 PC100
0_0402_5% 1U_0603_10V6K PR130
2
Close to IC Side 1 2 SC413TSTRT_TSSOP28 10K_0402_1%
23,27,28,30,34 SUSP#
Differential routing of feedback VFB=0.5V
2
1
@ PC101
to VSSA1 and VOUT1 PIN +5VALW 0.1U_0402_16V7K
2
1
1
@ PC102
PGOOD2_1.5V 0.1U_0402_16V7K
2
VFB=0.5V
VFB=0.5V Vo=VFB*(1+PR129/PR130)=1.5V
Vo=VFB*(1+PR122/PR127)=1.805V Ipeak=5.16A, Imax=3.612A
Ipeak=12.17A, Imax=8.519A Ton=(3.3E-12*(PR125+37K)*(Vout/VBat))+50ns
Ton=(3.3E-12*(PR121+37K)*(Vout/VBat))+50ns =0.3201us
=3.3*10e-12*(820K+37K)*(1.8/19)+50ns=0.3179us AO4916 Rds(on)=>Typ:21 mOhm
FDS6670AS:Rds(on)=>Typ:9 mOhm Max:27 mOhm
Max:11.5 mOhm Ivalleymin=9*10u*(29.4K/0.027*1.4)=7A
Iocp=Ivalley+Iripple/2 Ivalleymax=11*E-6*(29.4K/0.021*1.1)=12.833A
Iripple=(vin-vout)*(Ton/L)=5.467A, 1/2 Iripple=2.734A. Iripple=(vin-vout)*(Ton/L)=2.546A, 1/2Iriiple=1.273A
A
Ivalleymin=10E-6*(PR120/Rds(ON)max*1.5) Iocp=Ivalley+Iripple/2 A
=9*10e-6*(27.4K/0.0115*1.5)=14.295A>11.73*1.2=14.076A OCP==>8.273A~14.106A
Dr-Bios.com
Ivalleymax=10E-6*(PR120/Rds(ON)typ*1.2)
=11*10e-6*(27.4K/0.009*1.2)=27.907A.
Security Classification Compal Secret Data Compal Electronics, Inc.
OCP==>17.029A~30.641A Issued Date 2007/01/16 Deciphered Date 2008/01/16 Title
+1.5VSP/+1.8VP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom JDW50/JDY70 LA3771P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, April 16, 2007 Sheet 40 of 44
5 4 3 2 1
5 4 3 2 1
D D
+5VALW
1
1
PR134
PR148 PC103 10_0603_5%
0_0402_5% 2.2U_0603_6.3V6K
2
1 2
2
30 VS_ON VCCA_1.05V PD10
1
PR142 1SS355TE-17_SOD323-2
B+_1.05
1U_0603_10V6K
1
@ PC121 1M_0402_5% PL12
PC104
0.1U_0402_16V7K B+_1.05 2 1 FBMA-L11-322513-151LMA50T_1210
2
1
1 2 B+
BST_1.05V-1
4.7U_1206_25V6K
SI4800BDY-T1-E3_SO8
1
4.7U_1206_25V6K
1
PC109
PC110
D 5
D 6
7
D 8
PC116
2
1000P_0402_50V7K
D
2
PQ26
C C
+5VALW
16
15
14
13
4 G
3 S
S
1 S
PR141 PC113
BST_1.05V 1 2 1 2
TON
NC
EN/PSV
BST
2
0_0603_5% Maximum continuous current=>6A
1
11K_0402_1%
3 10 1 2
2
FB ILIM
1
34K_0402_1%
5
6
7
8
PGOOD2_1.05V +5VALW PC117
PR146
4 9 1
330U_D2E_2.5VM
PGD VDDP
PGND
VSSA
PQ28 33P_0402_50V8K
D
D
D
D
2
+
NC
PC118
TP
DL
SI4810BDY-T1-E3_SO8
2
PU9 FB_1.05V
17
G
2
S
S
S
SC411MLTRT_MLPQ16_4X4
1
VFB=0.5V
4
3
2
1
DL_1.05V PR147
10K_0402_1%
1
PC120
2
1U_0603_10V6K
2
Close to IC Side
B B
Differential routing of feedback to VSSA2 and VOUT2 PIN
A OCP==>12.346A~20.127A A
5
Dr-Bios.com 4
Security Classification
Issued Date 2007/01/16
Compal Secret Data
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2008/01/16
2
Title
Size
Custom
Date:
Compal Electronics, Inc.
+1.05VSP
Document Number
JDW50/JDY70
Monday, April 16, 2007
LA3771P
Sheet
1
41 of
0.1
44
Rev
5 4 3 2 1
+5VS
CPU_B+ B+
PR64
0_1206_5% PL6
5VS12 1 FBMA-L18-453215-900LMA90T_1812
1 2
0.01U_0402_25V7K
1
@ PC42
100U_25V_M
PR65
2200P_0402_50V7K
0.1U_0603_25V7K
1
+
PC43
10_0402_5%
1
10U_1206_25VAK
10U_1206_25VAK
10U_1206_25VAK
PC44
PC45
PC46
PC47
PC48
200K_0402_5%
2
2
1
2
2
D D
PR66
PC49
2
PC50 2.2U_0603_6.3V6K
2
PR67 1U_0603_6.3V6M
1
13K_0402_1%
5
PQ13
SI7686DP-T1-E3_SO8
PU5
1
NTC
@PH2 VCC 19 25
Use one 220uF or two 100uF
100K_0603_1%_TH11-4H104FT Vcc VDD PC51 4
1 2 6 8 PR69 0.22U_0603_16V7K
THRM TON 0_0603_5%
PR68 0_0402_5%
5 CPU_VID0 2 1 31 D0 BST1 30 BST1_CPU 1 2 BSTM1_CPU 1 2 PR71 +CPU_CORE
0_0603_5%
3
2
1
PR70 0_0402_5% 2 1 32 29 DH1_CPU 1 2 PL7
5 CPU_VID1 D1 DH1 0.36UH_PCMC104T-R36MN1R17_30A_20%
PR72 0_0402_5% 2 1 33 28 LX1_CPU 2 1 +CPU_CORE
5 CPU_VID2 D2 LX1
1
PR73 0_0402_5% DL1_CPU
4.7_1206_5%
2.1K_0402_1%
5 CPU_VID3 2 1 34 D3 DL1 26
2
PR74
FDS6676AS_SO8
5
6
7
8
5
6
7
8
PR76
PR75 0_0402_5%
FDS6676AS_SO8
5 CPU_VID4 2 1 35 D4 PGND1 27
PQ14
D
D
D
D
D
D
D
D
PQ15
PR77 0_0402_5% 2 1 36 18
5 CPU_VID5
2
D5 GND PR79 NTC
1
CSP1_CPU
10_0402_5%
PR78 0_0402_5% 1 2 37 17 3.48K_0402_1% PH3
5 CPU_VID6 D6 CSP1
G
G
S
S
S
S
S
S
PR80
680P_0402_50V7K
1 2 1 2
5
VCCSENSE
PR81 2 71.5K_0402_1%
1 7 16 CSN1_CPU
4
3
2
1
4
3
2
1
TIME CSN1
PC52
10KB_0603_5%_ERTJ1VR103J
2 1 9 12 FB_CPU 1 2
2
47P_0603_50V8J PC53 CCV FB
PR82 1 2 11 10 CCI_CPU PC54 0.22U_0603_16V7K
C 499_0402_1% REF CCI C
1
PR83 0_0402_5%
1 2 3 22 LX2_CPU PR86 0_0402_5% 放放Choke附附 PR85
5 PSI# PSI LX2
PR84 0_0402_5% 1 2 0_0402_5%
+3VS 2 24 DL2_CPU
PWRGD DL2 @ PR87 1K_0402_1% @ PC56 1000P_0402_50V7K
2
2
0_0603_5%
1 23 1 2 1 2 CPU_VCC_SENSE
CLKEN PGND2
PR88
2
1
VRHOT CSN2 @ PR95 PR92 100_0402_5%
2
4 13 3K_0603_1%
1
BSTM2_CPU
6,14,20 VGATE
4700P_0402_25V7K
4700P_0402_25V7K
1
TP @ PR94
3K_0603_1% PC58
14 CLK_ENABLE# MAX8770GTL+_TQFN40 470P_0603_50V8J
41
2
PC59
1 2 1 2
28 VR_ON 1 2
PR97
1
2
0.22U_0603_16V7K
1
0_0402_5% @ PR99 +3VS 2
PC60
10K_0402_5%
1
PR100
2
PR101 100_0402_5%
2200P_0402_50V7K
10U_1206_25VAK
10U_1206_25VAK
10U_1206_25VAK
0.1U_0603_25V7K
1
VRHOT
56_0402_5% PQ16
1
1
1
PC62
SI7686DP-T1-E3_SO8
1
PC61
PC65
PC63
PC64
B B
2
5 VSSSENSE VSSSENSE
2
2
2
PR103
PR104 0_0603_5%
1
10K_0402_5% 1 2 4
1 2 PR105
28 POUT
10_0402_5%
2
PL8
PC66 0.36UH_PCMC104T-R36MN1R17_30A_20%
2
3
2
1
0.1U_0402_16V7K 2 1
1
Rdcr
1
放放Choke附附
4.7_1206_5%
PR106
5
6
7
8
5
6
7
8
2.1K_0402_1%
FDS6676AS_SO8
FDS6676AS_SO8
1
R1
D
D
D
D
D
D
D
D
2
PQ17
PQ18
PR107
680P_0402_50V7K
Valley current limit threshold : 19.5mV ~ 25.5mV R2 R3
G
S
S
S
S
S
S
PC67
2
1
4
3
2
1
4
3
2
1
PR108 PH4
3.48K_0402_1% NTC 10KB_0603_5%_ERTJ1VR103J
Rcs = Rdcr*(R2+R3)/(R1+R2+R3)
2
1 2 1 2
2 CSN1_CPU
2 CSN2_CPU
2 CSP1_CPU
2 CSP2_CPU
1000P_0402_50V7K
1000P_0402_50V7K
1 2
1000P_0402_50V7K
PC69
PC71
1 2
Dr-Bios.com
1
1
1
放放Choke附附
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+CPU_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom JDW50/JDY70 LA3771P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, April 16, 2007 Sheet 42 of 44
5 4 3 2 1
5 4 3 2 1
clk frequency error pin error 0.1 ==> 0.2 14 Q48,Q49,Q50 pin error
2
EC add a GPIO pin EC GPIO pin modify 0.1 ==> 0.2 16 del DPST_PWM net from North Bridge
3
follow ICL50 follow ICL50 20 CRT_DET# net modify
4 0.1 ==> 0.2
5 EMI request EMI request 0.1 ==> 0.2 24 Add R477, R748
8 Blue LED issue Blue LED issue 0.1 ==> 0.2 27 BT_LED# schematic modify
9 EC GPIO pin modify EC GPIO pin modify 0.1 ==> 0.2 28 EC GPIO pin define modify
C
10 ESD request ESD request 0.1 ==> 0.2 29 reserve C895 to C904
C
11 easy short easy short 0.1 ==> 0.2 30 change J1,J2 jumper sybmol to 0603 symbol
13 chip issue chip issue 0.1 ==> 0.2 32 U31 chip update version
14 voice too small modify gain value 0.1 ==> 0.2 32 change R472 form 39k to 30k ohm
15 EMI request EMI request 0.1 ==> 0.2 32 change R523,R524,R50,R38,R26,R28 for 0 ohm to bead
17 Wireless Lan S4 fail Wireless Lan fail 0.2 ==> 0.3 26 del R756, add R757
18 Wireless Lan S4 fail Wireless Lan fail 0.2 ==> 0.3 26 change C906,C907 from 22u_1206 to 10u_0805
Lead Free non LF==>Lead Free 0.2 ==> 0.3 17 change C211,C510,C514,C216,C508,C515
19
B KBC version update KBC version update 0.2 ==> 0.3 28 reserve 0.1u at pin 124 B
20
SPDIF udpate SPDIF circuit udpate 0.2 ==> 0.3 32 add q59,q60
21
DFX DFX issue 0.2 ==> 0.3 32 del JP13
22
23
24
25
26
27
28
29
A A
30
5
Dr-Bios.com
4 3 2
Title
Size
Date:
Compal Electronics, Inc.
Document Number
PIR (HW)
JDW50
Monday, April 16, 2007
LA-3771P
Sheet
1
43 of 44
Rev
0.2
5 4 3 2 1
Charger IC damage issue Charger IC damage issue 0.2 40 Change PR162 from SD013180A80 to SD013200A80
2
Charger IC damage issue Charger IC damage issue 0.2 40 Add PR197 SD013200A80
3
Charger IC damage issue Charger IC damage issue 0.2 40 Add PR198 SD013220B80
4
5 Charger IC damage issue Charger IC damage issue 0.2 40 Add PC133 SE026473K80
6 Add EMI solution in charger. Add EMI solution in charger. 0.3 40 Add PR199 SD001470B80(S RES 1/4 4.7 1206 5%). 04/01/07 PVT
7 Add EMI solution in charger. Add EMI solution in charger. 0.3 40 Add PC163 SE074681K80(S CER CAP 680P 50V K X7R 0402) 04/01/07 PVT
8
9
C
10 C
11
12
13
14
15
16
17
18
19
B B
20
21
22
23
24
25
26
27
28
29
A A
30
5
Dr-Bios.com
4 3 2
Title
Size
Date:
Compal Electronics, Inc.
Document Number
PIR (PWR)
HCW51
Monday, April 16, 2007
LA-3121P
Sheet
1
44 of 44
Rev
0.2