IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 63, NO.
10, OCTOBER 2016
Single-Stage Bridgeless AC–DC PFC Converter
Using a Lossless Passive Snubber
and Valley Switching
Sin-Woo Lee and Hyun-Lark Do
Abstract—A single-stage bridgeless ac–dc PFC converter
using a lossless passive snubber and valley switching is
proposed. The proposed converter is based on a two-stage
bridgeless boost-flyback converter. In the proposed con-
verter, the conduction losses are reduced by removing
an input full-bridge diode rectifier. The boost inductor is
designed to be operated in the discontinuous–conduction
mode for achieving high power factor. In the flyback
module, the couple inductor that provides input–output
electrical isolation for safety is designed to be operated in
the critical-conduction mode for low RMS current and low
turn-on switching loss by using valley-switching operation.
Because of the lossless snubber circuit, the voltage spike
of switch is clamped, and the leakage inductor energy
is recycled. The snubber capacitor is used as a dc-bus
capacitor, which is divided into two capacitors. In addition,
some input power is directly conducted to the output, and
the remaining power is stored in dc-bus capacitor. So,
low-voltage rating capacitors can be used as the dc-bus
capacitor and power transfer efficiency is improved. The
presented theoretical analysis is verified on an output 48-V
and 60-Wexperimental prototype.
Index Terms—Boost-flyback converter, bridgeless con-
verter, lossless snubber, power factor correction (PFC).
I. INTRODUCTION
ITH numerous advances in industrial technology, the
W requirements of a switch-mode power supply such as
an ac–dc converter are becoming more stringent because they
require high power efficiency and low harmonic distortion. In
context of these requirements, several strategies have been stud-
ied to achieve high power factor, low-conduction losses, and
low-switching losses in ac–dc converters. Generally, the scheme
of an ac–dc converter can be classified into two stage and single
stage. Over the past few decades, a two-stage scheme com-
prising a power factor correction (PFC) stage and an output
regulation stage was usually adopted because it is easy to design
Manuscript received January 26, 2016; revised March 29, 2016; ac-
cepted April 30, 2016. Date of publication June 7, 2016; date of current
version September 9, 2016. This work was supported by the Basic Sci-
ence Research Program through the National Research Foundation of
Korea supported by the Ministry of Education, Science and Technology
(2011-0021186).
The authors are with the Department of Electronic and Informa-
tion Engineering, Seoul National University of Science and Tech-
nology, Seoul 139-743, South Korea (e-mail: weaerz@gmail.com;
hldo@seoultech.ac.kr).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TIE.2016.2577622
0278-0046 © 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications standards/publications/rights/index.html for more information.
Authorized licensed use limited to: ANNA UNIVERSITY. Downloaded on October 19,2021 at 12:19:26 UTC from IEEE Xplore. Restrictions apply.
6055
regardless of each stage and it provides very good performance
such as high power factor and low harmonic distortion. How-
ever, the control circuit is complex and the cost, component
count, and size of the converter increase because each power
stage needs a control system. In addition, the two-stage scheme
has a lower power efficiency compared to a single-stage scheme.
In the single-stage scheme, a PFC stage and an output regulation
stage are merged using shared common switches. As a result,
the total component count and size decreases and the power
efficiency increases, making the single-stage scheme suitable
for cost-effective solutions. However, the single-stage scheme
has still some major drawbacks, such as low efficiency and high
dc-bus voltage stress [1]–[5].
Several single-stage boost-flyback-type converters have been
studied in [2]–[10]. A boost-flyback converter is one of the
most popular single-stage ac–dc converters. However, these
converters need an input full-bridge diode rectifier that leads
to high-conduction losses and need for additional thermal man-
agement. Generally, conventional ac–dc converters must have a
full-bridge diode rectifier. Therefore, in order to overcome the
above-mentioned problems, many bridgeless converters have
been proposed in [11]–[19], [24], [25]. In [11], there is an inte-
grated boost PFC and half-bridge converter without a full-bridge
diode. This converter reduces the conduction loss of rectifica-
tion because of the absence of the full-bridge diode. In addition
to this problem, boost-flyback converters also face challenges
with the RCD snubber. An additional RCD snubber is usually
adopted in view of the high-voltage spikes generated in the main
switch because of the resonance between the leakage inductance
and the parasitic output capacitance of the MOSFET. However,
this RCD snubber causes additional power loss resulting in low-
ering of the total efficiency. For these reasons, various passive
snubbers for flyback converters have been studied in [20]–[22].
These studies have proposed a snubber circuit that recycles the
leakage inductor energy for high efficiency.
In a single-stage PFC converter, three types of opera-
tion modes can be adopted, i.e., continuous-conduction mode,
discontinuous-conduction mode (DCM), or critical-conduction
mode (CRM), that are characterized by the behavior of the in-
ductor. Valley switching which is zero-current- switching (ZCS)
turn-on in the MOSFET is usually utilized to operate in the CRM
mode for soft switching. It features higher efficiency than the
DCM operation because of the reduced turn-on switching loss
and the lower RMS current. In addition, CRM alleviates diode
reverse recovery when the active switch turns on because the
inductor current falls to zero [23].
6056
Fig. 1. Conventional two-stage bridgeless boost-flyback ac–dc PFC converter.
Fig. 2. Circuit diagram of the proposed converter.
Fig. 3. Equivalent circuit diagram of the proposed converter.
Given their importance, the above-mentioned challenges have
been targeted by the proposed converter, which is a single-
stage bridgeless ac–dc PFC converter using a lossless passive
snubber and valley switching. The proposed converter is based
on the conventional two-stage bridgeless boost-flyback structure
in Fig. 1. It achieves high power factor because of boost induc-
tor’s DCM operation and provides electrical isolation owing to
a coupled inductor. Also, the conduction losses of rectification
are reduced because it has no input full-bridge diode rectifier.
In the dc–dc flyback module, since the lossless snubber is used,
the leakage inductor energy is recycled into the dc–dc flyback
circuit, and the peak voltage spike of main switch is clamped
to low voltage. Moreover, since CRM operation is adopted by
using valley switching, switching loss is significantly reduced.
Therefore, the total power efficiency is improved. In addition,
the dc-bus capacitor is divided into two capacitors: snubber
Authorized licensed use limited to: ANNA UNIVERSITY. Downloaded on October 19,2021 at 12:19:26 UTC from IEEE Xplore. Restrictions apply.
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 63, NO. 10, OCTOBER 2016
capacitor and another dc-bus capacitor. Some of input energy
is immediately distributed to the load without middle process
(dc-bus capacitor) and the order energy is charged on dc-bus
capacitor. Hence, a low-voltage rating capacitor can be used as
a dc-bus capacitor and energy transfer efficiency is improved.
In conclusion, the proposed converter can provide high power
factor and achieve high power conversion efficiency.
II. CIRCUIT DESCRIPTION
A circuit diagram of the proposed converter driver is shown in
Fig. 2. The input line filter includes Lf and Cf . In the bridgeless
boost rectifier, switching devices, such as D1 , D2 , S1 , and S2 ,
are used. DS1 and DS2 are body diodes of S1 and S2 . Lb is
the boost inductor circuit. In the dc–dc flyback circuit, there
is a coupled inductor T1 , shared common switches S1 and S2 ,
LEE AND DO: SINGLE-STAGE BRIDGELESS AC–DC PFC CONVERTER USING A LOSSLESS PASSIVE SNUBBER AND VALLEY SWITCHING 6057

Fig. 4. Key waveforms of the proposed converter.

dc-bus capacitor Cdc , output diode Do , and output capacitor Co

with lossless snubber circuit including Lsn , Csn , and Dsn .
The equivalent circuit diagram of the proposed converter is
shown in Fig. 3. The input line filters are not included in this
diagram, and the input voltage is considered as constant in a
switching period. The capacitors CS1 and CS2 are the parasitic
output capacitances of S1 and S2 , respectively. The coupled
inductor T1 includes a magnetizing inductor Lm and a leakage
inductor Lk with the turn ratio n : 1(n = Np /Ns ). According to
the volt–second balance law, since the average inductor voltage
should be zero at steady state, the voltages across Csn and Cdc
are equal to Vdc . The capacitance of Csn , Cdc , and Co is large
enough to regard the voltages across them to be of a constant
value.

III. CIRCUIT DESCRIPTION

Fig. 5. Operating modes of the proposed converter.
In the proposed converter, the switches S1 and S2 are oper-
ated with the same gate signals and the converter operation is
symmetrical according to polarity of input voltage. Owing to
such symmetricity, the converter is analyzed during one switch- Mode 1 [t0 , t1 ]: At t0 , both S1 and S2 are turned ON
ing period in the positive half-line cycle of the input voltage at same time in the valley of the drain-voltage oscillation.
only. Figs. 4 and 5 show the theoretical waveforms and operat- This instance is called valley switching. Therefore, the turn-
ing modes of the proposed converter during a switching period on switching loss is reduced. Since the boost inductor voltage
Ts in the positive input voltage. There can be five modes of VL b is Vin , the boost inductor current iL b increases linearly as
operation of the proposed converter. follows:
Before t0 , the current iL b , iL m , and iL sn are zero. The par-
asitic output capacitances of S1 and S2 are discharged be-
cause of the drain-source voltage oscillation between CS1 and Vin
(Lm + Lk )//Lsn . iL b (t) = (t − t0 ). (1)
Lb

Authorized licensed use limited to: ANNA UNIVERSITY. Downloaded on October 19,2021 at 12:19:26 UTC from IEEE Xplore. Restrictions apply.
6058 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 63, NO. 10, OCTOBER 2016

The total voltage across both the components Lm and Lk is follows:

Vdc . Therefore, the iL m increases linearly as follows:
VL b = − (nVo + Vdc − VL k − Vin ) (13)
Vdc
iL m (t) = (t − t0 ). (2) VL sn = nVo − VL k (14)
Lm + Lk
Since the snubber inductor voltage VL sn is Vdc , the iL sn in- nVo Lb − (Vin − nVo − Vdc )Lsn
VL k = Ls (15)
creases linearly as follows: Lb Lsn
Vdc where 1/Ls = (1/Lk ) + (1/Lsn ) + (1/Lb ).
iL sn (t) = (t − t0 ). (3) The currents iL b and iL sn can be obtained by
Lsn
At the end of this mode, the iL b , iL m , and iL sn arrive at the iL b (t) = IL b (m id)
maximum current as follows:
−(nVo + Vdc − VL k − Vin )
Vin + (t − t2 ) (16)
IL b (m ax) = Ton (4) Lb
Lb
−(nVo − VL k )
Vdc iL sn (t) = IL sn (m id) + (t − t2 ) (17)
IL m (m ax) = Ton (5) Lsn
Lm + Lk
and then, iL b , iL m , and iL sn flow through the coupled inductor
Vdc T1 to the secondary side. Hence, the output diode current iD o is
IL sn(m ax) = Ton (6)
Lsn expressed as follows:
where Ton is the turn-on time, which is the time interval between 
−(nVo + Vdc − VL k − Vin )
t0 and t1 . iD o (t) = ID o(m ax) + n
Lb
Mode 2 [t1 , t2 ]: At t1 , both S1 and S2 are turned OFF and 
the parasitic output capacitor CS1 begins to charge. Since CS 1 −(nVo − VL k ) −nVo
+ + (t − t2 ). (18)
is assumed to be very small, the charging time is negligible. In Lsn Lm
this mode, the leakage inductor energy is stored in the snubber
Equation (18) shows that the boost inductor current iL b flows
capacitor Csn by the snubber diode Dsn . Therefore, the switch
through the coupled inductor T1 to the output diode Do . Hence,
voltage VS1 is clamped to 2Vdc .
some of input power is directly delivered to the load.
Since the boost inductor voltage VL b is −(2Vdc − Vin ), the
Mode 4 [t3 , t4 ]: At t3 , the boost inductor current iL b reaches
boost inductor current iL b decreases linearly as follows:
zero. The total voltage across both components Lsn and Lk is
−(2Vdc − Vin ) nVo . iL sn can be obtained by
iL b (t) = IL b (m ax) + (t − t1 ). (7)
Lb nVo
Since the magnetizing inductor voltage VL m is −nVo , the iL sn (t) = iL sn (t2 ) + (t − t3 ). (19)
Lsn + Lk
iL m decreases linearly as follows:
Since iL b is zero, the output diode current iD o decreases
−nVo linearly as follows:
iL m (t) = IL m (m ax) + (t − t1 ). (8)
Lm  
−(nVo − VL k ) −nVo
Since the snubber inductor voltage VL sn is −Vdc , the snubber iD o (t) = iD o (t3 ) + n + (t − t3 ).
Lsn Lm
inductor current iL sn decreases linearly as follows: (20)
−Vdc Mode 5 [t4 , t5 ]: When the output diode current iD o reaches
iL sn (t) = IL sn(m ax) + (t − t1 ). (9) zero, this mode starts. Therefore, the output diode Do is turned
Lsn
off under a ZCS condition. In this mode, VS 1 nonlinearly de-
At the end of this mode, iL b and iL sn arrive at the middle or
creases with the oscillation between CS 1 and (Lm + Lk )//Lsn .
minimum current as follows:
−(2Vdc − Vin ) IV. DESIGN PROCEDURE
IL b (m id) = IL b (m ax) + TL k (10)
Lb
A laboratory prototype of the proposed converter is designed
Vdc with the following specifications in order to prove the theoretical
IL sn (m id) = IL sn(m ax) + TL k (11)
Lsn analysis and performance of the proposed converter.
where TL k is the leakage inductor discharging time that is the 1) Input-line voltage range vin = 90 ∼ 240 [Vac ].
time interval between t1 and t2 . 2) Input-line frequency fL = 60 [Hz].
Since the output diode Do is turned on in this mode, the iD o 3) Output voltage Vo = 48 [V].
arrives at the maximum current with vary large slope as follow: 4) Output power Po = 60 [W].
  5) Minimum switching frequency fS = 60 [kHz].
nVo Vdc − nVd
ID o (m ax) = n − TL k + TL k . (12) In order to simplify the mathematical analysis for the design
Lm Lk procedure, the leakage inductor Lk and the parasitic output ca-
Mode 3 [t2 , t3 ]: When Dsn is turned OFF, this mode begins. pacitors CS 1 and CS 2 are not considered in the analysis because
In this mode, the voltages VL b , VL sn , and VL k are expressed as these values are negligible.

Authorized licensed use limited to: ANNA UNIVERSITY. Downloaded on October 19,2021 at 12:19:26 UTC from IEEE Xplore. Restrictions apply.
LEE AND DO: SINGLE-STAGE BRIDGELESS AC–DC PFC CONVERTER USING A LOSSLESS PASSIVE SNUBBER AND VALLEY SWITCHING 6059

  
A. Input Current and Power Factor 2 π −α
+ √ − tan−1 √ (27)
Fig. 6(a) shows the theoretical waveforms of the input line α 1 − α2
2 2 1 − α2
voltage vin (t), input current iin (t), boost inductor current iL b (t),
and peak boost inductor current iL b.pk (t) in a line period. The Vin.pk
α= . (28)
input line voltage vin (t) is given as Vdc + nVo
vin (ωt) = Vin.pk sin(2πfL t) (21) The input RMS current in a half-line period and the power
factor can be expressed as (29), shown at the bottom of the page
where Vin.pk is the peak input voltage and fL is the line fre-
quency. To simplify the notation, phase angle ωt is substituted Pin
PF = (30)
for 2πfL t. Vrm s Irm s
Since the boost inductor Lb operates at DCM with constant where Vrm s and Irm s are the RMS values of the input voltage
duty in one line period, the peak the boost inductor current and current.
IL b.pk follows the input line voltage vin (t) in Fig. 6(a).
The value of Ton is constant because of a fixed duty ratio in B. Output Current and DC-Bus Voltage
one line period to supply the output power for a constant output
voltage. Td , the discharging time of boost inductor is obtained The output current Io is the average output diode Do current
by ido.avg (t) in half-line period expressed as

Vin (ωt) Io = iD o(avg) (t)

Td =
nVo + Vdc − Vin (ωt)
DTS (22) 
1 π
= n(iL b.d(avg) + iL sn.off (avg) + iL m .off (avg) )dt
where Vin (t) is the rectified line voltage |vin (t)|, and π 0
D(= Ton /Ts ) is the duty cycle. To obtain D, The maximum 
n2 Vo D α 1 1
magnetizing inductor current IL m (m ax) is given by = − − + √
Lb fs π 2 π 1 − α2
Vdc nVo   
IL m (m ax) = Ton = Toff . (23) π −α
Lm Lm × − tan−1 √
2 1 − α2
From (23), the duty cycle D can be obtained as follows:
n2 Vo Le
Ton nVo + (1 − D)2 Ts (31)
D= = . (24) 2
Ts nVo + Vdc
where 1/Le = (1/Lsn ) + (1/Lm ).
The input current iin (t) is the average boost inductor current In one line period, the dc-bus capacitor current idc (t) is shown
iL b (avg) (t) during switching period Ts as follows: in Fig. 6. This current consists of iL m , iL b , and iLsn in one
iin (ωt) = iL b(avg) (ωt) = iL b.on(avg) + iL b.d(avg) switching period Ts .
The average dc-bus capacitor current idc.avg (t) in half-line
1 (Ton + Td ) period is expressed as
= IL b.pk (ωt)
2 Ts 
1 π
Vin.pk D2 Ts |sin(ωt)| idc.avg (t) = (iL m .on(avg) − iL sn.off (avg) − iL b.d(avg) )dt
= . (25) π 0
Vin . p k
2Lb 1− V d c +n V o |sin(ωt)| Vdc 2 nVo nVo D
= D Ts − (1 − D)2 Ts −
The average input power in a half-line cycle can be calculated 2Lm 2Lsn Lb fs
as 
 α 1 1
1 π × − − + √
Pin = vin (ωt)iin (ωt)dt π 2 π 1 − α2
π   
0
 π −1 −α
× − tan √ = 0. (32)
Vin.pk 2 D2 Ts π sin2 (ωt) 2 1 − α2
= dωt (26)
2πLb 0 1 − α |sin(ωt)|
Since idc.avg (t) should be zero, Vdc is constant value and it is
 π
sin2 (ωt) 2 π always higher than Vin.pk due to a structure of boost converter.
dωt = − − 2
0 1 − α |sin(ωt)| α α From (26), (31), and (32), assuming that Pin is Po , and following

 π
1
Irm s = iin 2 (ωt)dt
π 0
   
nVo D 2α 2α(2α2 − 1) π −α
= 1+ + √ − tan−1 √ (29)
2Lb fs π(1 − α ) π(1 − α2 ) 1 − α2
2 2 1 − α2

Authorized licensed use limited to: ANNA UNIVERSITY. Downloaded on October 19,2021 at 12:19:26 UTC from IEEE Xplore. Restrictions apply.
6060 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 63, NO. 10, OCTOBER 2016

Fig. 6. Theoretical waveforms for analysis power factor, dc-bus capacitor, and output current in a line period. (a) Theoretical waveforms for analysis
power factor. (b) Theoretical waveforms for dc-bus capacitor and output current.

equation can be obtained: From (31), the output power can be obtained by

2Vin.pk Le 2 1 2 Pout = Vo Io
Vdc = − − + √ 
Lb π α πα 1 − α2 n3 Vo 2 α α 1 1
   = − − + √
π −α Lb fs π 2 π 1 − α2
× − tan−1 √ . (33)   
2 1 − α2 π −1 −α
× − tan √
Equation (33) clearly shows that Vdc is regardless of the load 2 1 − α2
condition. Le Vdc 2 2
+ D Ts . (36)
4
C. Design of the Inductors Lb , Lsn , and Lm
The directly delivered power, Pdirect , is given by follows:
From (26), assuming that the efficiency of the proposed con-
Le Vdc 2 2
verter is 100%, i.e., Pin = Po , the boost inductor Lb should be Pdirect = Pout − D Ts . (37)
determined as 4
√
 By substituting Po = 100 [W], n = 3, Vdc = Vpk = 90 2, Lsn
Vin.pk 2 D2 π sin2 (ωt)
Lb = dt (34) = Lm = 1.2 [mH], TS = 16 [μs], and Vo = 48V into (33), the
2πPo fs 0 1 − α |sin(ωt)|
directly delivered power is calculated as 38.13 W.
√
where fs is the switching frequency. When n = 3, Vpk = 90 2
[V] and Vdc = Vpk [V], and Lb = 534[μH] is calculated from E. Voltage Stress of Devices
(34). In the proposed converter, the maximum voltage of
From (33), Le should be determined as S1 , S2 , D1 , and D2 is clamped by 2Vdc . In addition, the voltage
Lb Vdc stress of snubber diode Dsn is 2Vdc . The voltage stress of output
Le =
   . diode Do is Vo + Vdc /n.
Vin.pk − π4 − 2
+ √4 π
− tan−1 √ −α
α π α 1−α 2 2 1−α 2
(35) V. EXPERIMENTAL RESULTS
Hence, Lsn and Lm can be calculated from the relation
The laboratory prototype of the proposed converter is im-
1/Le = (1/Lsn ) + (1/Lm ). In order to reduce high-conduction
plemented and tested with the specifications discussed in de-
loss from the large ripple current of Lm , large turn ratio is se-
sign procedure. The designed parameters and selected com-
lected for large Lm ; however, √this causes large leakage induc-
ponents of the laboratory prototype are listed in Table I. For
tance. When n = 3, Vpk = 90 2 [V] and Vdc = Vpk [V], and
the power switching devices, SPP60N60C3 is used by S1
Lb = 534 [μH], Le = 0.675 [mH] is calculated from (35). If
and S2 , MUR860 is used by D1 and D2 , and RF2001T4S
Lsn is equal to Lm , Lsn = Lm = 1.35[mH] is obtained.
is used by Do . The boost inductor Lb is divided into two
inductors Lb1 and Lb2 in the same half of boost inductance
D. Output Power and Directly Input Power to reduce the common-mode noise. Therefore, both inductors
In the conventional two-stage boost-flyback PFC converter, Lb1 and Lb2 are selected as 255 μH. The magnetizing in-
the input energy is delivered through two-stage process. How- ductance Lm is selected as 1.2 mH. The Leakage inductance
ever, the proposed converter immediately transfers some of the Lk is 4 μH. In the snubber circuit, BYR29X-800 is used by
input energy to the load and the dc-bus capacitor is charged by Dsn and the snubber capacitor and inductor are selected as
the remaining energy. 47 μF and 1.2 mH, respectively. The value of capacitor Cdc

Authorized licensed use limited to: ANNA UNIVERSITY. Downloaded on October 19,2021 at 12:19:26 UTC from IEEE Xplore. Restrictions apply.
LEE AND DO: SINGLE-STAGE BRIDGELESS AC–DC PFC CONVERTER USING A LOSSLESS PASSIVE SNUBBER AND VALLEY SWITCHING 6061

Fig. 7. Experimental waveforms at vin = 110 [Va c ]. (a) vin , iin , iL b , and Vd c . (b) vg s1 , v S 1 , iL b , and iL s n . (c) v D o and iD o .

Fig. 8. Experimental waveforms at vin = 220 [Va c ]. (a) vin , iin , iL b , and Vd c . (b) vg s1 , v S 1 , iL b , and iL s n . (c) v D o and iD o .

and Co are selected as 45 and 1410 μF, respectively. The con- TABLE I
DESIGNED PARAMETERS AND COMPONENTS
trol circuit is implemented with the voltage-mode pulse-width OF THE LABORATORY PROTOTYPE
modulation controller NCP1607 from On Semiconductor.
IR2110S was used as a gate driver from international recti-
Component Value Description
fier for same gate signal of both switches. Since zero current
is detected by the bias winding of the coupled inductor T1 , the Input L f 1.38 m H EI3329S, Liz wire (32/ϕ0.12)
filter C f 0.1 μF 630 V
off-time is almost constant during the line cycle. Boost inductor 255 μH (30T) EI3329S, Liz wire(32/ϕ0.12)
The experimental waveforms of vin , iin , iL b , and Vdc at L b 1 (= L b 2 )
110[Vac ] and 220[Vac ] are, respectively, shown in Figs. 7(a) Rectifier diodes MUR860 600 V/20 A
D1 , D2
and 8(a). It can be observed that the phase of the input current Main switches SPP20N60C3 600V/20A, Rd s on = 0.19 Ω
is similar to that of the input line voltage and a high power fac- S1 , S2
DC-bus 47 μF 450 V
tor is achieved. However, iin is not perfectly sinusoidal because capacitor C d c
this distortion depends on the ratio of Vin.pk /(Vdc + nVo ). The Snubber 1.2 m H (48T) EI3329S, Liz wire(32/ϕ0.12)
distortion will be reduced at relatively higher dc-bus voltage inductor L s n
Snubber diodes RF2001T4S 430V/20A ultra-fast diode
values. Figs. 7(b) and 8(b) show the experimental waveforms of Dsn
vg s1 , vS 1 , iL b , and isn at 110[Vac ] and 220[Vac ]. These wave- Snubber 47 μF 450 V
capacitor C s n
forms show that Lb operates in DCM. Since Lsn and Lm operate Coupled L m = 1.2 m H, L k = 1.4 μH EI3329S, Liz wire
in CRM, the switching loss of MOSFET is significantly reduced. inductor T 1 N p : N s : N a = 48T : 16T : 11T (15/ϕ0.10) N 1 p ,
(32/ϕ0.12) N 1 s , N a
At high-input voltage, the leakage inductor discharging time is Output diodes RF2001T4S 450 V/20 A
shorter than low-input voltage condition because voltage across Do
leakage inductor is higher. Figs. 7(c) and 8(c) show the exper- Output capacitor 470 μF x3 100 V
Co
imental waveforms of vD o and iD o at 110[Vac ] and 220[Vac ]. Control IC NCP1067 Voltage-mode CRM controller
Because ZCS of the output current iD o is achieved, the reverse- Gate Driver IR2110S High- and low-side MOSFET
driver
recovery problem of output diode is alleviated. Moreover, it
shows that the direct power transfer is achieved.
Fig. 9 shows the efficiency and power factor of the pro-
posed converter. To verify efficiency improvement, the pro- low-switching loss, direct transfer of power, and recycling of
posed converter is compared with the proposed converter with leakage inductor energy, the proposed converter achieves higher
a RCD snubber and its nonbridgeless version. The efficiency efficiency. The power factor of the proposed converter is
and power factor were measured at 60 W according to the input marginally higher than a conventional converter. The efficiency
line voltage vin . Owing to low-conduction loss of rectification, and dc-bus voltage trajectory of the proposed converter under

Authorized licensed use limited to: ANNA UNIVERSITY. Downloaded on October 19,2021 at 12:19:26 UTC from IEEE Xplore. Restrictions apply.
6062
Fig. 9. Measured efficiency and power factor according to input line
voltage vin at 60 W.
Fig. 10. Measured efficiency and dc-bus voltage at 110 [Va c ] and
220 [Va c ]. (a) Efficiency under different output power P o . (b) DC-bus
voltage under different output power P o .
different output values of power Po at 110 [Vac ] and 220 [Vac ]
are shown in Fig. 10(a) and (b), respectively.
VI. CONCLUSION
A single-stage bridgeless ac–dc PFC converter using a loss-
less passive snubber and valley switching has been proposed.
In order to reduce conduction losses, input full-bridge diode
rectifier has been removed from the converter circuit. Using the
boost PFC circuit in DCM operation, a high power factor has
been achieved. In the dc–dc flyback circuit for electrical iso-
lation, the turn-on switching loss has been reduced by using
Authorized licensed use limited to: ANNA UNIVERSITY. Downloaded on October 19,2021 at 12:19:26 UTC from IEEE Xplore. Restrictions apply.
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 63, NO. 10, OCTOBER 2016
valley-switching operation. In addition, because of the loss-
less snubber circuit, the peak voltage stress of switch has been
clamped and the leakage inductor energy has been recycled.
The dc-bus capacitor is split up into two capacitors, owing to
the snubber capacitor. In addition, some of input power at the
boost inductor is directly conducted to the output. Hence, a
low-voltage rating capacitor can be used. Therefore, the total
efficiency of power conversion is improved.
REFERENCES
[1] G. Moschopoulos and P. Jain, “Single-phase single-stage power-factor-
corrected converter topologies” IEEE Trans. Ind. Electron., vol. 52, no. 1,
pp. 23–35, Feb. 2005.
[2] D. D.-C. Lu, H. H.-C. Iu, and V. Pjevalica, “A single-stage AC/DC
converter with high power factor, regulated bus voltage, and output
voltage,” IEEE Trans. Power Electron., vol. 23, no. 1, pp. 218–228,
Jan. 2008.
[3] H. S. Athab, D. D.-C. Lu, and K. Ramar, “A single-switch AC/DC sfly-
back converter using a CCM/DCM quasi-active power factor correction
front-end,” IEEE Trans. Ind. Electron., vol. 59, no. 3, pp. 1517–1526,
Mar. 2012.
[4] C. Qiao and K. M. Smedley, “A topology survey of single-stage power fac-
tor corrector with a boost type input-current-shaper,” IEEE Trans. Power
Electron., vol. 16, no. 3, pp. 360–368, May 2001.
[5] J.-J. Lee, J.-M. Kwon, E.-H. Kim, W.-Y. Choi, and B.-H. Kwon, “Single-
stage single-switch PFC flyback converter using a synchronous rec-
tifier,” IEEE Trans. Ind. Electron., vol. 55, no. 3, pp. 1352–1365,
Mar. 2008.
[6] Y. Jang, D. L. Dillman, and M. M. Jovanovic, “A new soft-switched PFC
boost rectifier with integrated flyback converter for stand-by power,” IEEE
Trans. Power Electron., vol. 21, no. 1, pp. 66–72, Jan. 2006.
[7] Y.-C. Li and C.-L. Chen, “A novel primary-side regulation scheme for
single-stage high-power-factor AC–DC LED driving circuit,” IEEE Trans.
Ind. Electron., vol. 60, no. 11, pp. 4979–4986, Nov. 2013.
[8] J.-Y. Lee, “Single-stage AC/DC converter with input-current dead-zone
control for wide input voltage ranges,” IEEE Trans. Ind. Electron.,
vol. 54, no. 2, pp. 724–732, Apr. 2007.
[9] M. H. L. Chow, Y.-S. Lee, and C. K. Tse, “Single-stage single-switch
isolated PFC regulator with unity power factor, fast transient response,
and low-voltage stress,” IEEE Trans. Power Electron., vol. 15, no. 1,
pp. 156–163, Jan. 2000.
[10] L. Huber and M. M. Jovanovic, “Single-stage single-switch input-current-
shaping technique with reduced switching loss,” IEEE Trans. Power Elec-
tron., vol. 15, no. 4, pp. 681–687, Jul. 2000.
[11] W.-Y. Choi and J.-S. Yoo, “A bridgeless single-stage half-bridge AC/DC
converter,” IEEE Trans. Power Electron., vol. 26, no. 12, pp. 3884–3895,
Dec. 2011.
[12] H.-Y. Tsai, T.-H. Hsia, and D. Chen, “A family of zero-voltage-
transition bridgeless power-factor-correction circuits with a zero-current-
switching auxiliary switch,” IEEE Trans. Ind. Electron., vol. 58, no. 5,
pp. 1848–1855, May 2011.
[13] H. L. Cheng, Y.-C. Hsieh, and C.-S. Lin, “A novel single-stage high-
power-factor AC/DC converter featuring high circuit efficiency,” IEEE
Trans. Ind. Electron., vol. 58, no. 2, pp. 524–532, Feb. 2011.
[14] C.-M. Wang, “A novel zero-voltage-switching PWM boost rectifier with
high power factor and low conduction losses,” IEEE Trans. Ind. Electron.,
vol. 52, no. 2, pp. 427–435, Apr. 2005.
[15] A. A. Fardoun, E. H. Ismail, N. M. Khraim, A. J. Sabzali, and M. A.
Al-Saffar, “Bridgeless high-power-factor buck-converter operating in dis-
continuous capacitor voltage mode,” IEEE Trans. Ind. Appl., vol. 50,
no. 5, pp. 66–72, Sep./Oct. 2014.
[16] J.-W. Yang and H.-L. Do, “Bridgeless SEPIC converter with a ripple-free
input current,” IEEE Trans. Power Electron., vol. 28, no. 7, pp. 3388–3394,
Jul. 2013.
[17] J.-W. Shin, S.-J. Choi, and B.-H. Cho, “High-efficiency bridgeless flyback
rectifier with bidirectional switch and dual output windings,” IEEE Trans.
Power Electron., vol. 29, no. 9, pp. 4752–4762, Sep. 2014.
[18] L. Huber, Y. Jang, and M. M. Jovanovic, “Performance evaluation of
bridgeless PFC boost rectifiers,” IEEE Trans. Power Electron., vol. 23,
no. 3, pp. 1381–1390, May 2008.
LEE AND DO: SINGLE-STAGE BRIDGELESS AC–DC PFC CONVERTER USING A LOSSLESS PASSIVE SNUBBER AND VALLEY SWITCHING
[19] B. Su, J. Zhang, and Z. Lu, “Totem-pole boost bridgeless PFC rectifier
with simple zero-current detection and full-range ZVS operating at the
Boundary of DCM/CCM,” IEEE Trans. Power Electron., vol. 26, no. 2,
pp. 427–435, Feb. 2011.
[20] A. Abramovitz, T. Cheng, and K. Smedley, “Analysis and design of for-
ward converter with energy regenerative snubber,” IEEE Trans. Power
Electron., vol. 25, no. 3, pp. 667–676, Mar. 2010.
[21] A. Abramovitz, T. Cheng, and K. Smedley, “State-plane analysis of re-
generative snubber for flyback converters,” IEEE Trans. Power Electron.,
vol. 28, no. 11, pp. 5323–5332, Nov. 2013.
[22] S. Jung and G.-H. Cho, “Transformer coupled recycle snubber for high-
efficiency offline isolated LED driver with on-chip primary-side power
regulation,” IEEE Trans. Ind. Electron., vol. 61, no. 12, pp. 6710–6719,
Dec. 2014.
[23] L. Huber, B. T. Irving, and M. M. Jovanovic, “Effect of valley switch-
ing and switching-frequency limitation on line-current distortions of
DCM/CCM boundary boost PFC converters,” IEEE Trans. Power Elec-
tron., vol. 24, no. 2, pp. 339–347, Feb. 2009.
[24] H. Ma, C. Zheng, W. Yu, and J.-S. Lai, “A single-stage integrated
bridgeless AC/DC converter for electrolytic-less LED lighting applica-
tions,” Int. J. Circuit Theory Appl., vol. 43, no. 6, pp. 742–755, Jun.
2015.
[25] H. Ma, C. Zheng, W. Yu, B. Gu, J.-S. Lai, and Q. Feng, “Bridgeless
electrolytic capacitor-less valley-fill AC/DC converter for offline twin-bus
light-emitting diode lighting application,” IET Power Electron., vol. 6,
no. 6, pp. 1132–1141, 2013.
Authorized licensed use limited to: ANNA UNIVERSITY. Downloaded on October 19,2021 at 12:19:26 UTC from IEEE Xplore. Restrictions apply.
6063
Sin-Woo Lee received the B.S. and M.S. de-
grees from Seoul National University of Sci-
ence and Technology, Seoul, South Korea,
in 2014 and 2016, respectively, where he is
currently working toward the Ph.D. degree in
electronic engineering.
His research interests include power factor
correction, ac–dc/dc–dc power converters, soft-
switching power converters, renewable energy
conversion, and LED lighting.
Hyun-Lark Do received the B.S. degree
from Hanyang University, Seoul, South Korea,
in 1999, and the M.S. and Ph.D. degrees
in electronic and electrical engineering from
Pohang University of Science and Technol-
ogy, Pohang, South Korea, in 2002 and 2005,
respectively.
From 2005 to 2008, he was a Senior Re-
search Engineer with the PDP Research Labo-
ratory, LG Electronics, Inc., Gumi, South Korea.
Since 2008, he has been with the Department
of Electronic and Information Engineering, Seoul National University of
Science and Technology, Seoul, South Korea, where he is currently a
Professor. His research interests include the modeling, design, and con-
trol of power converters, soft-switching power converters, resonant con-
verters, PFC circuits, and driving circuits for plasma display panels.