9806
10, OCTOBER 2019
A Single-Stage Single-Switch Soft-Switching (S6)
Boost-Flyback PFC Converter
Alireza Abasian , Student Member, IEEE, Hosein Farzanehfard , Member, IEEE, and Sayed Amir Hashemi
Abstract—This paper presents a single-stage single-switch soft-
switching (S6) power factor correction (PFC) converter to enhance
the current shaping performance and reduce the total harmonic
distortion. This improvement is achieved by the aid of an auxiliary
winding which is used to lower the input current harmonics and
also achieve soft-switching condition. As a result, the switching
losses are reduced and harmonic content of the input current is
improved noticeably in comparison to the conventional S6 PFC
converter. Also, the total number of semiconductor elements is
reduced in the proposed topology which results in lower cost and
higher efficiency. The operating modes of the proposed converter
are discussed in detail and the design procedure is presented. A
200-kHz prototype of the proposed converter is implemented and
the obtained results are provided to verify the converter theoretical
analysis and operation.
Index Terms—AC–DC converter, dc–dc converter, power factor
correction (PFC), single-stage, soft switching.
I. INTRODUCTION
N RECENT years, power conversion equipments connected
I to the grid are constantly increasing. In order to manage
the problems associated with the harmonic pollution of power
conversion equipment and fulfil the harmonic current limits set
by standards like IEC61000-3-2 [1], it is imperative to develop
power-factor correction (PFC) techniques [2]–[4]. Thus, major
research has been carried out to address the aforementioned
issues and develop high-performance PFC converters [2]–[10].
Two-stage cascade PFC converter which consists of a PFC
stage and dc–dc stage is an approach to achieve a smooth output
voltage in conjunction with a high power factor. By using sepa-
rate controllers, these converters can achieve high performance
input current shaping and output voltage regulation. However,
the major drawback of this type of PFC is its high cost due to
high device count (of at least two switches and a separate con-
troller for each stage) [3]. In order to overcome this problem,
single-stage PFC converters are developed in which the current
shaping and the dc–dc stages are combined [3]–[10]. In most
single stage structures, the dc–dc stage switch, together with
other elements, act as the current shaping stage. Single stage
PFC converters are commonly used in low-power applications,
Manuscript received July 13, 2018; revised October 3, 2018 and December
1, 2018; accepted January 18, 2019. Date of publication January 24, 2019; date
of current version June 28, 2019. Recommended for publication by Associate
Editor M. Duffy. (Corresponding author: Hosein Farzanehfard.)
The authors are with the Department of Electrical and Computer Engi-
neering, Isfahan University of Technology, Isfahan 8415683111, Iran (e-mail:,
abasian@ieee.org; hosein@cc.iut.ac.ir; s.amir.hashemi@ec.iut.ac.ir).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TPEL.2019.2895116
0885-8993 © 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 34, NO.
such as LED drivers [2], [6], ballast circuits [7], [8], and battery
chargers [9], [10].
These converters operate under either continuous conduction
mode (CCM) or discontinuous conduction mode (DCM) [11],
[12]. Operating the converter under DCM allows the input in-
ductor current to depend only on the input voltage and not on
the previous cycle parameters which can eliminate the current
control loop of current shaping stage and simplify the control
circuit and also, make it possible for the dc–dc stage to achieve
fast output regulation. On the other hand, operating under CCM
condition produces less high-order harmonics that means higher
efficiency is possible in CCM [12]. In the proposed topology,
the DCM operation is selected due to self-PFC characteristic
and also other desired features which are discussed.
Soft switching methods are applied to single-stage PFC con-
verters to improve the efficiency and further increase the oper-
ating switching frequency [13]–[22]. However, soft-switching
characteristic in these converters is mostly achieved by using
additional switches and other circuit components which results
in more complicated control scheme and extra cost [14]–[18]. In
addition to these drawbacks, the loss associated with the newly
added circuit is another concern in such methods. Neverthe-
less, some of these PFC converters like boost flyback converters
proposed in [16], [17] are not capable of achieving full soft
switching condition.
In order to overcome the above-mentioned shortcomings, the
idea of single stage-single switch-soft switching (S6) PFC con-
verters are developed [13], [19]–[22] which achieve soft switch-
ing condition without any extra switch and only by adding few
passive components and/or extra diodes. An integrated SEPIC-
flyback PFC converter is proposed in [19] as an LED driver.
However the converter only achieves soft-switching at turn-ON.
S6 LED drivers proposed in [20] and [21] are capable of achiev-
ing low total harmonic distortion (THD) but they have high num-
ber of components. Moreover, they do not achieve soft switching
condition at switch turn OFFwhich degrades their efficiency. In
[22] a single-stage isolated power-factor-corrected power sup-
ply is introduced which uses a regenerative clamping to reduce
the voltage stress and to recycle the energy trapped in the leak-
age inductance. However, same as [20] and [21] it suffers from
high number of semiconductor components and not achieving
soft-switching condition at turn-OFF.
In [13], a boost flyback S6 PFC converter is proposed in which
the same extra elements used to provide soft switching at turn
OFF, are employed to replace the switch of current shaping stage
[Fig. 1(a)]. As a result, a fully soft-switched PFC is obtained with
no additional switch, simple control system while no additional
losses are imposed. Also, this converter has fewer elements
when compared to its counterparts, but its boost inductor charge
ABASIAN et al.: SINGLE-STAGE SINGLE-SWITCH SOFT-SWITCHING (S6) BOOST-FLYBACK PFC CONVERTER
Fig. 1. (a) S6 PFC converter of [13]. (b) Proposed S6 PFC converter.
time depends on the input voltage value and thus varies with the
input voltage amplitude. To lower the input-current THD, it is
preferred that the charge time of boost inductor be dependent
only on the converter duty cycle [11].
To overcome the drawback of the S6 converter in [13], a new
S6 converter with fewer semiconductor elements is proposed
in this paper. The harmonic content of the proposed converter
fulfills the IEC61000-3-2 class D harmonic current limits and is
noticeably lower than that of the converter in [13]. The proposed
converter is fully soft-switched and also the leakage inductance
energy is recovered to improve the converter efficiency. In ad-
dition, the leakage inductance of the flyback transformer is em-
ployed as the resonant inductance while no extra switch is used.
Furthermore, the switch zero voltage switching (ZVS) turn-OFF
is resulted to eliminate the high voltage spike on switch at turn-
OFF instant which reduces losses, electromagnetic interference,
and the switch voltage stress. A prototype of the proposed con-
verter is implemented to verify the converter theoretical analysis
and operation.
II. PROPOSED CONVERTER
A. Description of the Idea
Fig. 1(b) illustrates the schematic of proposed converter.
The converter consists of a boost inductor (LB ), dc-link ca-
pacitor (CB ), output capacitor (Co ), resonant capacitor (Cr ),
power MOSFET (Sw), input bridge diode rectifier, high frequency
diodes (D1 , Do ), and a three-winding transformer (T ) where
Np , Ns , and Na denote the primary, secondary, and auxiliary
windings number of turns respectively. To simplify the theoret-
ical analysis, it is assumed that all semiconductors components
are ideal, the voltage of dc-link capacitor is almost constant and
also during a switching period, the input voltage is constant due
to high switching frequency and low-line frequency.
In the proposed S6 PFC, the auxiliary winding (Na ) is con-
nected in series with the boost inductor. This formation allows
controlling the boost inductor voltage and shaping its current
which results in lowering the THD. Also the auxiliary wind-
ing diode in [13] is eliminated in the proposed topology which
improves the efficiency and simplifies the converter.
The input inductor (LB ) operates in DCM, similar to the
converter of [13] in order to have intrinsic PFC characteristic.
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9807
The input voltage–current characteristic of a boost converter in
DCM mode is as follows [11]:
 
D2 Ts vin (t)Vo D 2 Ts 1
iin (t) = = vin (t) (1)
2LB Vo − vin (t) 2LB 1 − v in (t) Vo
where D is the converter duty cycle, vin (t) and iin (t) respec-
tively denote the input voltage and current. Also Vo is the output
voltage and Ts is the switching period. The relation between vin
and iin depends on duty cycle and vin to vo ratio. Even if the
output voltage is assumed greatly higher than the peak of the
input voltage, the relation between vin and iin is nearly linear,
only if the duty cycle is fixed and then the converter would have
an inherent PFC property. Thus, if the charge time of the boost
inductor varies with time, then the relation between vin and iin
is not linear enough anymore which leads to intense amount of
harmonic content. It should be noted that (1) is derived from
the inductor volt–second balance. In the converter of [13], the
boost inductor is charged through a circuit which consists of a
rectified input voltage source and Cr . Thus, the charge time of
LB depends on the input voltage and because the input voltage
is time variant, the charge time of the boost converter varies
with time. This results in deformation of the input current with
increased THD. Also, as soft-switching and even PFC operation
of this converter depends on the input voltage (charging voltage
of the resonant capacitor), the performance would reduce no-
ticeably by varying input voltage. To solve these problems, the
circuit should be improved in such a way that the input inductor
current is proportional to the switch ON time.
To overcome the above-mentioned problem, a new S6 PFC
is proposed as illustrated in Fig. 1(b). In this converter, the
auxiliary winding (Na ) is connected in series with the boost
inductor (LB ) to form a PFC cell together with the resonant
capacitor (Cr ). This special connection of the auxiliary winding
in addition to a proper design can result in the appropriate control
of the input inductor voltage. Controlling the inductor voltage
would lead to controlling its charge and discharge states. Also
due to presence of bulk capacitor voltage (VC B ) in the charging
loop and its almost constant voltage, the effect of input voltage
variations on converter performance is reduced.
B. Operating Principles
In the proposed converter, both LB and Lm are designed to
operate under DCM condition. This would simplify the control
circuit by eliminating the current shaping control loop. The
proposed converter operating modes in one switching period are
illustrated in Fig. 2 and the steady-state theoretical waveforms
are shown in Fig. 3.
Stage 1 (t0 –t1 ): This mode starts when the switch is turned
ON under zero current switching (ZCS) due to DCM operation
of the inductor LB and also the transformer leakage induc-
tance. Diodes D1 and Do are reversed biased and LB starts
charging, while VC B is applied to Lm and causes the magnetiz-
ing inductance current (Im ) to increase linearly. Concurrently,
Cr which has a negative initial voltage is being charged by
the input inductor current and its voltage increases until it be-
comes equal to VC B at the t1 . The bulk capacitor current (IC B )
can be obtained by the ampere-turns of transformer. The trans-
former is modeled with an ideal transformer plus a magnetizing
9808
Fig. 2. Topological operating modes of proposed converter. (a) Stage 1.
(b) Stage 2. (c) Stage 3. (d) Stage 4. (e) Stage 5. (f) Stage 6. (g) Stage 7.
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 34, NO. 10, OCTOBER 2019
Fig. 3. Steady-state analytical waveforms.
inductance.
IC B = −(Im + (Na /Np )IL B ). (2)
The current of power switch is equal to sum of IC B and LB
current (Isw = IL B − IC B ). As discussed later, LB operates
under DCM condition and due to the transformer leakage in-
ductance, IC B gradually increases from zero, thus the switch
current slowly rises from zero which indicates ZCS operation
of the power switch as illustrated in Fig. 3.
Stage 2 (t1 –t2 ): This interval begins when D1 starts conduct-
ing and fixes the voltage across LB (VL B ) at a certain value
which can be obtained from the below equation
VL B = Vin + VN a − VC r = Vin + (Na /Np − 1)VC B . (3)
As discussed before, in the proposed converter, the aim is to
keep LB in charging mode till the switch turns OFF. To keep LB
in charging mode, its voltage must be positive regardless of the
input voltage value, thus at the worst case (Vin = 0)
(Na /Np − 1)VC B ≥ 0 ⇒ Na ≥ Np . (4)
It is not desired to choose Na > Np because it increases the
switch current stress and the transformer cost. For this reason,
choosing Na = Np is the most suitable case. The power switch
ABASIAN et al.: SINGLE-STAGE SINGLE-SWITCH SOFT-SWITCHING (S6) BOOST-FLYBACK PFC CONVERTER
Fig. 4. Proposed topology to eliminate the repeatable resonance between C r
and L l k .
current can be written as below
Isw = (Na /Np )IL B + IL m .
Stage 3 (t2 –t3 ): This mode starts when the switch is turned
OFF under zero voltage switching (ZVS) due to Cr which is
placed in parallel with the primary winding of transformer (Np )
and then slowly discharges in Lm . This feature is achieved due
to the direct connection of Cr to power switch and fixed voltage
of VC B . In this state, VL B is equal to
VL B = Vin − VC B + (Na /Np )VC r .
Thus, until VC r reaches N N p (VC B − Vin ), VL B is positive and
a
the input inductor current is still increasing and then starts re-
ducing. Due to the large size of Lm and small size of Cr , the
input inductor charge time in this interval is very short and thus
it can be assumed that the input inductor current starts reducing
after turning OFF the switch. As described before, this results
in lower harmonic content of input current. Resonant capacitor
N
continues its discharge until its voltage decreases to − N ap Vo and
then Do starts conducting.
Stage 4 (t3 –t4 ): At t3 , Do starts conducting under ZCS due
to the transformer leakage inductance (Llk ) which begins to
resonant with Cr . When the resonant capacitor current (iC r )
becomes equal to LB current (IL B ), D1 current reaches zero.
Stage 5 (t4 –t5 ): After D1 turns OFF, Lm starts discharging
into the load and LB is also still discharging into the bulk
capacitor. This state ends when both LB and Lm are totally
discharged. It does not matter which one discharges first but,
here it is assumed that Lm is totally discharged first. This mode
indicates the converter DCM operation.
At this time, Cr is charging due to its positive current and
when its voltage reaches N N p (VC B − Vin ), D1 starts conduct-
a
ing again and a new resonance between Cr and Llk would
start and it would end when IC r becomes equal to IL B . How-
ever due to discharge of LB , this resonance is damped faster
than the previous stage and with lower voltage and current.
Note that the resonant energy is basically recovered and has a
minute contribution to the converter losses. The appearance of
the resonance at this mode depends on many factors such as the
input voltage, the values of LB and Cr , the transformer param-
eters, and the load. If Lm totally discharges before the voltage
of Cr reaches N N p (VC B − Vin ), the new resonance would not
a
happen. In order to totally eliminate this resonance, a diode can
be placed in series with the primary winding as shown in Fig. 5.
By doing so, after half a resonance period, the resonant cur-
rent reaches zero and D2 would turn OFF and disconnects Cr
from the circuit. Then, D1 continues its conduction until LB
is totally discharged. However, in addition to the extra cost of
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9809
Fig. 5. Input inductance voltage in one switching period.
(5)
the new diode and its conducting loss, the conducting time of
D1 increases which contributes to lowering the efficiency. Also,
as discussed later, it can increase the switch-current stress and
thus, in general, placing this new diode is not recommended.
Stage 6 (t5 –t6 ): In this stage, LB is still discharging into the
bulk capacitor. This mode ends when LB is totally discharged
which indicates the DCM condition.
Stage 7 (t6 –t0 ): The output capacitor continues to supply the
(6) load in this stage while LB is being charged very slowly. As can
be observed in Fig. 2(g) a loop consists of LB , Lm , Cr , and CB
and the input source is formed which due to the high size of Lm
and opposite direction of VC B with the rectified input voltage,
a very slow charging occurs as illustrated in Fig. 3.
In this stage Cr is in series with LB and its voltage is being
increased. As a result, the initial value of VC r at the beginning
of the next stage is higher and reaches VC B faster which would
reduce the time interval of the first stage. Consequently, soft-
switching condition is provided even at low duty cycles and
limits the extra current stress on the switch. Also, the sum of
IL B and IL m which is equal to the switch current is zero because
they are equal with opposite directions, thus the slow charge of
LB in this mode, would not affect the switch ZCS operation. It
should be noted that by adding the diode D2 to the topology, the
input inductor never charges in this mode, because D2 prevents
the formation of the discussed current loop in Stage 7 and thus
the advantages of decreasing the initial voltage of Cr is not
achieved.
III. ANALYTICAL ANALYSIS
The average
 π input power (Pin ) can be obtained from its defi-
nition ( π1 0 Vm sin(ωt)Iin dωt). Also Iin can be approximately
obtained from the boost inductor peak current (IL B peak )
Iin = IL B ave = 0.5IL B peak (D + d2 ) (7)
where d2 T is the discharge time of the input inductor. Fig. 5
illustrates the voltage of LB and by using its discharge time,
IL B peak is obtained as follows:
Na
IL B peak = [(VC B + Vo − |Vin |)/LB ]d2 Ts . (8)
Ns
By using the above equation, Pin can be calculated by
Vm d2 (D + d2 ) Na π
Pin = [VC B + Vo − Vm ]. (9)
πLB fs Ns 4
The output power of a DCM flyback converter is [13]
Po = Vo2 /R = (VC2B /2Lm )D2 Ts . (10)
9810 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 34, NO. 10, OCTOBER 2019

Fig. 5 (and some estimation), d2 can be obtained

VC B + |VC r 0 | Vin + VC B ( N
N p − 1)
a

d2 = d1 + D
2(VC B + N N s Vo − Vin )
a
VC B + N
N s Vo − Vin
a

(14)
where d1 T is time interval of Stage 1 (from switch turn ON to
diode D1 turn ON) which can be observed in Fig. 5. Solving (13)
and (14) simultaneously result in finding VC B and d2 . However,
the values of d1 and VC r 0 in (14) are still unknown and must
be determined. It is mentioned in Stage 1 that d1 Ts is the time
that the voltage of resonant capacitor rises from VC r 0 to VC B .
In this stage, VC r equation can be written as below with respect
to the initial conditions

VC r (t) = (VC B + Vin ) − (VC B + Vin + |VC r 0 |)cosωt (15)

√
where ω is the resonant frequency and is equal to 1/ LB Cr .
Thus, d1 can be determined by using VC r (d1 Ts ) = VC B

Vin
d1 = fs LB Cr cos−1 . (16)
VC B + Vin + |VC r 0 |

Adjusting the amount of d1 is very important in the converter

design. In order to achieve full soft-switching characteristic the
charge time of resonance capacitor (d1 T ) should be smaller
than switch turn ON time (DT ). As it can be observed in (16),
the amount of d1 depends on input, output and bulk capacitor
voltage, and also the passive components (LB and Cr ). This
 indicates that, based on input voltage range, the converter should
Fig. 6. V C B versus (a) n 1 = L m /L B and (b) input voltage.
be designed somehow to meet d1 T ≤ DT condition. So, by
proper design of transformer (which results to reducing VC B or
Thus, output voltage can be calculated as VC r 0 ) and adjusting LB or Cr , the amount of d1 can be modified
to achieve full soft-switching characteristic.
 VC r 0 is voltage of Cr after its resonance with Llk (by ne-
Vo = R/(2Lm fs )DVC B . (11)
glecting the discharge in Stage 7), so with respect to the initial
conditions, VC r 0 can be determined
By assuming ideal efficiency and substituting the output voltage
from (11) into (9), then 
VC r t 6 = −(Na /Ns )Vo
   VC r 0 : (17)
Vm d2 (D + d2 ) Na R π IC r t 6 = (Na /Np )IL B peak + IL m peak .
Pin = VC B + DVC B − Vm
πLB fs Ns 2Lm fs 4
Thus, VC r 0 can be shown as
= Po . (12)
Na
Thus, the VC B equation can be obtained as VC r 0 = − Vo
Ns
     
Llk Na VC B + N as Vo − |Vin |
N
Na R π VC B
KVC2B − 1+ D VC B + Vm = 0 (13) − d2 + D Ts .
Ns 2Lm fs 4 Cr Np LB Lm
(18)
2
where K is defined as 2V m LπmLdB2D(D +d 2 ) . Now VC B can be
obtained from (13) by estimating d2 (for example d2 ≈ D ). It can be observed from (18), VC r 0 depends on the turns ratio
Analysis shows that the result is very much dependent on VC2B and the output
 voltage as well as Llk /Cr . This means a high
coefficient (K) and due to the inverse relationship of K with amount of Llk /Cr can significantly increase the initial res-
VC B , it can be concluded that increasing LL mB and Vm leads to onant capacitor voltage and thus, high leakage inductance and
reduction of K which increases VC B . The mentioned deduc- small resonant capacitance are not recommended. Now that the
tions are examined by simulation and the results are illustrated relations of d1 and VC r 0 are obtained, the exact amount of d2
in Fig. 6. Using the volt–second balance of LB with the aid of and VC B can be found by solving (13) and (14) simultaneously.

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ABASIAN et al.: SINGLE-STAGE SINGLE-SWITCH SOFT-SWITCHING (S6) BOOST-FLYBACK PFC CONVERTER 9811

TABLE I
PROTOTYPE CIRCUIT ELEMENTS

Fig. 7. Photo of 160-W sample prototype.

IV. DESIGN GUIDELINES

A. Input Inductor (LB )
To design LB , (8) can be used


Na
LB = VC B + Vo − |Vin | /IL B peak d2 Ts . (19)
Ns
Since ( N
N s Vo − |Vin |) is much smaller than VC B . Also d2 max is
a

smaller than (1 − Dmax ), thus

LB < [(1 − Dmax )/(IL B max fs )]VC B min . (20)

B. Magnetizing Inductance (Lm )

Lm can be obtained from (10)
 
VC2B 2 V2 d2min
Po = η d Ts ⇒ Lm = η C B max . (21)
2Lm 2f Po

C. Transformer Turns Ratio (Ns /Np )

Turns ratio can be designed from the gain of the flyback
converter [17] by assuming minimum dc-bus capacitor voltage
(VC B min ) and maximum duty ratio (dmax )
Vo = (Ns /Np )(D/D2 )VC B ≈ (Ns /Np )(D/(1 − D))VC B .
(22)
Thus, the turns ratio can be obtained as
Ns /Np ∼
= (Vo /VC B min )((1 − dmax )/dmax ).
V. EXPERIMENTAL TEST RESULT
A. Description of Test Setup
In this section in order to validate the performance of the
proposed topology and also verify the analytical approach, a
prototype of the proposed converter is realized as observed in
Fig. 7. The input voltage is 110Vrms ± 15% and the output volt-
age is 40 V with 10 Ω output load, resulting in 160 W output
power. Due to soft switching behavior of the proposed topology,
high switching frequencies can be selected thus, the switching
frequency is selected as 200 kHz. Other circuit elements are
chosen based on the aforementioned analytical approach and
design guidelines as shown in Table I.
B. Test Results
The experimental results are provided in Figs. 8 and 9. The
input current (which its ripple is filtered through a LC filter)
Fig. 8. Input voltage/input current for 110 V rms input voltage.
is illustrated in Fig. 8. The result shows an almost sinusoidal
input current which verifies the current shaping performance
of the proposed topology. The LC filter selected is the same
as the converter proposed in [13], however, due to converters
(23) different switching frequencies, the passive components sizes
are adjusted. Voltage and current of the power switch can be
observed in Fig. 9(a) which indicate ZCS turn ON and ZVS turn
OFF of the power switch.
The current and voltage waveforms of diodes Do and D1 are
shown respectively in Fig. 9(b) and (c) in which the zero voltage
zero current switching operation of Do can be observed. Also it
can be observed that the maximum voltage stress of D1 occurs
after the switch is turned ON due to initial voltage of Cr and
then reduces fast due to charging of Cr in a short interval of the
switching period. Also the maximum current stress of D1 occurs
after the switch is turned OFF due to the resonance of Cr and Llk .
Voltage of Cr is shown in Fig. 9(d) which illustrates the fast
rise of this voltage from its initial value (VC r 0 ) to its final value
(VC B ) in almost one-tenth of the switching period and thus the
soft-switching condition can be achieved for duty cycles higher
than 0.1. For this reason the minimum duty cycle is set at 0.1 as
observed in Table I.
Converter THD and detailed current harmonic content of the
proposed converter are presented in Fig. 10. Fig. 10(a) verifies

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9812
Fig. 9. Current/voltage of: (a) switch, (b) D o , (c) D 1 , and (d) voltage of C r .
the compliance of the proposed converter with class D of IEC
61000-3-2 Standard under three different line voltages (93.5,
110, and 126.5 Vrms ) and illustrates that the harmonic content of
the proposed topology is noticeably lower than the S6 converter
of [13]. Also, a comparison between the proposed converter
under different line voltages and the S6 converter of [13] in
terms of THD can be observed in Fig. 10(b) which indicates
lower THD of proposed converter.
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 34, NO. 10, OCTOBER 2019
Fig. 10. (a) Measured harmonic content of the input current under different
line voltages. (b) THD comparison. (c) Efficiency under different output powers
for different line voltages at 200-kHz operating frequency.
It should be mentioned that as the PFC operation and even soft
switching condition of the S6 converter of [13] greatly depends
on the input voltage, the performance considerably drops by the
input voltage variation and thus the results are only presented
for nominal voltage. Also as observed from Fig. 10(c), the ef-
ficiency improves by increasing the output power and therefore
the maximum efficiency which is almost 92%, occurs at max-
imum output power (nominal power). In addition, it should be
noted that at higher input voltages, both voltage and current
stress of circuit elements in [13] would increase which intensi-
fies the losses.
Table II presents a comparison in case of circuit elements
and performance between the proposed topology, the S6 PFC
of [13], conventional single-stage PFC converters [3], [4] and
other similar S4 (single-stage soft-switching) PFC topologies
in low-power applications [14]–[16]. Since the conventional
single-stage PFC converters do not have soft-switching charac-
teristics, a conventional single-stage PFC converter [23] (quasi-
boost converter) together with an LCD snubber [24] is also
compared with the proposed S6 converter. As observed, only the
proposed topology, the S6 PFC in [13] and quasi-boost converter
with LCD snubber achieve soft-switching condition without any
additional switch. Since all the compared topologies are boost-
ABASIAN et al.: SINGLE-STAGE SINGLE-SWITCH SOFT-SWITCHING (S6) BOOST-FLYBACK PFC CONVERTER
TABLE II
DIFFERENT SOFT SWITCHING BOOST FLYBACK TOPOLOGIES COMPARISON
flyback type, all sources of power loss in the proposed converter
and the counterpart converters in Table II are very close except
for the switching loss, thus, only the switching loss compari-
son is provided. Also, in comparison with other topologies, the
proposed topology has fewer components and more importantly,
less current harmonic content (THD = 6.8%) which verifies the
theoretical analysis. Furthermore, by designing Na < Np , the
switch current stress is lower than other topologies.
VI. CONCLUSION
This paper proposes an improved S6 PFC converter in order
to improve the input current THD. The harmonic content of the
proposed converter fulfills class D harmonic current limits of
IEC61000-3-2 Standard and is noticeably lower than the con-
ventional converter. Also soft switching is provided only by an
auxiliary winding and a resonant capacitor without any extra
switch to reduce the total number of components in compari-
son with similar soft switching PFC converters. Low number
of components and soft-switching operation of the converter
has contributed to the converter efficiency improvement. Also,
simple control circuit is required since the converter operates in
DCM. A 200-kHz prototype of the proposed converter is real-
ized and the experimental results confirm the theoretical analysis
and the performance of the proposed topology.
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