Design theory and fabrication process of 90nm Unipolar-CMOS
Jyi-Tsong Lin1, Hsuan-Hsu Chen1, Kuan-Yu Lu1,
Chih-Hung Sun , Yi-Chuen Eng1, Chih-Hao Kuo1, Po-Hsieh Lin1, Tung-Yen Lai2, Fu-Liang Yang2
1
1
Department of electrical engineering, National Sun Yat Sen University, No.70 Lien-Hai Rd, Kaohsiung 80424, Taiwan ROC
2
National Nano Device Laboratories, Hsinchu 30078, Taiwan
Phone: (886) 7-5252000-4122 Fax: (886) 7-5254199 E-mail: jtlin@ee.nsysu.edu.tw
Abstract
The innovative basic punchthrough theory for the unipolar-CMOS is
for the first time presented and the first unipolar-CMOS inverter has been
fabricated successfully by using the 90nm technology developed in
Taiwan National Nano Device Lab. The severe scaling issues with silicon
can be further use and no more serious. The low-performance P-FETs can
be get rid of and switch much faster both for high-electron-mobility III-V
and CNT based technology. According to the measurement two empirical
models, the new concept of the load line drawing and the optimum design
of the unipolar-CMOS are also illustrated. Employing them for
unipolar-CMOS design, the desired high performance ultimate SOC and
SOP system can be easily realized.
Introduction
Continued semiconductor scaling faces new obstacles arising from the
limits of lithography, the cost of fabrication, and transistor sizing [1]. The
most effective response is to simplify the process and develop the
ultra-short wave-length lithography. Beyond these standard approaches,
this work considers how non-ideal effects such as punch through (PT) and
drain induced barrier lowering (DIBL) can improve CMOS chip function.
Because the mobility of electrons is higher than holes, and because
n-wells and p-wells require physical separation, a unipolar-CMOS [2] that
employs only NMOS transistors holds promise for extreme scaling. The
difficulty, however, is that complementary logic is not easily
implemented with only NMOS logic gates. But, by utilizing the
nondestructive effects of DIBL and PT, we have, for the first time,
invented and realized a unipolar- CMOS logic device. DIBL is exploited
to enhance charge/discharge triggering, because, when Vin = 0 and VDs ≤
V(logical-1)-V(logical-0), the difference between Ioff(0) and Ioff(1) is
sufficiently large. Concerning the PT effect: Fig. 1 illustrates that, when
Vin = 0, Q1 is off because Vin < Vth and Q2 is on because the source and
drain depletion regions are punched through. This PT current aids the
charging/pull-up process; when Vin = 1, Q1 is on because Vin is larger than
Vth and Q2 is off because the gate controlled depletion region holds off the
punch-through between the source/drain depletion regions. The inversion
channel current of Q1 is employed for the discharging/pull-down process.
It is worthwhile nothing that Q1 possesses low Vth whereas Q2 possess
high Vth. Fig. 2 gives details of how these unipolar transistors operate.
Fig. 2 shows the unipolar-CMOS device examined in this paper. It uses
two 90 nm NMOS transistors: Q1 is fabricated normally but Q2 has a
recessed source/drain. The design of Fig. 2 is significant, because it is the
first functional unipolar-CMOS devices to be built. Nonetheless, it is not
optimized, and, in our research, we have uncovered multiple alternative
structures that will be examined in the future.
Device Fabrication
Fig. 3 summarizes the key process steps. A 6” (100) bulk silicon wafer
was used as the starting material with the same masks used in
conventional CMOS. It is based on the NDL 90nm CMOS fabrication
technology including local oxidation of silicon (LOCOS), Vth / APT
implant, gate patterning, Halo implantation, lightly doped drain (LDD)
shallow junction, SiN MSW, S/D implantation, rapid thermal annealing
(RTA), TEOS ILD, M1 patterning and sintering. There were some
modifications, such as differing the thickness of gate oxide (GOX) and
recessing the 300 Å S/D of the load NMOS. To achieve the different GOX
thickness, 100 Å of GOX was grown on the active region and then etched
back -- 80 Å for the driver NMOS and 60 Å GOX for the load NMOS,
respectively. Concerning the recessed S/D, it was achieved after the
implementation of the gate pattern. The mask of a conventional PMOS
process is used for the load NMOS. The gate oxide was firstly etched out
and then the S/D regions were anisotropically etched down 300 Å to form
the recessed regions. The remaining process steps follow the conventional
CMOS fabrication process, as presented in Fig. 3. The final TEM
cross-section image of the unipolar device is shown in Fig. 4.
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Results and Discussions
Our measurements show that our proposed unipolar-CMOS device is
capable of being used in logic circuits and is faster than a conventional
CMOS logic circuit designed in the same fabrication technology. To
validate this claim, we fabricated the unipolar-CMOS device, extracted its
device parameters through physical measurement, and then provided
these parameters to the ISE tools. With these parameters, ISE TCAD
produces a result that is comparable to the physical measurement. Having
verified the effectiveness of ISE TCAD, we then can conduct further
studies of the unipolar system. Specifically, we have studied an
inverter-cluster ring counter, and found it to be faster than its conventional
CMOS counterpart. This is a new result. Furthermore, ISE TCAD can also
be used to study the unipolar circuit, so as to optimize the design. We have
validated that this is possible by comparing against other published
measurements [3-4], as shown in Table 1. This table also contains two
new empirical models for the punchthrough I-V characteristics.
Fig. 5 shows the measured and calculated (by model 2) punchthrough
current of the NMOS load. It can be seen that the two empirical models fit
the data well. Fig. 6 shows output waveforms of a unipolar-CMOS
3-input NOR gate, based on our initial experiment. Both experiment and
simulation results show that the output voltage does not reach the full
swing of Vin. Fortunately, all of the logic states are correct and have
enough swing to operation. The swing-scaling factor is attributed to, and
depends on, the device parameters as designed and fabricated. Fig. 7
shows the transfer curves of the unipolar-CMOS inverter. Two of them
are measured and the others are derived from empirical modeling,
optimized with different process and device parameters.
In this paper, we also develop a new method for drawing the load line
of a unipolar-CMOS inverter based on its CMOS connection: (IDs2 = IDs1,
VDs2 = VDD - VDs1, and VGs2 = Vin - VDs1). Firstly, we transform IDs2 (VDs2 ,
VGs2) as IDs2 (VDD - VDs1 , Vin - VDs1), then plot the IDs2 (VDs1 , VGs1) and
IDs1(VDs1 , VGs1) in the same IV figure. Next, we draw the load line based
on the same VGs1. Next, the transfer curves are drawn by following the
load line. Fig. 8 shows the load line drawing of our two punchthrough
current models and the models of [3] and [4]. The unipolar-CMOS’s load
lines are here drawn for the first time. Regardless of whether the
measurement data comes from our NDL experiment or from [3] or [4], the
unipolar-CMOS can be constructed from existing measured data -– and
the resulting unipolar-CMOS transfer characteristics can be measured, as
shown in Fig. 8.(f). This figure is drawn from the load lines in Fig. 8.(a-e).
As the device designs and fabrication process are different, the
unipolar-CMOS transfer characteristics are completely different and
exhibits different noise margins. Although we have fabricated and
realized the unipolar-CMOS, it is seen that more research can better
optimize its performance.
Conclusion
Here, for the first time, a unipolar-CMOS of 90nm gate has been
realized, along with an innovative punchthrough theory to describe it. The
technology will ease the implementation of high-electron-mobility III-V
and CNT transistors that outperform the p-FETs typically used in CMOS.
Thus, a low cost, ultra-low power, extra-high speed on-off, and high
packing density CNT, III-V and Si based SOC and SOP can be achieved.
Acknowledgments
The authors would like to thank the NSC and NDL of Taiwan, R.O.C.
under contracts NSC-98-2221-E-110-075 and NDL98-C05M2G-019.
We also thank Professor Steve Haga for his help in editing this manuscript.
References
[1] M. Haselman et al., IEEE Proceedings, vol. 98, pp. 11-38, Jan 2010.
[2] T.P. Ma, Semiconductor International, 10/8/2008.
[3] B.M. Wilamowski et al., IEEE EDL, vol. EDL-3, pp. 277-280, Oct
1982.
[4] F-C Hsu, et al., IEEE TED, vol. ED-30, pp. 1354-1359, 1983.
 (a) Inverter (b) NOR gate
Fig. 1. Operation theory of the unipolar-CMOS inverter and NOR (a) Charging at t = 0+. (b) Discharging at t = 0+.
gate comprising two NMOSs. Fig. 2. The detailed operation theory of the unipolar-CMOS sample fabricated.
Table 1
Punchthrough current models.
Model Equations
Empirical 2
I = (a×VDs +b×VDs + c)×(K1 ×VGs + K2)
Model 1 pt
Empirical I = K × (V + K × V + K ) 2
Model 2 pt 3 Ds 4 Gs 5

9 A
Ref [3] I pt = ×μ ×εsi × 3 ×(VDs − m×VGs −V0 )
2

8 L
φ min + V B
Ref [4] I pt = I 0 × exp( )
Vt
Fig. 3. Process flow sequence for the 90 nm Fig. 4. Cross-section TEM image of the fabricated
unipolar-CMOS sample fabricated. 90 nm NMOS (driver).

Fig. 5. Punch through current

characteristics: experimental (solid) and Fig. 6. The simulated output waveforms of an Fig. 7. The measured voltage transfer characteristics
calculated (hollow). Where VGs = -3, 0, and unipolar-CMOS 3-input NOR gate based on the and optimized simulation transfer curves with
3 V respectively. measurement parameters. different model parameters.

Fig. 8. The load lines associated with the (a) empirical model 1, (b) empirical model 2, (c) the model in [3] and (d) the model in [4] of punchthrough current,
and (e) empirical Model 2 with measured load and wider driver respectively, which are graphically drawn bases on the same VGs1 of IDs1 (VDs1, VGs1) and IDs2
(VDs1, VGs1) characteristics. (f) The corresponding voltage transfer characteristics associated with the above empirical models and reference models.

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