MOS

TRANSISTOR
THEORYY

2.1 Introduction

In Chapter 1 the MOS transistor was introduced in terms of its operation as

an ideal switch. In this chapter we will examine the characteristics of MOS
transistors in more detail to lay the foundation for predicting the perfor-
mance of the switches, which is less than ideal. Figure 2.1 shows some of the
symbols that are commonly used for MOS transistors. The symbols in Fig.
2.1(a) will be used where it is necessary only to indicate the switch logic
required to build a function. If the substrate connection needs to be shown,
the symbols in Fig. 2.1(b) will be used. Figure 2.1(c) shows an example of
the many symbols that may be encountered in the literature.
This chapter will concentrate on the static or DC operation of MOS tran-
Sistors. This is the first design goal that must be satisfied to ensure that logic
gates operate as logic gates. All circuits are analog in nature and the digital
abstraction only remains an abstraction as long as certain design goals are
Inet Design for timing constraints is covered in Chapter 4.
An MOS transistor is termed a majority-carrier device, in which the cur-
nt in a conducting channel between the source and the drain is modulated
a) () (c)
&voltage applied to the gate. In an n-type MOS transistor (i.e., nMOS),
jority characters are electrons. A positive voltage applied on the gate FIGURE 2.1 MOS transis
espect to the substrate enhances the number of electrons in the channel tor symbols

41
 TOR ORY
(the region immediately under the gate) and hence increases the conductivity
Or the channel. For gate voltages less than a threshold value denoted by V,
n e ehannel is cut off, thus causing a very low drain-to-source current. The
operation of a p-type transistor (i.e., pMOS) is analogous to the nMOS tran-
sistor, with the exception that the majority carriers are holes and the voltages
are negative with respect to the substrate.
The first parameter of interest that characterizes the switching behavior
of an MOS device is the threshold voltage, V. This is defined as the voltage
at which an MOS device begins to conduct ("turn on"). We can graph the rel-
ative conduction against the difference in gate-to-source voltage in terms of
the source-to-drain current ( ) and the gate-to-source voltage (Vg). These
graphs for a fixed drain-source voltage, Vdy, are shown in Fig. 2.2. It is pos-
sible to make n-devices that conduct when the gate voltage is equal to the
source voltage, while others require a positive difference between gate and
source voltages to bring about conduction (negative for p-devices). Those
devices that are normally cut off (i.e., nonconducting)) with zero gate bias
(gate voltage-source voltage) are further classed as enhancement-mode
devices, whereas those devices that conduct with zero gate bias are called
depletion-mode devices. The n-channel transistors and p-channel transistors
are the duals of each other; that is, the voltage polarities required for correct
operation are the opposite. The threshold voltages for n-channel and
p-channel devices are denoted by Vn and Vp» respectively.
n-channel enhancement
n-channel depletion
Drain
Current
Drain
Curent
ds ds
0+ Vtn - Vn
Gate-to-Source Voltage (Vgs)
Gate-to-Source Voltage (Vgs)
Gate-to-Source Voltage (Vgs
Gate-to-Source Voltage (Vas)
Vtp
0+Vtp
FIGURE 2.2 Conduction Drain
characteristics for enhance Current Drain
ment and depletion mode Ods) Current
ds)
MOS transistors (assuming
fixed Vds) p-channel enhancement
P-channel depletion
 transistors are fab-
both n-channel and p-channel
In CMOS technologies circuits, at
on the same chip.
Furthermore, most CMOS integrated
ricated of the enhancement type.
nresent, use transistors

2.1.1 nMOS Enhancement Transistor

shown in Fig.
for enhancement-type transistor,
an n-channel
The structure into which two
of moderately doped p-type silicon substrate
2.3, consists a Between
doped n" regions, the source and the drain, are diffused.
heavily substrate called the
there is a narrow region of p-type
these two regions
channel, which is by thin insulating
covered a layer of silicon dioxide (SiO,)
Over this oxide layer is a polycrystalline silicon
(polysili-
called gate oxide. is silicon that is
electrode, referred to as the gate. Polycrystalline silicon
con) the
not composed of a single crystal.
ince the oxide layer is an insulator,
of the inher-
to channel is essentially zerojBecause
DCcurrent from the gate the
distinction between
there is no physical
ent symmetry of the structure, dielec-
Since SiO, has relatively low loss and high
drain and source regions.
of high gate fields is feasible.
tric strength, the application and the
between the source
voltage is applied
In operation, a positivebias flows from source to
drain (Vds). With zero gate (Vgs 0), no current
=

insulated from each other by the

two
drain because they are effectively diode sym-
shown in Fig. 2.3 (indicated by the
reversed biased pn junctions to
a voltage applied to
the gate, which is positive with respect
bols). However,
an elèctric field E across
the substrate,
the source and the substrate, produces is
and repels holes. If the gate voltage
which attracts electrons toward the gate to n-type
under the gate changes from p-type
sufficiently large, the region conduction path
electrons) and provides a
(due to accumulation of attracted surface of the
Under such a condition, the
between the source and the drain
n-channel is applied
to be inverted. The term
underlying p-type silicon is said which shows
to the structure. This concept is
further illustrated by Fig. 2.4(a),
in a p-type silicon substrate of
the initial distribution of mobile positive holes is
much less than a voltage, V, which
an MOS structure for a voltage, Ves,

gate oxide Drain

Source Gate
+Vds

channel

holes electrons

P-substrate

FIGURE 2.3 Physical struc

Substrate ture of an nMOS transistor
(Usually VsS
 HANSISTOR THEO
ORY

ACCUMULATION

polysilicon gate
silicon dioxide insulator
O0OOOOO0OG
O000O000 0 P-substrate

O000000000
(a)

DEPLETION

- depletion region

OOO060000O
OO00000000
OO0000000
(b)

INVERSION
Vgs Vt

inversion region (n-type)

depletion region

FIGURE 2.4 Accumulation,

OOOO0000OO
Depletion and Inversion O000O00000
modes in an MOS structure.
(C)

the threshold voltage. This is termed the accumulation mode. As is raised

above V, in potential, the holes are repelled Ves
the gate. Now the structure is in causing depletion region under
a
the depletion mode
further above V, results in electrons (Fig. 2.4b). Raising Vgs
strate under the
being attracted to the region of the SuD-
gate. A conductive layer of electrons in the p substrate gives
rise to the name inversion mode (Fig. 2.4c).
T h e difference between a
diode (or between the source
pn junction that exists in a bipolar transistor O
or drain and substrate) and the inversion
layc
 2.1 INTRODUCTION 45

substrate junction is that in the pn junction, the n-type conductivity is

brought about by a metallurgical process; that is, the electrons are introduced
into the semiconductor by the introduction of donor ions. In an inversion
layer substrate junction, the n-type layer is induced by the electric field E
applied to the gate. Thus, this junction, instead of being a metallurgical junc-
tion, is afield-induced junction.
Electrically, an MOS device therefore acts as a voltage-controlled
switch that conducts initially when the gate-t0o-source voltage, Vgs is equal
to the threshold voltage, V,. When a voltage Vds is applied between source
and drain, with Vgs = V, the horizontal and vertical components of the elec-
trical field due to the source-drain voltage and gate-to-substrate voltage
interact, causing conduction to occur along the channel. The horizontal com-
ponent of the electric field associated with the drain-to-source voltage (i.e.,
Vds0) is responsible for sweeping the electrons in the channel from the
source toward the drain. As the voltage from drain to source is increased, the
resistive drop along the channel begins to change the shape of the channel
characteristic. This behavior is shown in Fig. 2.5. At the source end of the
channel, the full gate voltage is effective in inverting the channel. However,
at the drain end of the channel, only the difference between the gate and
drain voltages is effective. When the effective gate voltage (Ves- V,) is

greater than the drain voltage, the channel becomes deeper as Vgs
1S

increased. This is termed the "linear," "resistive," "nonsaturated," or "unsat-

urated" region, where the channel current Ids is a function of both gate and
drain voltages. If Vds> Vgs- V» then Vgd V, (Vgd is the gate to drain volt
age), and the channel becomes pinched of-the channel no longer reaches
the drain. This is illustrated in Fig. 2.5(c). However, in this case, conduction
of the
is brought about by a drift mechanism of electrons under the influence
the channel, they are injected
positive drain voltage. As the electrons leave
into the drain depletion region and are subsequently accelerated toward the
drain. The voltage across the pinched-off channel tends to remain fixed at

(Ves-V). This condition is the "saturated" state in which the channel cur-
rent is controlled by the gate voltage and is almost independent of the drain
voltage. For fixed drain-to-source voltage and fixed gate voltage, the factors
that influence the level of drain current, lds, flowing between source and
drain (for a given substrate resistivity) are:

the distance between source and drain

the channel width

the threshold voltage V,

the thickness of the gate-insulating oxide layer
the dielectric constant of the gate insulator
the carrier (electron or hole) mobility, u.
NSISTOR THEORY

Source Drain

Gate

n n

p-substrate

n-type channel Depletion Layer

(Inversion Layer)
0
Vgs V Vas =

(a)

Vds

Vas Vgs-VM
(Nonsaturated Mode)

b)

Vds
Vds

Vgs-V Pinch-off

n n

Vds

(Saturated Mode)
 2.1 INTRODUCTION 47

The normal conduction characteristics of an MOS transistor can be cat-

egorized as follows:

."Cut-off region: where the current flow is essentially zero (accumu-

lation region).
Nonsaturated" region: weak inversion region where the drain current is
dependent on the gate and the drain voltage (with respect to the substrate).
"Saturated" region: channel is strongly inverted and the drain current
flow is ideally independent of the drain-source voltage (strong inver-
sion region).

An abnormal conduction condition called avalanche breakdown or

can occur if very high voltages are applied to the drain.
punch-through
Under these circumstances, the gate has no control over the drain current.

2.1.2 pMOS Enhancement Transistor

So far, our discussions primarily directed toward nMOS; how-

have been
ever, a reversal of n-type and p-type regions yields a p-channel MOS transis-
tor. This is illustrated by Fig. 2.6. Application of a negative gate voltage
below the gate, resulting in the
(w.r.t. source) draws holes into the region
a conduc-
channel changing from n-type to p-type. Thus, similar to nMOS,
this instance, how-
tion path is created between the source and the drain. In
movement of holes (versus electrons) in
ever, conduction results from the
the channel. Anegative drain voltage sweeps holes from the source through
the channel to the drain.

2.1.3 Threshold Voltage

The threshold voltage, V,, for an MOS transistor can be defined as the volt

between the gate and the source of an MOS device below which
ge applied drops to zero. The word
"effec-
ne drain-to-source current Ids effectively

Source Gate Drain

-Vds

p p

electrons
n-substrate

FIGURE 2.6 Physical struc

transistor
ture of a pMOS
Substrate
(Usually VDD
CHAPTER 2 MOS TRANSISTOR THEORY

tively" is used because the drain current never really is zero

but drano.to
a
very small value that may be deemed insignifncant for the current application

(i.e., fast digital MOS circuits). In general, the threshold

ation
tion of a number of parameters including the following
voltage is a
func-

Gate conductor material.

.Gate insulation material.
Gate insulatorthickness-channel doping.
Impurities at the silicon-insulator interface.
.Voltage between the source and the substrate, Vsh

In addition, the absolute value of the threshold voltage decreases with an

increase in temperature. This variation is approximately -4 mV/°C for
high
substrate doping levels, and-2 mV/°C for low doping
levels.
2.1.3.1 Threshold Voltage Equations
Threshold voltage, V, may be expressed as

V, =
V mos+V (2.1)
where Vmos is the ideal threshold
voltage of an ideal MOS capacitor and Vz
is what is termed the flat-band
voltage. Vi-mos is the threshold where there is
no work function difference between
the gate and substrate materials.
The MOS threshold
voltage, V-mos,
is calculated by considering the
MOS capacitor structure that forms the gate of the MOS transistor (see tor
example or). The ideal threshold voltage may be expressed as

V-mos 20,t (2.2)

where N . o x 1S the oxide capacitance

and , =
/2,4N 20, which is called the bulk
charge term.
The symbol o, is the bulk
potential, a term that
accounts for the doping ot
substrate. It represents the difference
between the Fermi energy level
doped semiconductor and the Fermi of
tor. The intrinsic energy level of the intrinsiç semiconduc
level is midway between the
valence-band edge and the
 the
of the In a p-type semiconductor
semiconductor.
dauction-band edge semiconductor it
the valence band, while in an n-type
nlevel is closer to of carriers in the doped
the conduction band. N is the density
loser to concentration in intrinsic
s
substrate, and N; is the carrier
semiconductor
semiconduc.

at 300°K. The lowercase

kis
to 1.45 x 10 cm
silicon. N; is equal
(undoped)silicon., is
(undoped) constant 10-23
(1.380x Tis the temperature (°K) and q
J/°K).
Boltzmann's 10Coulomb). The expression kTlq equals
(1.602 x
the electronic charge
the electronic
is the permittivity of silicon
(1.06x 10
02586 Volts at 300"K. The
term
Es which is inversely
term ox 1s the gate-oxide capacitance,
Farads/cm). The thickness (tox). The threshold voltage, V-mos
is
oronortional to the gate-oxide
pr n-transistors and negative for p-transistors.
positive for is given by
The flatband voltage, V
(2.3)
V ns
flat-band voltage. The term represents the fixed
Qfc
The term V is the silicon-
surface states that arise due
to imperfections in the
charge due to term oms is the work
function difference
and doping. The
Oxide interface substrate (pate-Osi),
which may
material and the silicon
between the gate normal way for an n tran-
calculated for an n" gate over a p substrate (the
be
sistor) as follows:"

(2.4a)
+0)-0.9v (N 1x10 cm3)
=

Ps-
where
T
1.16--.704 x 10 110n
E =
is the band gap energy of silicon|
on an n-substrate (a nor-
and Tis the temperature (°K). For an n poly gate
mal p-transistor)

-4,) - -0.2V (N 1x10'

cm3) = (2.4b)
PM-
ms

and substrate mate-

Fron seen that for a given gate
m these equations it may be the doping concentra-
threshold voltage may be varied by changing
the (Cox), or the surface state
the substrate (N), the óxide capacitance
of mentioned above may be
fc). In addition, the temperature'variation
seen.
threshold voltage of
tis to adjust the native (original)
n M ten necessaryTwo common techniques
used for the adjustment of
the
th device. the silicon-
voltage entail varying the doping concentration at
eshold Voltage
 -ISTOR THEORY

sulator interface through ion implantation (i.e.. affecting Qf) or using dif.
rent insulating material for the gate (i.e., affecting Co). The former
proach introduces a small doped region at the oxIde/substrate interface
at adjusts the flat-band voltage by varying the 2jc term in Eq. (2.3). In the
tter approach for instance, a layer of silicon nitride (Si3N4) (relative per.
ittivity of 7.5) is combined with a layer of silicon dioxide (relative permit.
vity of 3.9), resulting in an effective relative permittivity of about 6, which
substantially larger than the dielectric constant of SiO2. Consequently, fo
e same thickness as an insulating layer consisting of only silicon dioxide,
he dual dielectric process will be electrically equivalent to a thinner layerof
i02, leading to a higher Cor value.
In order to prevent the surface of the silicon from inverting in the
egions between transistors, the threshold voltage in these field regions is
ncreased by heavily doped diffusions, by implants of the silicon surface, or
y making the oxide layer very thick. MOS transistors are self-isolating as
ong as the surface of the silicon can be inverted under the gate, but not in the
gions between devices by normal circuit voltages.

Cxample
1. Calculate the native threshold voltage for an n-transistor at 300°K for
a process with a Si substrate with NA = 1.80x 10°, a SiO, gate oxide
with thickness-200 A. (Assume o,ms -0.9V, efe 0.)
=

.02586 ln 18x10
1.45x100
= .36 volts

ith COx

.9x 8.85x104
0.2 x 10
=
1.726 x 10 Farads/cm2

2e aN ?0
 2.2 MOS DEVICE DESIGN EQUATIONS 51

2.1.4 Body Effect

As we have seen so far, all devices
comprising an MOS device are made on
a common substrate. As a result, the substrate
voltage of all devices is nor-
mally equal. (In some analog circuits this may not be true.) However, in
d2
arranging the devices to f orm gating functions it might be necessary to con-
g2T2
nect several devices in series as shown in
Fig. 2.7 (for example, the NAND
gate shown in Fig. 1.6). This may result in an increase in s2 Vsb2#0|
source-to-substrate
voltage as we proceed vertically along the series chain d1A

Under normal conditions-that is, when (Vsb| 50, Vsb2 # 0). V2

width remains constant and charge carriers are
Ves> V-the depletion-layer s1 Vsb1 =0
V1
pulled into the channel from
the source. However, as the substrate bias Vs (Vsource - substrate) is
increased, the width of the channel-substrate
depletion layer also increases, Vi2» Vi1
resulting in an increase in the density of the trapped carriers in the
layer. For charge neutrality to hold, the channel charge must decrease.depletion
The FIGURE 2.7
The effect of sub
resultant effect is that the substrate voltage, Vsh, adds to the channel-
strate bias on
substrate junction potential. This increases the
The overall effect is an increase in the threshold
gate-channel voltage drop. series-connected n-
voltage, V, (V2> Vi1). transistors

2.2 MOS Device Design Equations

2.2.1 Basic DC Equations
As stated previously, MOS transistors have three regions of operation:
Dr.AIT LIB
Cutoff or subthreshold region.
Nonsaturation or linear region.
.Saturation region.
755
Theideal (irst order, Shockley) equations6.7.8 describing the behavior ofa
nMOS device in the three regions are:
The cutoff region:

as=0 VSV, (2.5a)

he
nonsaturation, linear, or 1triode region:

B (Vg-V) Vas- 0<VasVs-V (2.5b)

Although this region is commonly called the linear region, Ids varies lin-
i t h Vgs and Vas when the quadratic term Vd,/2 is very small (i.e., Vas
sVg-V)
 onAIER MOS TRANSISTOR THEORY

The saturation region:

0<Vg-V,<Vds (2.5)
2

V2s
where Ids is the drain-to-source current, is the gate-to-source voltage, V, is the
device threshold, and B is the MOS transistor gain factor. The last factor is depen.
and is given by
dent on both the process parameters and the device geometry,

LE W (2.6)

where u is the effective surface mobility of the carriers in the channel, eis
the permittivity of the gate insulator, tor is the thickness of the gate insulator,
Wis the width of the channel, and L is the length of the channel. The gain
factor B thus consists of a process dependent factor HE/ tox, Wwhich contains
all the process terms that account for such factors as doping density and
gate-oxide thickness and a geometry dependent term (W/L), which depends
on the actual layout dimensions of the device. The process dependent factor
is sometimes written as uCor where Cox = E/ tox is the gate oxide capaci
tance. The geometric terms in Eq. (2.6) are illustrated in Fig. 2.8 in relation
to the physical MOS structure.
The voltage-current characteristics of the n- and p-transistors in thee non-
saturated and saturated regions are represented in Fig. 2.9 (with the SPICE
circuit for obtaining these characteristics for an n-transistor). Note that we
use the absolute value of the voltages concerned to plot the characteristics of
the p- andn-transistors on the same axes. The boundary between the linear
and saturation
regions corresponds to the condition Vds
appears as a dashed line in Fig. 2.9. The drain voltage at which the device
VgsVand

Polysilicon Gate

Drain Diftusion
SiO Source Diffusion

FIGURE 2.8 Geometric

terms in the MOS device
equation
 2.2 MOs DEVICE DESIGN EQUATIONS
53

Ngss
- IVgs-Vl= Vds!

Vds gsa
Vgs +05VV Wdsl
Vgsa
1-5
- IVgs2

Ngs FIGURE 2.9 VI characteris-

ds tics for and
n-
p-transistors

hecomes saturated is called Vdsat- or the drain saturation voltage. In the

above equations that is equal to Vgs- V

Example
Typical values (for an n-device) for current (-1) processes are as
follows:
H 500 cm/V-sec
e=3.9eg=3.9 x 885 x 107 Flcm (permittivity of silicon dioxide, S,O,)
o=200 A
Hence a typical n-device B would be

500 x 3.9x 8.85

x10 88.5HuA/V?
.2 x 103

On the other hand, p-devices have hole mobilities (,) of about 180
cmIV-sec, yielding a ß of

31.9uA/V
nus the ratio of n-to-p gain factors in this example is about 2.8. This ratio
varies from about 2 to 3 depending on the process

2.2.2 Second Order Effects

Eq represents the simplest view ofthe MOS transistor DC voltagecur
papers published on
more
cguations. There have been many researchcreated to fill a variety of
been
e d and accurate models that have and the conserva-
rements, such as accuracy, computational efficiency,and its commercial
tion f The circuit simulation program SPICE
and charge.
andnproprietary called LEVEL to spec-
PIetary derivations generally use a parameter
HAPTER 2 MOS TRANSISTOR THEORY

LEVEL I models build those defined

ify which model equations are used.
on

in Eq. (2.5) and include some important second-order effects. LEVEL 2

models calculate the currents based on device physics. LEVEL 3 is a
semiempirical approach that relies on parameters selected on the basis of
matching the equations to real circuits. The MOS device equations in terms
of the LEVEL 1 parameters used in SPICE will be covered here; Section
2.10, in this chapter, describes the LEVEL3 parameters used in the commer-
cially available HSPICE program.
First the term ue/tor (uC) is defined as the process gain factor. In
SPICE this is referred to as KP. Depending on the vintage of the process and
the type of transistor, KP may vary from 10-100 uA/V-, In addition, it is not
unusual to expect a variation of 10%-20% in KP within a given process as a
result of variations in starting materials and variation in Si02 growth.

2.2.2.1 Threshold Voltage-Body Effect

The threshold voltage V, is not constant with respect to the voltage differ-
ence between the substrate and the source of the MOS transistor. This is
known as the substrate-bias effect or body effect. The expression for the
threshold voltage may be modified to incorporate Vsbs the difference
between the source and the substrate.

V, =
+s4A
6+20,+:
20,+|V,D
Cos
,Vo7L20,+|V.-J20, (2.7)
where Vsb is the substrate bias, VMo is the threshold
voltage for Vsh = 0 (Eq.
2.1), and yis the constant that describes the substrate bias effect. The term o
is defined in Eq. 2.2.
Typical values for y lie in the range of 0.4 to 1.2. It may be expressed as

Y 24EsNA = 24e3,MA (2.8)

OX OX

in which q is the charge on an electron, Eor is the dielectric constant of the sil-
icon dioxide, Es; is the dielectric constant of the silicon substrate, and N is the
doping concentration density of the substrate. The term y is the SPICE param-
eter called GAMMA. Vo is the parameter VTO, N is the parameter NSUB,
and o,= 20, is PHI, the surface potential at the onset of
strong inversion.
 2.2 MOS DEVICE DESIG

Example
For with NA = 3x 10o cm, Tox 200Å, Eor = 3.9 x 8.85 x 101 Flcm,
=11.7x 8.85 x 107* Flcm, and q = 1.6x 10 Coulomb

0.2x 10
Y 1 0 X T0 x11.7x 8.85 x 10-14x 3 x 10!6
3.9 x8.85x 10-14**
= 57

In
(3x106
.02586
1.5x
1.5x 1010
1010
= .375

At a Vsb of 2.5 volts, and with

V2.5Vo+57 L.75+2.5 -75

Vr0+.53

Thus the threshold shifts by approximately half a volt with the source at 2.5
volts for these process parameters.
CMOS process can have a
As we shall learn in Chapter 3, the type of
and p-transistors. The increase in
large impact on this parameter for both n- which in turn leads to
threshold voltage leads to lower device currents,
slower circuits.

2.2.2.2 Subthreshold Region

also referred to as the subthresh-
The cutoff region described by Eq. (2.5a) is
exponentially with and
Vds Vgs. Although the
increases
d region, where Ids finite value of Ids may be used to
(ds 0), the
value of I4s is very small or it may adversely affect
to construct very low power circuits
vantage nodes. As an approximation,
Level
such dynamic-charge storage
Cuits as
current to 0. (See Section
2.11 for the
the subthreshold
SPICE models set
SPICE Level 3 subthreshold equations.)

2.2.2.3 Channel-length Modulation

device a s s u m e
the behavior of an MOS
Simpli
ined equations that
describe
and do not take
into a c c o u n t the varia
thatue
the carrier
Carrier mobility is constant,
in d r a i n - t o - s o u r c e voltage, Vds
to the changes
c h a n n e l length due
MOS TRANSISTOR THEORY

For long channel lengths, the influence of channel variation is of little con-
this variation should be
sequence. However, as devices are scaled down,
taken into account.
When an MOS device is in saturation, the effective channel length actu-
ally is decreased such that

Lef L-Lshort (2.9)

where

short egi
N - -Y)
The reduction in channel length increases the (WIL) ratio, thereby
increasing ß as the drain voltage increases. Thus rather than appearing as a
constant current source with infinite output impedance, the MOS device has
a finite output impedance. An approximation that takes this behavior into
account is represented by the following equation:

kW
ds2 -)2(1+AV) (2.10)

where k is the process gain factor ue/tox and a is an empirical channel-

length modulation factor having a value in the range 0.02V to 0.005V,
In the SPICE level I model A is the parameter LAMBDA.

2.2.2.4 Mobility Variation

The mobility, u, describes the ease with which carriers drift in the substrate
material. It is defined by

average carrier drift velocity (V)

Electric Field (E) (2.11)
If thevelocity, V, is given in cm/sec, and the electric field,
E, in V/cm, the
mobility has the dimensions cm/V-sec. The
of ways. mobility may vary in a number
Primarily, mobility varies according to the type of
carriers) in silicon have a much charge
Electrons carrier.
(negative-charge
than holes
(positive-charge carriers), resulting in n-deviceshigher mobility
having higher
current-producing capability than the corresponding p-devices.
decreases with increasing Mobility
The
temperature variation
doping-concentration and increasing temperature.
becomes less pronounced as the
increases. In SPICE p is doping density
specitied by the parameter UO.
 2.2 MOS DEVICE DESIGN EQUATIONs

2.2.2.5 Fowler-Nordheim Tunneling

When the gate oxide is very thin, a current can flow from gate to source or
drain by electron tunneling
through the gate oxide. This current is propor-
tional to the area of the
gate of the transistor follows:
as 4,1, l*

FNC,WLE, "x (2.12)

V
where E is the electric field across the gate oxide and
ox

E and C, are constants.

This effect limits the thickness of the

gate oxide as processes are scaled. How-
ever, it is of great use in electrically alterable programmable logic devices.

2.2.2.6 Drain Punchthrough

When the drain is at a high enough voltage with respect to the source, the
depletion region around the drain may extend to the source, thus causing cur-
rent to flow irrespective of the gate voltage (i.e., even if it is zero). This is
known as a punchthrough condition. Currently, this effect is used in I/O
pro-
tection circuits to limit the voltages across internal circuit nodes, although it
will impact design as devices are scaled down by requiring that internal cir-
cuit voltages be reduced to a point where the effect does not occur.

2.2.2.7 Impact lonization-Hot Electrons

As the length of the gate of an MOS transistor is reduced, the electric field at
the drain of a transistor in saturation increases (for a fixed drain voltage). For
SuDmicron gate lengths, the field can become so high that electrons are
mparted with enough energy to become what is termed "hot." These hot
electrons impact the drain, dislodging holes that are then swept toward the
negatively charged substrate and appear as a substrate current. This effect is
nown as impact ionization. Moreover, the electrons can penetrate the gate
e , causing a gate current. Eventually this can lead to degradation of the
MOS device parameters (threshold voltage, subthreshold current, and
sconductance), which in turn can lead to the failure of circuits.5,16,17
While the substrate current may be used in a positive manner to estimate the
Severity of the hot-electron effect, it can lead to poor refresh times in
aynamic memories, noise in mixed signal systems, and possibly latchup. Hot
noles do not
normally present a problem because of their lower mobility.
CHAPTER 2 MOS TRANSISTOR THEORY

The presence of hot electrons has guided CMOS device

engineering over
the last few years. Chapter 3 shows some examples of the process
steps that
are used to provide long-lifetime submicron devices at 5 volts. Various
circuit
techniques that aim at reducing the voltage stress at the drains of n-transistors
have also been proposed. Hot electrons will eventually push 3-volt and
1lower
power supplies into prominence in CMOS design as the reduction in drain
voltage markedly improves device lifetimes and reliability.
As an illustration of the relative
magnitude of the substrate current, the
following equation is representative° (for an L = 0.8 u, tor= 160A CMOS
process):

substrate a,C1 (Vas-Vdsa) C2 (2.13)

where

C1 2.24 x 10- .l x10Vs

C2 = 6.4

dsat Vmesa
Vm+Lesat
with

VimVs-Vn -0.13 s -0.25s

Esat1.10 x 10' +0.25 x 10'V,

efr is the effective channel length in meters.

2.2.3 MOS Models

In Section 2.2.2 we presented the ideal equations that describe the behavior of
MOS transistors. While these incorporate some nonideal effects
(channel-
length modulation, threshold-voltage variation), they may not accurately
model a specific device in a particular process. That is especially true for
devices that have very small dimensions (gate lengths, gate widths, oxide
thicknesses) as the modeling process becomes increasingly 3D in nature.
Researchers have developed and refined a wide range of MOS models in an
effort to predict more accurately the performance of MOS devices before they
are fabricated for varying
design scenarios. For instance, one might predie
DC currents very accurately from raw thus
the behavior of an
process parameters, helping predn
as yet untested device. However, because of the complexiy
 2.3 THE COMPLEMENTARY CMOS INVERTER-DC CHARACTERISTICS 61

rent, Id and the input voltage, Vgs and is defined by

8m dlds Vas
dVds = constant
(2.17)
8S

It is used to measure the gain of an MOS device. In the linear region 8m is

given by

8m (linear) = pVds
(2.18)

and in the saturation region by

Bm(sa) (V-V). (2.19)

Since transconductance must have a positive value, the absolute value is
used for voltages applied to p-type devices

2.3 The Complementary CMOS Inverter

DC Characteristics

A complementary CMOS inverter is realized by the series connection of a

p-and ann-devicetas shown in Fig. 2.11. In orderto derive the DC-transfer
characteristics for the inverter (output voltage, Vou as a function of the
inverter, Vin), we start with Table 2.1, which outlines various regions of oper-
ation for the n- and p-transistors. In this table, Vn is the threshold voltage of
the n-channel device, and Vip is the threshold voltage of the p-channel

VDD

dl P-device

Vin On-device Vout

LE FIGURE 2.11 ACMos

inverter (with substrate con-
Vss nections)
2 MOS TRANSISTOR THEORY

TABLE 2.2 Relations Between Voltages for the

Three
Regions of Operation of a CMOS Inverter
CUTOFF NONSATURATED SATURATED

Vgpp VinVp+VDD gspVp

p-device Vin<Vip+VDD
VinVp+VDD VdspVgsp-Vp VdspVgsp-Vp
Voutin-Vp VoutVinVp
VgsnV VgsnVm
n-device
VgsnVm Vinn VinVin
VinVm Vdsn<Vgs- Vm Vdsn Vgs- Vn
VoutVin-Vm VoVin-V

device. The objective is to find the variation in

output voltage (Vou) for
changes in the input voltage (Vin).
We begin with the graphical representation of the simple algebraic equa-
tions described by Eq. (2.5) for the two inverter transistors shown in Fig.
2.12(a).0 The absolute value of the p-transistor drain current Ids inverts this
characteristic. This allows the VI characteristics for the p-device to be
reflected about the x-axis (Fig. 2.12b). This step is followed by taking the
absolute value of the p-device, Vds and superimposing the two characteris-
tics yielding the resultant curves shown in Fig. 2.12(c). The
input/output
transfer curve may now be determined by the points of common V2s intersec-
tion in Fig. 2.12(c). Thus, solving for Vinn = Vinp and dsn dsp gives the
desired transfer characteristics of a CMOS inverter as illustrated in Fig. 2.13.
The switching point is typically designed to be 50 percent of the
magnitude
of the supply voltage: VpD/2. During trausition, both transistors in the
CMOS inverter are momentarily "ON," resulting in a short pulse of current
drawn from the power supply. This is shown by the dotted line in Fig. 2.13.

The operation of the CMOS inverter can be divided into five

regions (Fig.
2.13). The behavior of n- and p-devices in each of the regi»ns may be found
by using Table 2.2.

Region A. This region is defined by 0 S Vin s Vm in which the n-device is

cut off (dn= 0), and the p-device is in the
the drain-to-source current dsp for the
linear region. Since Idsn=-dsp
p-device is also zero. But for Vdsp
VoulDD. With Vdsp=0, the output voltage is

outDD (2.20)
 2.3 THE COMPLEMENTARY CMOS INVERTER-DC CHARACTERISTICS 63

gsns

Vgsn
dsn
Vgsn

Vgsn2
-VDD NdsP
-Vgsp1 Voo
Vgsn
Ngsp2 Vdsn
Vgsps dsp
-Vgsp4
-Vgsps
(a)

dsn"dsp!

Vgsp Vgsn

-Vdsp 0 Vdsn Voo

()

5
Equal Current Points

ldsndsp --- Vout

Vinn
Vinp
FIGURE 2.12 Graphical
derivation of CMOS inverter
Vden (Voo-Vdsp) characteristic
C)

Region B. This region is characterized by VmS Vin< VDD/2 in which the

in satu-
p-device is in its nonsaturated region (Vds # 0) while the n-device is
ration. The equivalent circuit for the inverter in this region can be repre-
resistor for the p-transistor and a current source for the
n-
Sented by a
 64 CHAPTER 2 MOS TRANSISTOR THEORY

p "ON" n "OFF" P OFF" n "ON"

p "ON" n "ON"

Voo

Vout 5VpD sn-dsp

.
-...
..
FIGURE 2.13 CMOS
inverter DC transfer charac- Vtn 5Voo Vpo+Vip Voo
teristic and operating regions Vin

transistor as shown by Fig. 2.14(a). The saturation current adn for the n-
device is obtained by setting Vs = Vin. This results in

(2.21)
where
eW

and

Vthreshold voltage of n-device

H= mobility of electrons
W channel width of n-device
Ln = channel length of n-device.

Region B Region C Region D

dsp

Vout dan Vout dein Vout

FIGURE 2.14 Equivalent
circuits for operating regions
 2.3 THE COMPLEMENTARY CMOS INVERTER-DC CHARACTERISTICS 65

The Current for the p-device can be obtained by noting that

gs (Vin-VDD)
and

Vds (VoutVpp)
and therefore

(outVpD).2.22)
ap-Pp(Vin-VpD-Vp) (VoVpn) 2

where

ox

and

Vp threshold voltage of p-device

Hmobility of holesS
Wchannel width of p-device
Lp=channel length of p-device.

Substitutingg
dsp dsn
as
be expressed
the output voltage Vut Can

VpD
-""pD- (V-V2
ou(Vin-V,)+(Vn-V-2(
(2.23)
are in saturation. This is
n- and p-devices
Kegion C. In this region both the
Fig. 2.14(6) which shows
two current
represented by the schematic in
sources in series.
two devices are given by
The saturation currents for the

dp Vin-Vp»-V2
6 CHAPTER2 MOS TRANSISTOR THEORY

anVV,)
I asn

with

dsp dsn
This yields

VDD+ Vp+Vn
Vin (2.24)
P

By setting

B B and Vn -Vpr
we obtain

Vin (2.25)
which implies that region C exists
only for one value of Vin. The possible
values of Vout in this region can be deduced as follows:
n-channel: Vin -

Voutn
VousVin-V
p-channel: Vin -

Vout> Vp
VotVin-Vp
Combining the two inequalities results in

(2.26)
Vin-VinVoutVin-Vp
This indicates that with Vi= ,VVaries within the range shown.
course, we have assumed that af MOs device in saturation behaves like a"
ideal current source with drain-to-source current
being independen 1as a
In reality, as Vds increases, Id, also increases slightly; thus regio two
ninite slope. The significant factor to be noted is that in region Cwe
nall
current sources in series, which is an "unstable" condition. Thus a >
small
 2.3 THE COMPLEMENTARY CMoS INVERTER-DC CHARACTERISTICS

input voltage has a large effect at the output. This makes the
very steep, which contrasts with the
output transition
equivalent nMOS inverter characteris-
tic. (See Section 2.4.) The relation defined
by Eq. (2.24) is particularly useful
since it provides the basis for defining the
gate threshold Vin which corre-
sponds to the state where Vout Vin-This region also defines the "gain" of the
CMOS inverter when used as a small signal
amplifier.
Region D. This region is described by VpD/2 < Vin S Vpp + Vp The
p-device is in saturation while the n-device is operating in its nonsaturated
region. This condition is represented by the equivalent circuit shown in Fig.
2.14(c). The two currents may be written as

dsp ,(Yn -Voo-V,

and

V 21
aun B,(u-V,)Vu
with

dspdsn
The output voltage becomes

o(Vm)-(-V) -VDD- (2.27)

Region E. This region is defined by the inputcondition Vin Vop-p in

which the p-device is cut off Jasp =0), and the n-device isinthe linear mode.
Here, Vgsp = Vin - VpD. which is more positive than Vp. The output in this
region is

out0. (2.28)

From the transfer curve of Fig. 2.13, it may be seen that the transition
between the two states is very steep. This characteristic is very desirable
because the noise immunity is maximized. This is covered in more detail in
Section 2.3.2. For convenience, the characteristics associated with the five
regions are summarized in Table 2.3.