This article has been accepted for publication in a future issue of this journal, but has not been
fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2020.3014278, IEEE
Transactions on Power Electronics
IEEE TRANSACTIONS ON POWER ELECTRONICS
Improved Hybrid Switched Inductor/Switched
Capacitor DC-DC Converters
Behdad Faridpak, Mohammad Bayat, Mojtaba Nasiri, Rahim Samanbakhsh,
Meisam Farrokhifar, Senior Member, IEEE
Abstract—High voltage gain DC-DC converters are widely used
in various applications like low voltage sustainable sources. In
traditional boost converters, the voltage gain is limited by high
voltage stress, high current ripple, and low efficiency due to
employing a high duty cycle ratio. In this paper, we propose
converters that are a combination of four sub-structures, namely
active switched inductor, passive switched inductor, switched
capacitor cell, as well as an auxiliary switch with non-isolated
configuration. The proposed structures have high voltage gain
compared to the conventional either switched inductor-based
or switched capacitor-based ones in addition to a low duty
cycle ratio. By adding an auxiliary switch, the efficiency is
improved, particularly for high voltage gains. The principle of
operation and steady-state analysis are discussed in detail. Also,
simulation results from PSCAD/EMTDC software are validated
by a prototype built for experimental examination. The results
are demonstrated that the voltage gain and efficiency could be
improved by utilizing the auxiliary switch.
Keywords—DC-DC converter, High gain converter, Switched
Inductor/Switched Capacitor converter, Hybrid converter.
I. I NTRODUCTION
Nowadays, DC-DC converters with high voltage gain are
employed to use low voltage sources for achieving high output
voltage levels [1]. DC-DC boost converters appeared suitable
among other converters for these applications. However, in
these converters, with approaching duty cycle to unity, voltage
gain is limited due to increased conduction losses. Also, a
higher duty cycle ratio may affect efficiency, reverse-recovery,
and electromagnetic interference [2]–[4]. Besides, high voltage
gain requires high voltage components, which increase the
switching and conduction losses [5], [6]. Furthermore, the
equivalent series resistance of elements is another limitation
of a step-up voltage gain [7].
High voltage gain can be achieved by adjusting the turns
ratio of a transformer in some converters such as push-
pull, forward, flyback, full-bridge, and half-bridge. However,
leakage inductor of the transformer in these converters cause
Manuscript received March 27, 2020; revised June 25, 2020; accepted July
29, 2020. (Corresponding author: Meisam Farrokhifar.)
B. Faridpak is with the Faculty of Electrical and Computer Engineering,
University of Tabriz, Tabriz, Iran (e-mail: behdad.faridpak@gmail.com).
M. Bayat is with the Electrical Engineering Department, University of
Zanjan, Zanjan, Iran (e-mail: mohammad.bayat@znu.ac.ir).
M. Nasiri is with the Electrical Engineering Department, Amirkabir Uni-
versity of Technology, Tehran, Iran (e-mail: m nasiri@aut.ac.ir).
M. Farrokhifar and R. Samanbakhsh are with the Center for Energy Science
and Technology, Skolkovo Institute of Science and Technology, Moscow,
Russia (e-mail: rahim.samanbakhsh@skoltech.ru, m.farrokhi@skoltech.ru).
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1
high power dissipation and the high voltage spike [1], [7], [8].
To overcome these problems, a half-bridge flyback converter
with a new lossless passive snubber was proposed using an
interleaved structure in [9]. Also, the authors in [10] introduced
a passive lossless snubber to provide soft-switching conditions
for all semiconductor elements at turn on/off states.
Non-isolated DC-DC converters were introduced to elimi-
nate leakage inductor of the transformer in addition to obtain
high efficiency and low cost. These converters can be classified
as a non-coupled inductor and a coupled inductor [11]. The
size and number of magnetic components can be minimized
in non-coupled inductor type [12]–[15]. In [16], a composed
method based on using multiple capacitors in switching-mode
DC-DC converters was proposed. Due to the high voltage gain
and low duty cycle introduced in [16], high efficiency can be
expected. In [17], a switched capacitor circuit was integrated
with a boost converter, which allows a vast range of output
voltage by using multiple capacitors. However, the efficiency
of the combined structure is low for constant voltage [17].
In [18] and [19], non-isolated high step-up DC-DC convert-
ers were proposed, which utilized switched capacitor cells.
Several switched inductor techniques like adding a greater
number of switched cells can be used to obtain high voltage
gain in DC-DC converters [20], [21]. However, these structures
are complex. Also, a high voltage gain Z-source DC-DC con-
verter was proposed based on the Z-source impedance network
in [22], [23]. Nevertheless, traditional Z-source converters
have a higher voltage gain in comparison to switched boost
converters with less number of passive components [24].
In this paper, to improve practical voltage gain and re-
duce the duty cycle ratio, an auxiliary switch is added to
the conventional hybrid switched inductor/switched capacitor
converters [5], [19]. Correspondingly, three popular asymmet-
rical hybrid switched inductor (AH-SL), symmetrical hybrid
switched inductor (SH-SL), and switched capacitor switched
inductor active network converter (SC-SL-ANC) structures
have been integrated with an auxiliary switch. The stored
inductor and capacitor energies are increased to supply the
load without an additional clamping circuit by adding the aux-
iliary switch. Indeed, the proposed converters are capable of
achieving high voltage gain without utilizing additional hybrid
switched capacitor [14] neither hybrid capacitor techniques
[15]. Furthermore, in the same voltage gain, the efficiency
of the proposed converters are much higher than previous
structures.
The remainder of the paper is organized as follows. Section
II presents the structure of the proposed converters. In Section
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IEEE TRANSACTIONS ON POWER ELECTRONICS 2

III, the operation principles of the converters are explained.
The theoretical voltage gains are calculated in Section IV. In
Section V, the proposed structures are discussed in detail. Also,
the proposed converters are compared to similar converters in
Section VI. Simulation and experimental analysis are provided
in Section VII. The conclusion is the last section of this paper.
II. S TRUCTURE OF THE PROPOSED CONVERTERS
In this paper, three converters are achieved based on a
combination of active switched inductor (ASL) network [5],
passive switched inductor (PSL) network [5], switched capac-
itor (SC) cell [1], and an auxiliary switch. The structure of
the proposed converters is shown in Fig.1. The combination
of ASL and PSL networks yields two sub-structures hybrid
asymmetrical switched inductor (HASL) and hybrid symmet-
rical switched inductor (HSSL). The improved asymmetrical
hybrid switched inductor (IAH-SL) converter is composed of
an HASL and an auxiliary switch (Fig.1(a)). The improved
symmetrical hybrid switched inductor (ISH-SL) consists of an
HSSL and an auxiliary switch, which is presented in Fig.1(b).
Furthermore, the improved symmetrical hybrid switched in-
ductor switched capacitor (ISH-SL-SC) is constituted of HSSL,
an SC-cell, and an auxiliary switch shown in Fig.1(c). It is
worth mentioning that the improvement is achieved by utilizing
an auxiliary switch S3 . This switch improves the voltage gain
and efficiency explained in detail in the following sections.
III. O PERATION ANALYSIS
In this section, according to Fig. 2, the operation principle
and steady-state analysis of the proposed structures are dis-
cussed for continuous conduction mode (CCM). In this regard,
Ts = 1/fs is a switching period and fs is switching frequency.
To simplify the analysis, it is assumed that all components
are ideal. Also, inductors, capacitors, and resistors have linear,
time-invariant, and frequency independent behaviors. Since
the switching process of the three converters is similar, the
operation modes of ISH-SL-SC are just analyzed.
Mode 1 [0 ≤ t < D1 Ts ]: According to Fig. 2(a), in this
mode, the switches S1 , S2 are turned on and S3 is turned
off, simultaneously. The current of inductors L1a , L2a , L1b ,
L2b is increased linearly in parallel connection with Vin . The
capacitor C1 is charged by stored energy in C3 from previous
mode through the S1 , S2 . During this mode, diodes D1a , D1c ,
D2a , D2c , D4b are turned on and the rest of diodes are blocked.
The voltage and current equations of inductors are calculated
as (1) and (2). Also, The voltages of switched capacitors C1 ,
C2 in SC-cell are obtained from (3) and (4).
VL1a = VL1b = VL2a = VL2b = Vin (1)
∆iL1a = ∆iL1b = ∆iL2a = ∆iL2b = (Vin ∆t)/L (2)
VC1 = Vin + VC3 (3)
VC2 = Vo − VC3 (4)
Mode 2 [D1 Ts ≤ t < (D1 + D2 ) Ts ]: According to Fig. 2(b),
the switch S3 is turned on and S1 ,S2 are turned off. The current
of inductors L1a , L2a , L1b , L2b is increased linearly in series
connection with Vin . Meanwhile, the capacitors C1 , C3 have
the same voltage. In addition, the upward steep of inductors
current is lower than Mode 1. During this mode, diodes D1b ,
D2b , D3 , D4b are turned on and the rest of diodes are blocked.
Also, the amounts of voltage and current of inductors are
obtained from (5) and (6).
VL1a = VL1b = VL2a = VL2b = Vin /4 (5)
∆iL1a = ∆iL1b = ∆iL2a = ∆iL2b = Vin ∆t/4L (6)
Mode 3 [(D1 + D2 ) Ts ≤ t < Ts ]: According to Fig. 2(c), the
entire switches S1 , S2 , S3 are turned off. The stored energy in
all the switched inductors and switched capacitors is deployed
on output load Ro . During this mode, diodes D1b , D2b , D4a ,
D4c are turned on and the rest of diodes are blocked. The
following equations are obtained for this operation mode.
VL1a = VL1b = VL2a = (3Vin − Vo )/8 (7)
VC1 = VC2 = (Vin + Vo )/2 (8)
Vo = VC2 + VC3 (9)
VC3 = (Vo − Vin )/2 (10)
The main waveforms of ISH-SL-SC are illustrated in Fig.3.
IV. VOLTAGE GAIN OF THE IDEAL CONVERTER
In this section, the voltage gain of the proposed ISH-SL-
SC converter is presented. This voltage gain is derived from
operation modes and is based on the inductors’ voltage-second
balancing.
In this converter to achieve the desired operation principles,
the constraint in (11) must be satisfied.
D1 + D2 < 1 (11)
The following equations can be derived for the voltage gain
of ISH-SL-SC in CCM by using (1), (5) and (7).
8Vin D1 + 2Vin D2 + (3Vin − Vo ) (1 − D1 − D2 ) = 0 (12)
Vo 5D1 − D2 + 3
G= = (13)
Vin 1 − D1 − D2
The voltage gain of the proposed converter versus switches
duty cycles D1 and D2 is plotted in Fig. 4.
V. D ETAILED ANALYSIS AND DESIGN CONSIDERATIONS
In this section, to demonstrate the operation characteristics
of the described ISH-SL-SC, firstly, the structure is divided
into the sub-structures and are analyzed separately. Secondly,
the specifications of the output capacitors are determined.
Thirdly, the power losses and efficiency of designed converters
are calculated incorporating parasitic elements i.e., on-state
collector-to-emitter voltage drop VCE−on , switching turning-
on losses Eon and turning-off losses Eof f , on-resistance of the
switches ron , forward resistance of the diodes rD , the threshold
voltage of the diodes VF , equivalent series resistance (ESR)
of the inductors rL , and ESR of the capacitors rC .

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IEEE TRANSACTIONS ON POWER ELECTRONICS 3

SC cell D4c
L1b
D1a L1b C2
D1a Io
D4b
Iin L1a D1b Io C1
L1a D1b
L1b D1c Iin D1c D4a
D1a
S1 S2 Do
D3 S1 S2 Ro Vo
D3
Iin L1a D1b Io
D1c Vin
S3 Co Ro Vo Vin
S3 C3
S1 S2 Do
D3

Vin D2c Auxiliary D2c

S3 Co Ro Vo L2a Auxiliary
switch L2a
D2b switch
L2a D2b
D2a D2a
Auxiliary L2b L2b
HASL
switch HSSL HSSL

(a) (b) (c)

Fig. 1. Structure of the proposed improved converters including an auxiliary switch S3 . (a) IAH-SL. (b) ISH-SL. (c) ISH-SL-SC.

D4c
+ D4c
+ D4c +
L1b L1b L1b
D1a + - +
C2
-
D4b
D1a + - +
C2
-
D4b
D1a + - +
C2
D4b
-
D1b C1
- D1b C1 - D1b C1
-
+L1a - D1c D4a
+ + -
L1a
D1c D4a
+ +L1a - D1c D4a
+
S1 S2 Ro S1 S2 Ro Vo S1 S2
+ Vo
+ + Ro Vo
D3 D3 D3
+ - - -
C3
C3
- + C3
- + -
Vin
- Vin
- Vin
-
S3 S3 S3

D2c D2c D2c

- + + - + -
L2a
D2b L2a L2a
D2b D2b

D2a D2a D2a

- + + - + -
L2b L2b L2b

(a) (b) (c)

Fig. 2. Operation modes of the proposed ISH-SL-SC converter. (a) Mode 1. (b) Mode 2. (c) Mode 3.

Mode1 Mode2 Mode3

g1 ,g2 A. Sub-structures of the proposed converters
According to Fig. 1(c), the structure of the designed con-
g3 t
verter is composed of combining HSSL, SC cell, and an
auxiliary switch sub-structures. It is worth mentioning that the
t
VS1 ,VS2 design process is evaluated in CCM. Also, it is assumed that
( Vo + Vin ) / 4 the current ripple of inductors is negligible.
Vin
VS3 t
● HSSL
Vo / 2 Inductors L1a , L1b , L2a , L2b : During the Modes 1 & 2 the
inductors are charged by Vin and the variations in the inductor
VD1a,VD1c t
VD2a,VD2c currents are equal to ∆iL . Accordingly, the value of switched
( Vin - 3Vo ) / 8
inductors in the ISH-SL-SC is expressed by (14).
VD1b,VD2b t Vin
L= (4D1 + D2 ) (14)
Vin 4∆iL fs
VD4b t
Switches S1 , S2 : The design of switches is affected by
( Vo + Vin ) / 2
Vo / 2
the voltage and current stresses. Accordingly, the voltage and
VD4a,VD4c t
Vin

iL1a , i L1b t
iL2a , i L2b 100
Vo/Vin

75
50
25
0
t 0.1
0.2 0.5
0.3 0.4
D1 D2 1-D1 -D2 0.4 0.3
D2 0.5 0.2 D1
0.1
Fig. 3. Key operation waveforms of the proposed ISH-SL-SC converter for
L1a =L2a =L1b =L2b . Fig. 4. Voltage gain illustration of the proposed ISH-SL-SC converter.

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current stresses of main switches are calculated by (15) and C. Power losses and efficiency in CCM
(16). In (29)-(53) the efficiency of ISH-SL-SC is calculated by
stress
VS1,S2 = (Vo + Vin )/4 (15) assuming the ripple-free current of inductors. Therefore, the
istress conduction losses for IGBT and MOSFET is modeled by (29)
S1,S2 = (Iin + 5Io )/4 (16)
and (30), respectively.
Diodes D1a , D1b , D1c , D2a , D2b , D2c : Voltage and current
stresses of the diodes are the most important factors to design PSIGBT
con = VCE−on IS ave (29)
these devices. These stresses are calculated in (17)-(20). PSMcon
OSF ET
= ron IS2 (30)
rms
stress
VD1a,D1c,D2a,D2c = (Vo − 3Vin )/8 (17)
stress It is assumed that the switch output capacitance Cosw has
VD1b,D2b = Vin (18) linear behavior. Thus, the switching losses PS sw for IGBT
istress
D1a,D1c,D2a,D2c = (Iin + 3Io )/2 (19) and MOSFET are modeled by (31) and (32), respectively.
istress = Iin (20) PSIGBT
sw = (Eon + Eof f )fs (31)
D1b,D2b
● Auxiliary switch PSMsw
OSF ET
= (fS Cosw VS2 )/2 (32)
The voltage stress of switch S3 in ISH-SL-SC is equal to
half of the output voltage. Finally, the total power losses in switches (PS ) with neglect-
stress
VS3 = Vo /2 (21) ing drive power is calculated by the following equation.

In addition, the average current of the switch S3 is related PS = Pcon + Psw (33)
to the inductor’s current. So, the following equation is derived.
Similarly, the power losses in rD and the power losses
istress
S3 = (Iin + 5Io )/8 (22) associated with the VF are given by (34) and (35), respectively.
Also, the voltage and current stresses of D3 are the same 2
as S3 . PrD = rD ID rms (34)
● SC cell PV F = VF iD ave (35)
Capacitors C1 , C2 : The average voltage of the switched
capacitors by assuming C1 = C2 is calculated using (23). With considering (34) and (35), the total diode conduction
losses is obtained using (36).
VC1,C2 = (Vo + Vin )/2 (23)
PD = PrD + PV F (36)
According to (23), the voltage-rated of the capacitor is
extremely affected by the required voltage gain. The inductor’s losses, as indicated in (37), is related to its
Diodes D4a , D4b , D4c : According to Fig. 2, the operation ESR and current.
principles of SC diodes are related to D1 , D2 function. Hence,
the following equations are derived for voltage and current PrL = rL IL2 rms (37)
stresses of diodes.
stress The current of Co is needed to calculate power losses in the
VD4a,D4b,D4c = Vo /2 (24)
output capacitor. This current is determined by (38).
istress
D4a,D4b,D4c = Io (25)
−Io 0 ≤ t < (D1 + D2 ) TS
iCo = { (38)
B. Output capacitor iL − Io (D1 + D2 ) TS ≤ t < TS
The voltage of the output capacitor has upward steep (charg- Accordingly, the power losses of capacitor is calculated
ing) whenever either S1 , S2 , or S3 are turned on, as stated in using the following relation.
Modes 1 & 2. In contrast, as stated in Mode 3, the output
voltage has decreased while all switches are turned off. The PrC = rC IC2 rms (39)
value of the output capacitor is related to the electric charge
(Q) stored in Co . Totally, the overall power losses is obtained from (40).
∆VCo = ∆Q/Co (26) Ploss = Pd + PD + PrL + PrC (40)
Vo (D1 + D2 )
∆VCo = (27) Finally, the efficiency is calculated by (41).
fS Ro C o
Therefore, the minimum filter capacitance required to reduce Po Po
its peak-to-peak voltage below the desired level ∆VCo is η1 = = (41)
Pin Ploss + Po
Vo (D1 + D2 )max
Co ≥ Cmin = (28) The efficiency of ISH-SL-SC utilizing IGBT switches is
fS Ro min ∆VCo rewritten by voltage gain in (42). The same calculation is
It is worth noting that the output capacitor for ISH-SL-SC performed using (43) for MOSFET switches. We use different
is equal to a series of C2 and C3 (see Fig.2). letters in equations (44)-(53) to avoid lengthy equations.

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TABLE I. C OMPARISON BETWEEN THE PROPOSED CONVERTERS AND OTHER SC/SL- BASED STEP - UP STRUCTURES
Normalized
Voltage Gain No. of Components
Structure/ Ref. Voltage stress (G=Vo /Vin )
Switch Diode S D L C
ISH-SL-SC (5D1 -D2 +3)/(1-D1 -D2 ) (G+1)/4 (G-1)/8 3 10 4 3
ISH-SL (3D1 -D2 +1)/(1-D1 -D2 ) (G+1)/2 (G-1)/4 3 8 4 1
IAH-SL (2D1 +1)/(1-D1 -D2 ) (2G+1)/3 (G-1)/3 3 5 3 1
AH-SL [5] (2D+1)/(1-D) (2G+1)/3 (G-1)/3 2 4 3 1
SH-SL [5] (3D+1)/(1-D) (G+1)/2 (G-1)/4 2 7 4 1
SC-ANC [14] (D+2)/(1-D) (G+1)/4 (G+1)/4 2 3 2 3
SL-ANC [14] (2D+1)/(1-D) (D+3)/(1-D) (D+3)/(1-D) 2 3 4 1
SC-SL-ANC [19] (5D+1)/(1-D) (G+1)/4 (G-1)/8 2 9 4 3
SL/SC-SBC [15] 2(1-D)/(1-3D) 2D/(1-3D) 2D/(1-3D) 2 7 2 3
ASL-SU2C [1] (3D+1)/(1-D) 1/(1-D) 2/(1-D) 2 2 3 3
HBC [25] (3-D)/(1-D) 1/(1-D) 1/(1-D) 1 5 1 4
HSXSQ Z-source [23] (D+2)/(1-D) (G+1)/3 - 5 - 2 6
SL-Boost [18] (D+1)/(1-D) G G 1 4 2 1
SC-Boost [18] 2/(1-D) G/2 G/2 1 3 2 1
APICs-based [11] (5D+1)/(1-D) (2+G)/3 1+G 3 11 6 1

1 be used. Correspondingly, regarding the vast range of voltage

η1 = (42)
A1 + B1 + C + 1 gains based on only varied D1 , applying constant D2 causes
1 no dysfunction.
η2 = (43)
A2 + B2 + C + 1 √ √ We compare our structures with other ones regarding voltage
VCE−on (5G + 1) (4 D1 + D2 ) gains in Fig. 5. According to this figure, for D2 =30%, the
A1 = (44) proposed structure has a mild slope, and it can generate a
8GVo
9 higher voltage gain compared to other structures for various
ron j (8D 1 D2 )
+
A2 = 64 (45) duty cycles. Also, to achieve high voltage gain with ISH-SL-
Ro SC converter, there is no need for high duty cycles.
B1 = 3 (Eon + Eof f ) fs (46) The voltage stresses comparisons of semiconductor devices
9f C sw m are illustrated in Fig. 6(a) and Fig. 6(b). For instance, to
B2 = S o2 (47) clarify the good performance of the proposed structures, the
2G
1 1 maximum voltage stress of switches and diodes is calculated
VF w 16 rL j + rD n + 16 rC (h + m)
C= + (48) in the same voltage gain (for example, G=5) for all structures
4Vo R mentioned in Table I. The results show that the voltage stress
√ √o
m = (G + 1) ( D1 + D2 1 − D1 − D2 ) (49) of main switches in ISH-SL-SC is equal to SC-ANC [14],
2
SC-SL-ANC [19], SL/SC-SBC [15]. However, it is less than
j = G + 10G + 25 (50) the voltage stresses of other structures in which show good
u = G2 + 6G + 9 (51) performance. Furthermore, in comparison to the voltage stress
n = D1 (G2 + 6G + 8) + D2 (G2 + 6G + 25) + 2 (52) across the diodes, the ISH-SL-SC structure has low voltage
stress among other structures. As a result, it can be claimed
h = (D1 + D2 ) (15 − G2 − 2G) + G2 + 2G + 1 (53) that the proposed structures have proper operation respect to
the voltage stress across the semiconductor devices. It is clear
VI. P ERFORMANCE COMPARISON that in addition to the high voltage gain of the ISH-SL-SC
To evaluate a comprehensive performance comparison be- converter, the voltage stress of the auxiliary switch is decreased
tween the proposed structures and previous ones, Table I is in comparison to the IAH-SL and ISH-SL converters. The
presented. These structures are compared in terms of voltage reason for this decrease is adding SC cell. In fact, the voltage
gain, maximum voltage stress across the semiconductors, and stress of Vo is shared between diodes of SC cell and auxiliary
the number of components. switch. The summation of (21) and (24) verifies this advantage.
As mentioned in Section II, this work improves the perfor- stress
VS3 stress
+ VD4a,D4b,D4c = Vo (54)
mance of the conventional AH-SL [5], SH-SL [5] and SC-SL-
ANC [19] converters by adding the auxiliary switch S3 . In this In terms of current stress, the normalized average current
regard, other studies such as [1], [11], [14], [15], [18], [23], of semiconductors versus voltage gain is compared for CCM
[25] have introduced similar non-coupled and non-isolated in Fig. 7. According to this figure, the rate of average current
structures which combined the basic sub-structures ASL, PSL in the main switches remains lower for higher voltage gains
and SC as the hybrid structures to provide high voltage gains. compared to the conventional structures [5], [19] in Fig. 7(a).
According to Table I, the voltage gains of the proposed Similarly, this comparison is obtained for the maximum current
structures are dependent on both duty cycles D1 and D2 . In of the diodes in Fig. 7(b). Thus, in the proposed structures, the
fact, D2 has the role of the modifier to achieve a high gain efficiency is improved through the conduction losses reduction.
(see the second column of Table I). However, other structures The number of components, including switches, diodes,
are controlled by a single duty cycle. It is worth noting that to inductors, and capacitors, are compared in Table I. According
simplify the control function of switches, a constant D2 can to this table, among the comprised structures, HSXSQ Z-

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SL/SC-SBC SL-Boost HSXSQ-Z source, SC-ANC SC-Boost HBC IAH-SL AH-SL ISH-SL SH-SL ISH-SL-SC SC-SL-ANC
SC-SL-ANC, APICs- based AH-SL, SL-ANC SH-SL, ASL-SU2C 5
ISH-SL-SC IAH-SL ISH-SL
30 4
25

i /Io
3

ave
20

S
2
15
G

1
10

5 0
0 2 4 6 8 10 12 14 16 18 20
G
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 (a)
D IAH-SL AH-SL ISH-SL SH-SL ISH-SL-SC SC-SL-ANC
10
Fig. 5. Voltage gain comparison between the proposed converters and other
converters. 8

D o
6

/I
ave
i
4
APICs-based SC-Boost ISH-SL,SH-SL IAH-SL,AH-SL SL-Boost
SL/SC-SBC ASL-SU2C HSXSQ-Z source HBC SL-ANC 2
ISH-SL-SC, SC-ANC, SC-SL-ANC
0
30 0 2 4 6 8 10 12 14 16 18 20
G
25 (b)
Normalized VSstress

20
Fig. 7. Comparison between the proposed improved converters and conven-
15 tional converters. (a) Normalized average current of switch. (c) Normalized
average current of diode.
10

0
2 4 6 8 10 12 14 16 18 20
VII. S IMULATION AND EXPERIMENTAL ANALYSES
G
(a) A. Description of the experimental setup
SL/SC-SBC SL-Boost ISH-SL,SH-SL IAH-SL,AH-SL SC-ANC
SC-Boost SL-ANC ASL-SU2C HBC APICs-based
In this sub-section, design properties of a prototype ISH-SL-
ISH-SL-SC, SC-SL-ANC SC are described for low input voltage application. According
30 to (13), for Vin =3 V, D1 =50% and D2 =30% the value of Vo is
25
78 V. In addition, as stated in (14), for ∆iL =25% and fs =20
Normalized VDstress

kHz the minimum value of inductors L1a , L1b , L2a , L2b in

20
HSSL sub-structure is equal to 345 µH. Also, according to
15 (28), for ∆VCo =25% the value of Cmin is 696 µF.
10 Based on the above specifications, a laboratory prototype
5 of the proposed structure is implemented for experimental
validation. In the practical test, high-speed IGBTs which have
0
2 4 6 8 10
G
12 14 16 18 20 high voltage and current ratings are used as semiconductor
(b) switches. The ARDINO DUE R3 ARM-based digital control
platform is used to generate switching pulses. This pulse
Fig. 6. Comparison between the proposed converters and other converters. (a) generator is connected to the IGBTs gate driver through buffers
Normalized voltage stress of switch. (b) Normalized voltage stress of diode. and optocoupler. The implemented converter is composed of
two stacked boards that are shown in Fig. 8.
Three gate driver, three IGBTs and two DC voltage sources
are used with constant values of D1 =50%, D2 =30% and fs =20
kHz. For all inductors, LCR measurement shows that the
source [23] has the maximum number of switches. Also, the values of inductance L and resistance rL are 350 µH and
proposed structures take the next rank. Nevertheless, adding 1.9 Ω, respectively. For isolating the grounds, three DC-DC
the auxiliary switch makes the difference between the number converters in a small SIP package are used. Consequently,
of switches. In fact, a minimum change in the number of Table II shows the summarized list of components that are
switches leads to advantages like higher voltage gains and used in the prototype structure.
efficiency. Besides, the number of diodes and inductors in [11] The generated gate pulses for the switches are shown in
is relatively higher than the ISH-SL-SC converter. Finally, we Fig. 9. Accordingly, the auxiliary switch S3 is turned on
do not utilize plenty of capacitors in comparison with other immediately after S1 ,S2 switches are turned off. Also, all
structures. switches are turned off after (D1 + D2 )Ts . Therefore, the

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g1,g2
1.00 g1,g2

0.00 0
g3
1.00 g3

0
0.00
50µs
0.19975 0.19980 0.19985 0.19990 0.19995 2V

Fig. 9. Gate signals of S1 , S2 and S3 .

iL1a , iL2a , iL1b , iL2b [A]

(a) 35.0
30.0
25.0 4.250
20.0
15.0
3.950 0
10.0
5.0 50µs
0.0
-5.0 2A
0 0.025 0.050 0.075 0.100 0.125 0.150 0.175

Fig. 10. Simulation and experimental current of the inductors.

VD1a ,VD1c ,VD2a ,VD2c [V]

12.0
VD1a , VD1c ,VD2a ,VD2c
8.0 10
(b)
4.0 0 5V
0.0 0
VD1b ,VD2b [V]
Fig. 8. Prototype of the proposed ISH-SL-SC converter. (a) Connection 7.0 VD1b ,VD2b
framework. (b) Introducing the components. 1V
3
0. 0 0
TABLE II. S PECIFICATION OF PROPOSED CONVERTER 0 50µs
0 0.025 0.050 0.075 0.100 0.125 0.150 0.175
No. Component Description and value
1 Buffer GD74HCT244
2 Voltage source For supplying control unit with 5 V Fig. 11. Simulation and experimental waveforms of the voltages across the
3 DC-DC converters MAU209, 1 W , ±15 V, ±34 mA HSSL diodes.
4 Vs For supplying power part with 3 V
5 Diodes MUR460, ultrafast rectifier, 600 V, 4 A
6 Inductors 320 µH both experimental and simulation results. Due to the different
7 Capacitors 470 µF - 400 V
ARDINO DUE R3, microcontroller charging conditions in Modes 1&2 (see Figs. 2a and 2b),
8 Controller board based on Atmel SAMX8E ARM the charging slope of SLs’ currents iL1a , iL2a , iL1b , iL2b are
Cortex M3 CPU
6N137, high-speed integrated
varied. The peak to peak current ripple value of these inductors
9 Optocoupler is less than 0.5 A, and the percentage current ripple is about
photo-detector logic gate single-channel
10 Gate driver
A316J, high-speed integrated ∆iL =25%iL . Consequently, the simulated and experimental
photo-detector logic gate
FGH40N60UFD, high-speed IGBT,
waveforms are noted to be in agreement with the theoretical
11 Switches operation analysis from Section V.
600V, 40A
12 Output terminal - The relevant waveforms to analyze switches and diodes
13 Ro 200 Ω
operation modes are provided in Figs. 12 and 13. From Fig. 12,
the maximum voltage stress of the switches S1 , S2 in HSSL
sub-structure is approximately 20 V which is in compromise
three operation modes of the ISH-SL-SC are completed by
with theoretical calculation of (15). Meanwhile, the voltage of
the switches turn on/off states in each switching period.
these semiconductor switches in Mode 2 is equal to Vin (≃ 3
V) as presented in Fig. 12. Furthermore, the maximum voltage
B. Results of the simulated and prototype ISH-SL-SC stress of S3 is half of the Vo (≃ 40 V) as demonstrated in (21).
To verify the theoretical analyses, the simulation has been To confirm the desired operation of HSSL sub-structure, the
done in PSCAD/EMTDC comprehensively. In addition, the voltage of the diodes D1a , D2a , D1b , D2b , D1c , D2c are shown
operation modes are tested by implementing a 100 W ISH- in Fig. 11. As obtained from (17) and (18), the maximum
SL-SC experimental prototype. The steady-state results of the voltage stress of diodes D1a , D1c , D2a , D2c , D1b , D2b is
proposed structure under the open-loop control method are about 8.5 V and 3 V , respectively. Diodes D4a , D4c , D4b
illustrated in Figs. 10 to 14. have opposite operation principles. As shown in Fig. 13, the
The experimental currents flowing through SLs are shown maximum voltage stress of diodes in SC-cell is approximately
in Fig. 10 and compared with the simulation results. These 40 V as evaluated in (13). Indeed, Fig. 13 verifies the proper
inductors are charged through the input voltage Vin =3 V in operation of SC-cell sub-structure.
Modes 1&2 and transfer desired power to Ro in Mode 3. In Fig. 14, the high step-up output voltage is presented for
Hence, the current of SLs has a trapezoidal wave shape in both simulated and prototype ISH-SL-SC structure. Based on

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Vs1 , Vs2
30.0 VS1 ,VS2 98.5
AH−SL [5]
20.0 25 10V IAH−SL
10.0 98

η (%)
0 0
0.0
Vs3 97.5
60 VS3
40
40 20V 97
20
0 0 2 4 6 8 10 12
0
50µs G
0 0.025 0.050 0.075 0.100 0.125 0.150 0.175
(a)
97
SH−SL [5]
Fig. 12. Simulation and experimental waveforms of voltages across the ISH−SL
switches. 95

η (%)
93
VD4b [V]
60
50 VD4b 91
40 2 6 10 14 18
30 40 G
20
10 0
0
VD4a ,VD4c [V] 0 (b)
60 VD4a ,VD4c
50 100
40 SC−SL−ANC [19]
30 40 ISH−SL−SC
20 90
10 0

η (%)
0 0 50µs 80
0 0.025 0.050 0.075 0.100 0.125 0.150 0.175 20V
70
60
2 6 10 14 18 22 26
Fig. 13. Simulation and experimental waveforms of voltages across the SC G
diodes.
(c)
96
Vo Measured
120 94 Calculated

η (%)
100 92
80 90
60
88
40 77.500
20
86
30 35 40 45 50 55 60 65 70 75
0 77.375 0 Po (W)
-20 500ms
0 0.025 0.050 0.075 0.100 0.125 0.150 0.175 20V (d)
Fig. 15. Comparison of efficiencies for the same Vin .
Fig. 14. Simulation and experimental waveforms of output voltage.
12%

(13), for D1 =50%, D2 =30% and Vin =3 V, the theoretical value
of Vo is 78 V. The main difference among the theoretical,
simulation, and experimental values of Vo depends on voltage
drops in parasitic elements of electrical components. Accord-
ing to Fig. 14, there is a low ripple in the output voltage about
0.1 V, which is negligible considering the ultra-high voltage
gain of the proposed structure (G=26).
In Figs. 15(a)-(c), the efficiency comparison is performed
between the improved and previous converters in terms of
voltage gain. According to Figs. 15(a), for higher voltage
gains, the rate of efficiency decrease in IAH-SL remains lower
compared to AH-SL. For example, at a voltage gain of 12,
the efficiency of the IAH-SL converter is approximately 1%
higher than the AH-SL converter. In Fig. 15(b), for the voltage
gains from 6 to 17, the efficiency of the ISH-SL converter is
about 2% higher than the SH-SL. In addition, Fig. 15(c) clearly
shows the advantage of the ISH-SL-SC converter over SC-SL-
ANC, especially at high voltage gains. So that for the voltage
gains from 2 to 26, the rate of gain decrease for ISH-SL-
SC and SC-SL-ANC converters is 18% and 34%, respectively.
According to this figure, with the increase of gain, even in the
presence of the auxiliary switch, the efficiency of the ISH-SL-
SC is higher than the previous one. For example, at the voltage
gain of 25, the efficiency of the proposed converter is 17%
higher than the previous one. On the other hand, to evaluate
the performance of the proposed converter for different loads,
31% 57% The loss of switches
The loss of diodes
The loss of inductors
Other losses
<1%
Fig. 16. Share of losses in the proposed ISH-SL-SC.
a comparison has been made between the calculated and the
measured efficiencies. According to Fig. 15(d), considering
different loads, corresponding to the powers of 33.33 W, 40.5
W, 51.6 W, and 70.8 W, the practical efficiencies are 92.64%,
92.04%, 88.96%, and 86.34%, respectively.
Fig. 16 shows the losses ratio of different elements in the
ISH-SL-SC converter for a voltage gain of 26. The total ISH-
SL-SC converter losses is about 12 W, while at the same
voltage gain, the amount of losses in SC-SL-ANC converter
without the auxiliary switch is 15 W. The total losses of
switches in the improved converter is about 1.56 W less than
the total losses of switches in the conventional converter. In
fact, the smaller duty cycle of the main switches (S1 , S2 )
reduces conduction losses. Also, according to (16), the average
current of S3 is approximately half of the main switches’
current. Therefore, the total losses of switches in the ISH-
SL-SC is smaller than the conventional one. Similarly, diode
and inductor losses in the proposed converter are 20% and

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21% smaller than conventional converters, respectively. These
results confirm the correctness of the comparison presented
in Fig. 15(c). Therefore, it seems that the proposed improved
converter has unique advantages over conventional converters
that can be considered by industry and other researchers.
VIII. C ONCLUSION
The structure of three non-isolated hybrid switched in-
ductor/switched capacitor DC-DC converters were improved
in this paper. The proposed converters can be derived by
integrating ASL, PSL, SC cell, and an auxiliary switch.
These structures not only include the benefits of conventional
converters but also could improve voltage gain and efficiency.
Accordingly, the efficiency was enhanced by almost 17% while
the practical voltage gain reached above 30. We calculated the
accurate voltage and current stresses of the entire elements, as
well as the proper size of inductors and capacitors. In addition,
the efficiency of the proposed converters was obtained by
incorporating parasitic elements. We validated our theoretical
analyses’ accuracy by implementing different simulations and
experimental investigations with an open-loop controller on
our prototype.
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Behdad Faridpak received the M.Sc. degree in
Electrical Engineering from the University of Tabriz
in 2016. His research interests include renewable en-
ergy systems, power electronics and power systems’
operation.
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Mohammad Bayat is currently pursuing the M.Sc. Rahim Samanbakhsh received the M.Sc. degree
degree in Bioelectrical Engineering at the school of in electrical power engineering from the University
Electrical and Computer Engineering, the Univer- of Zanjan, Zanjan, Iran, in 2016. He is currently
sity of Zanjan, Zanjan, Iran. His current research pursuing the Ph.D. degree in power electronics at
interests include molecular communication networks, the Skolkovo Institute of Science and Technology,
nano communication, power electronics, underwater Moscow, Russia. His current research interests in-
welding systems, and system identification. clude control of power electronic converters, multi-
level converters, Z-source and matrix converters, ap-
plications of power electronics in renewable energy
systems, and FACTS devices.

Meisam Farrokhifar (Senior Member, IEEE) re-

Mojtaba Nasiri received the Ph.D. degree from ceived the Ph.D. degree in electrical engineering
the Amirkabir University of Technology (Tehran from the Polytechnic University of Milan, Milan,
Polytechnic), Tehran, Iran. Since 2015, he has been Italy, in 2014. He was an Assistant Professor with
an Assistant Professor at the Department of Electri- Azad University, Iran, from 2014 to 2018. He then
cal Engineering, Abhar Branch, Islamic Azad Uni- joined the Skolkovo Institute of Science and Tech-
versity, Iran. His current research interests include nology, Moscow, Russia, as a Research Scientist.
renewable energies, DGs, Microgrid, power electron- Dr. Farrokhifar was engaged in the Next Generation
ics, flexible alternating current transmission systems Program between Skolkovo Institute of Science and
(FACTS) devices, and power system stability and Technology, and Massachusetts Institute of Tech-
control. nology, USA. He is also collaborating as a Guest
Researcher with the University of Groningen, The Netherlands. His research
focus comprises power systems optimization, energy conversion, fault analysis,
and renewable energy systems.

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