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Top Level View of Computer Function
Top Level View of Computer Function
Top Level View of Computer Function
Hardwired program
The result of the process of connecting the various components in
the desired configuration
+ Data
Sequence of
arithmetic
and logic
functions
Results
Hardware
and Software I nstruction I nstruction
Approaches
codes interpreter
Control
signals
General-purpose
Data arithmetic Results
and logic
functions
I/O AR
Data
Execution
unit Data
I/O BR Data
Data
PC = Program counter
Buffers IR = Instruction register
MAR = Memory address register
MBR = Memory buffer register
I/O AR = Input/output address register
I/O BR = Input/output buffer register
MAR
I/O address I/O buffer
register (I/OAR) register (I/OBR)
• Specifies a particular • Used for the
I/O device exchange of data
+ between an I/O
module and the CPU
MBR
Fetch Cycle Execute Cycle
Processor- Processor-
memory I/O
Data
Control
processing
0 1 15
S Magnitude
Multiple Multiple
operands results
Classes of Interrupts
User I/O User I/O User I/O
Program Program Program Program Program Program
1 4 1 4 1 4
Interrupt Interrupt
2b Handler Handler
END END
3a
3 3
3b
(a) No interrupts (b) Interrupts; short I/O wait (c) Interrupts; long I/O wait
i
Interrupt
occurs here i+1
Interrupts
Disabled
Check for
Fetch Next Execute
START Interrupt;
Instruction Instruction Interrupts Process Interrupt
Enabled
HALT
1 1
4 4
I/O operation
I/O operation;
processor waits 2a concurrent with
processor executing
5 5
2b
2
4
I/O operation
4 3a concurrent with
processor executing
I/O operation;
processor waits 5
5 3b
1 1
4 4
5
2
4
4
3 I/O operation
concurrent with
I/O operation; processor executing;
processor waits then processor
waits
5
5
Multiple Multiple
operands results
No
Instruction complete, Return for string interrupt
fetch next instruction or vector data
Interrupt
handler Y
Interrupt
User program handler X
Interrupt
handler Y
15
0 t=
t =1
t = 25
t= t = 25 Disk
40 interrupt service routine
t=
35
Data N–1
External
Address M Ports Data
Internal
Data Interrupt
Signals
External
Data
Instructions Address
Control
Data CPU Signals
Interrupt Data
Signals
An I/O
module is
allowed to
exchange
data
Processor Processor
directly
reads an Processor reads data Processor
with
instruction writes a from an I/O sends data
memory
or a unit of unit of data device via to the I/O
without
data from to memory an I/O device
going
memory module
through the
processor
using direct
memory
access
Data Bus
Data lines that provide a path for moving data among system
modules
Control lines
Data lines
I/O device
I/O Hub
DRAM
DRAM
Core Core
A B
DRAM
DRAM
Core Core
C D
I/O device
I/O device
I/O Hub
Routing Routing
Flits
Link Link
Figur e 3 .1 8 QPI La ye r s
+
QPI Link Layer
Gigabit PCIe
Memory
Ethernet
Chipset
PCIe–PCI PCIe
Memory
Bridge
PCIe
PCIe PCIe
Switch
PCIe PCIe
Physical Physical
Configuration Message
This address space enables This address space is for
the TL to read/write control signals related to
configuration registers interrupts, error handling,
associated with I/O devices and power management
PCIe TLP Transaction Types
Address Space TLP Type Purpose
Memory Read Request
Transfer data to or from a location in the
M emory Memory Read Lock Request system memory map.
Memory Write Request
I/O Read Request Transfer data to or from a location in the
I /O
I/O Write Request system memory map for legacy devices.
Config Type 0 Read Request
Config Type 0 Write Request Transfer data to or from a location in the
Configuration
Config Type 1 Read Request configuration space of a PCIe device.
Config Type 1 Write Request
Message Request Provides in-band messaging and event
M essage reporting.
Message Request with Data
Completion
M emory, I /O, Completion with Data
Returned for certain requests.
Configuration Completion Locked
Completion Locked with Data