IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 22, NO.

2, FEBRUARY 2014 425

Comparative Study of Various Latch-Type VDD

Sense Amplifiers
MP3 MP4
Taehui Na, Seung-Han Woo, Jisu Kim, Hanwool Jeong, VDD MP1 MP2
and Seong-Ook Jung BL BLB
OUT OUTB
MP1 MP2 MN1 MN2
Abstract— When the input voltage difference of a sense amplifier (SA) OUT OUTB
exceeds the offset voltage (V OS ), the SA correctly detects it and outputs MP3 MP4
a large signal. However, when the input voltage is in a certain region, the BLB BL
MN1 MN2 MN3 MN4
SA can fail to sense the input voltage difference even if it is sufficiently
COMN COMN
large. This input voltage region is defined as the sensing dead zone of the
SA. Because sensing dead zones differ depending on SAs and the input SAE SAE
voltages to the SA differ depending on the memory devices, analyzing MNFOOT MNFOOT
the sensing dead zone is very important. In this brief, we analyze the
sensing dead zones of the most popular latch-type SAs: voltage- and
(a) (b)
current-latched SAs. Furthermore, a suitable latch-type SA scheme is
suggested for various SA input voltages in terms of sensing delay, power Fig. 1. Two representative latch-type SAs. (a) FSPA-VLSA. (b) FS-CLSA.
consumption, and PDP, using a 65-nm predictive technology model at a
V DD of 1.1 V. where YSA is the yield of SA, μOS is the mean of VOS , and σOS is the
Index Terms— Latch-type, mismatch, offset voltage, sense standard deviation of VOS . For a fully balanced SA, μOS is assumed
amplifier (SA), sensing dead zone. to be zero [3]; therefore, YSA depends only on ΔVBL and σOS . There
is an input voltage region in which YSA is significantly reduced, even
I. I NTRODUCTION though ΔVBL is large. This input voltage region is referred to as the
The sense amplifier (SA) is one of the most important peripheral sensing dead zone. Different types of memory generate different SA
circuits in memory devices [1]. Although many types of SAs have input voltages. For example, SRAM generates SA input voltages near
been developed, the latch-type SA is the most popular because of VDD . DRAM generates SA input voltages that are approximately half
its high sensing speed and low power consumption [2], [3]. Fig. 1 of VDD . MRAM and PRAM generate intermediate SA input voltages
shows two representative latch-type SAs: 1) a voltage-latched sense [7], [8]. In previous studies, YSA has been analyzed in terms of VOS
amplifier with an nMOS footswitch and pMOS access transistors [3], [9]. However, thus far, there have been no studies on the sensing
(FSPA-VLSA) and 2) a current-latched sense amplifier with an dead zone. Because each SA structure has a unique sensing dead
nMOS footswitch (FS-CLSA). The VLSA senses the voltage zone, analyzing this zone is very important for achieving the required
difference (ΔVBL ) between the bit line voltage (VBL ) and the yield by properly selecting the SA according to the SA input voltage.
bit line bar voltage (VBLB ) and amplifies it to rail-to-rail output The rest of this brief is organized as follows. In Section II,
voltages (VOUT and VOUTB). Similarly, the CLSA senses the current the sensing dead zones of various latch-type SAs are analyzed.
difference produced by ΔVBL and amplifies it to rail-to-rail output In Section III, the sensing delays, power consumption, and power
voltages. The VLSA has the advantages of a higher sensing speed delay product (PDP) of each SA are compared, and a suitable SA
and a smaller layout area as compared to CLSAs because it has is proposed on the basis of the SA input voltage and performance
fewer transistors. However, because the output nodes also serve criteria. Conclusions are presented in Section IV.
as input nodes, the sense amplifier enable (SAE) signal needs to
be carefully controlled. The CLSA does not have this drawback, II. S ENSING D EAD Z ONES OF L ATCH -T YPE SA S
because it uses separate input and output nodes [4]. A. Simulation Methodology and Variability
In an ideal case, the offset voltage (VOS ) of an SA is zero.
Simulations were performed using a predictive model of a 65-nm
Therefore, the SA can correctly sense ΔVBL , unless ΔVBL is 0. In
CMOS technology with a VDD of 1.1 V. VBL is assumed to be larger
practice, however, VOS is not zero because of the mismatch between
than VBLB by ΔVBL . The SA input voltage is defined as VBL in
paired transistors. Hence, ΔVBL must be larger than VOS to be
this brief. Monte Carlo (MC) simulations were performed to analyze
identified correctly [5]. In general, VOS has a Gaussian distribution
the sensing dead zones of an SA. There are many sources of random
[6]. Using a cumulative distribution function (CDF) of the standard
and systematic variability that can induce transistor mismatch. As the
normal distribution (denoted by (x)), the yield of SA can be
process technology is scaled down, the effects of random variation
expressed as
increase. In particular, threshold voltage (VTH ) variation (which is
 
ΔVBL − μOS induced by random dopant fluctuation (RDF) and is assumed to
YSA = P [ΔVBL > VOS ] =  (1)
σOS follow a Gaussian distribution [10]) becomes a dominant factor [6].
Therefore, VTH variation is the main contributor to VOS . According
Manuscript received June 12, 2012; revised December 7, 2012; accepted to Pelgrom’s research [11], the standard deviation of VTH variation
January 8, 2013. Date of publication February 21, 2013; date of current version (σVT ) is expressed as
January 17, 2014. This work was supported by the IT R&D Program of
MKE/KEIT. A VT
σVT = √ (2)
T. Na, J. Kim, H. Jeong, and S.-O. Jung are with the School of W×L
Electrical and Electronic Engineering, Yonsei University, Seoul 120-749, 
Korea (e-mail: lataehee@yonsei.ac.kr; panatrop@yonsei.ac.kr; hanwool87@
4
4q 3 ε Si  F N TOX
A VT = · (3)
yonsei.ac.kr; sjung@yonsei.ac.kr). 2 εOX
S.-H. Woo was with the School of Electrical and Electronic Engineering,
Yonsei University, Seoul 120-749, Korea. He is now with Samsung Electronics where A VT is a constant that depends on the process technology
Co., Ltd., Yongin-City 449-711, Korea (e-mail: shwoo@yonsei.ac.kr). used [6],  F is the Fermi potential, TOX is the thickness of the gate
Digital Object Identifier 10.1109/TVLSI.2013.2239320 oxide, N is the doping concentration of the substrate, and ε Si and
1063-8210 © 2013 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

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 426 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 22, NO. 2, FEBRUARY 2014
80
60
σOS (mV)
40
20
Region 1 Region 2 Region 3 Region4
Near VSS Under VTHN Intermediate Region
0
0.0 0.1 0.2 0.3 0.4 0.5 0.6
VBL (V)
Fig. 2. σOS according to input voltage (VBL ) for latch-type SAs.
εOX are the permittivity of silicon and the gate oxide, respectively.
The transistor variability used in the MC simulations was modeled as
a VTH variation that follows a Gaussian distribution, using (2). A VT
was calculated using (3) based on the transistor model’s physical
parameters. However, [12] revealed that RDF-induced VTH variation
comprises ∼ 60% of the total VTH variation in deep sub-micron
technology because there are other variability sources, such as line
edge roughness (LER) [13], TOX variation, and interface roughness
[14]. Therefore, A VT was adjusted by multiplying the value obtained
from (3) by 1.7 (= 1/0.6) to account for the effects of other variability
sources, including β (= μn Cox W/L) variation. When designing an
SA, yield is the most important design criterion. Because the industry
design target of 3·σOS is typically set to be 50-70 mV, the SAs in
this brief are designed to have a σOS of 20 mV.
The simulation methodology for performing sensing dead zone
analysis is as follows. With a fixed value of VBL , the correct sensing
operation occurs when ΔVBL is larger than VOS . Then, YSA can be
estimated as
number of correct sensing operations
YSA = . (4)
total MC simulation trials
Because the SAs are designed to have a σOS of 20 mV, sweeping
ΔVBL from −70 to 70 mV is sufficient to extract μOS and σOS
from the fitted Gaussian CDF. Because the SAs are designed to be
balanced, the extracted μOS is close to 0, and thus, can be ignored.
The same procedures are performed while sweeping VBL from 0 V
to VDD . The YSA is significantly reduced when the VBL is in the
sensing dead zone. The degradation of YSA can be modeled as an
increase in σOS according to (1).
B. Conventional CLSAs and VLSAs
Fig. 2 shows σOS as a function of VBL for latch-type SAs. The
range of VBL is divided into six regions, based on σOS characteristics.
For FS-CLSA shown in Fig. 1(b), which senses the current difference
induced by ΔVBL , σOS decreases and becomes saturated as VBL
decreases from 1.1 V to the nMOS threshold voltage (VTHN ). On
the other hand, σOS rapidly increases when VBL is lower than VTHN .
The reasons for these variations are as follows. As VBL decreases,
the initial voltage difference (VO ), which is defined as the voltage
difference between the two output nodes when a latching pMOS
(MP1 or MP2) is turned on, increases, and more correct decision
occurs [3]. Thus, σOS decreases as VBL decreases. However, when
VBL is lower than VTHN , the input transistors (MN3 and MN4) are
not turned on. Thus, no sensing operation occurs because the input
transistors cannot convert the input voltage into current, referred to
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FSPA-VLSA
NMOS Sensing
DSPA-VLSA
Scheme
FS-CLSA
HSNA-VLSA
DSNA-VLSA
PMOS Sensing
Scheme
HS-CLSA
DSTA-VLSA
Region 5 Region 6
Above VDD – |VTHP| Near VDD
0.7 0.8 0.9 1.0 1.1
as the voltage-to-current conversion problem. Therefore, the sensing
dead zone of the FS-CLSA is below VTHN .
In FSPA-VLSA, shown in Fig. 1(a), the mismatch between the
weak latching pMOSs (MP1 and MP2) does not contribute to VOS
when VBL is higher than VDD − |VTHP | because they are in the
sub-threshold region in the early sensing period [7]. Thus, only
the mismatch between the strong latching nMOSs (MN1 and MN2)
contributes to VOS . However, when VBL falls below VDD − |VTHP |,
MP1 and MP2 are turned on, and their mismatch begins to contribute
to VOS . Moreover, because MP1 and MP2 are turned on even before
the sensing operation starts, invalid current paths [dotted lines in
Fig. 1(a)] occur, which reduces ΔVBL and leads to a rapid increase
in the sensing failure probability. Therefore, the sensing dead zone
of an FSPA-VLSA is less than VDD − |VTHP |.
Recently, a ground sensing structure has been proposed to achieve
a large sensing margin in the DRAM [15]. In this case, because
VBL is low, the VLSA with a pMOS headswitch and nMOS access
transistors (HSNA-VLSA) is required; two pMOS access transistors
and an nMOS footswitch of FSPA-VLSA are replaced with two
nMOS access transistors and a pMOS headswitch [16]. Its sensing
mechanism is diametrically opposite to that of the FSPA-VLSA.
Thus, the sensing dead zone of HSNA-VLSA is above VTHN . The
CLSA with a pMOS headswitch (HS-CLSA), which has a pMOS
headswitch and two nMOS precharge transistors to ground instead
of a nMOS footswitch and two pMOS precharge transistors to VDD
in FS-CLSA, is also a candidate for the ground sensing structure
[17]. Its sensing mechanism is also diametrically opposite to that of
the FS-CLSA. Therefore, the sensing dead zone of the HS-CLSA is
above VDD − |VTHP |.
C. VLSAs With Double Switches
The invalid current paths in FSPA-VLSA or HSNA-VLSA can
be removed by inserting an additional headswitch or footswitch,
respectively, in addition to introducing a complementary sense enable
signal, as shown in Fig. 3(a) and (b). The additional switch prevents
the weak latching transistors (MP1 and MP2 in DSPA-VLSA, or
MN1 and MN2 in DSNA-VLSA) from being turned on during an
idle period; thus, the invalid current paths are prohibited, leading
to a wide sensible VBL region. In the DSPA-VLSA, if the SAEB
is activated earlier than SAE, both MP1 and MP2 are turned on
when VBL is lower than VDD − |VTHP |, leading to invalid current
paths, similar to those found in FSPA-VLSA. Thus, the SAE must
be activated earlier than the SAEB. Similarly, the SAEB must be
activated earlier than the SAE in the DSNA-VLSA. This timing
 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 22, NO. 2, FEBRUARY 2014 427

D. VLSAs With Double Switches and Transmission Gate Access

Transistors
Although the VLSA with double switches reduces the size of the
sensing dead zone, its access transistors induce the sensing dead zone.
Using transmission gates as access transistors, as shown in Fig. 4, one
can completely remove the sensing dead zone. The solid line in Fig. 5
indicates that the VLSA with double switches and transmission gate
access transistors (DSTA-VLSA) has no sensing dead zone. Because
of the effect of both latching nMOS and latching pMOS, the σOS of
the DSTA-VLSA is almost flat over all VBL regions. In this brief,
it is assumed that VBL is greater than VBLB by ΔVBL . Thus, in the
case of no process variation, IMP1 is larger than IMP2 , and IMN1 is
(a) (b)
smaller than IMN2 . However, when the process variation is applied
Fig. 3. Double switch schemes. (a) DSPA-VLSA. (b) DSNA-VLSA. only to a latching nMOS pair, VOSN , which is the offset voltage
caused by the latching nMOS pair, is not zero. When the VOSN is
positive, IMN1 increases. This can cause sensing failure when IMN1 is
larger than IMN2 because of the large VOSN . As VBL decreases below
VTHN , the discharging current through the latching nMOSs decreases
and charging current through the latching pMOSs increases, leading
to a decrease in the effect of VOSN . Similarly, when the process
variation is applied only to a latching pMOS pair, VOSP , which is
the offset voltage caused by the latching pMOS pair, is not zero. As
VBL increases beyond VDD − VTHP , the charging current through
the latching pMOSs decreases and the discharging current through
the latching nMOSs increases, leading to a decrease in the effect
of VOSP . When the process variation is applied to both the latching
nMOS and pMOS pairs, VOS is the sum of VOSN and VOSP . Thus,
σOS is given by

σOS = σOSN 2 2
+ σOSP (5)
Fig. 4. Schematic diagram of DSTA-VLSA.
where σOSN (σOSP ) is the standard deviation of VOSN (VOSP ). The
effect of the access transistors on σOS is negligible, because they act
DSTA-VLSA as switches. Fig. 5 verifies (5). As shown in Fig. 5, the effect of
Only NMOS Variation σOSN on σOS decreases as VBL decreases and the effect of σOSP on
30 Only PMOS Variation σOS decreases as VBL increases, which induce an almost flat shape
Equation (5) in σOS for all VBL regions.
Without careful timing control, an invalid current path can occur
20
even if the double switches are used. Unlike DSPA-VLSA and
mV)

DSNA-VLSA, DSTA-VLSA has both invalid current paths from VDD

σOS (m

to VBL and from VBL to GND, and thus it cannot avoid these two
types of invalid current paths at the same time. For the reason,
10
DSTA-VLSA can be sensitive to the timing difference of ΔtSAE =
|tSAE −tSAEB | and its variation caused by the process variation, where
tSAEB and tSAE are the SAEB and SAE activation times, respectively.
0
When VBL is in regions 1 and 6, an invalid current path does not occur
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1
because the weak latching transistors are always off. However, when
VBL (V)
VBL is in the regions 2-5, invalid current path occurs. Especially,
Fig. 5. σOS of DSTA-VLSA according to SA input voltage (VBL ). when VBL is in the regions 3 and 4, both invalid current paths from
VDD to VBL and from VBL to GND occur, which makes σOS be very
sensitive to the ΔtSAE . Thus, the ΔtSAE needs to be carefully taken
into account when designing DSTA-VLSA. In this brief, mean + 3
sigma of the ΔtSAE is designed to be less than 20 ps to make σOS
sequence is implemented by using an inverter between SAE (SAEB)
less sensitive to the ΔtSAE .
and SAEB (SAE). Because of the additional switch, the sensing dead
zones of double switch schemes become narrow compared to those
of single switch schemes; however, the sensing dead zones never III. S UITABLE SA S CHEME BASED ON SA I NPUT VOLTAGE
disappear because of the voltage delivery problems introduced by To select a suitable SA based on VBL , not only the sensing dead
the access transistors. Because the pMOS access transistors in the zone but also the sensing delay, power consumption, and PDP must be
DSPA-VLSA cannot perfectly transfer the VBL when it is lower than considered. The sensing delay of an SA (TSA ) is defined as the time
|VTHP |, the sensing dead zone is below |VTHP |. Similarly, because delay from the time that the rising SAE (or falling SAEB) reaches
nMOS access transistors in DSNA-VLSA cannot perfectly transfer half of VDD to the time that VOUT reaches 90% (or 10%) of VDD . The
the VBL higher than VDD − VTHN , the sensing dead zone is above power consumption of an SA (PSA ) comprises the idle power (Pidle )
VDD − VTHN . in the idle period and the sensing power (Psensing) in the sensing

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 428 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 22, NO. 2, FEBRUARY 2014

SA
SA

(a) (b) (c)

Fig. 6. Normalized σOS , power consumption (PSA ), sensing delays (TSA ), and PDP of latch-type SAs according to input voltage region. (a) Regions 1 and 2.
(b) Regions 3 and 4. (c) Regions 5 and 6.

period. Pidle contains the power consumption due to the invalid
current in the VLSAs with a single switch, sub-threshold leakage
current of the off-state transistors, and the gate leakage current of
the on-state transistors. Psensing comprises the power consumption
caused by the sensing current (current through VDD (IDD ) for pMOS
sensing schemes or current through VSS (ISS ) for nMOS sensing
schemes) and the leakage current. Both powers are measured from
the time at which the sensing operation begins to the time at which
all SAs finish sensing; they are then averaged over this time period.
Therefore, PSA is given by
PSA = Pidle + Psensing .
Psensing = VDD IDD . (10)
Because the direction of the invalid current path in the nMOS
sensing scheme is different from that in the pMOS sensing scheme,
the equation for Pidle is slightly different. Fig. 6 shows the
simulation results for σOS , power consumption, sensing delay, and
PDP for different VBL . All simulation results are normalized. σOS is
normalized by 20 mV; power consumption, sensing delay, and PDP
are normalized by their minimum value among all SAs.
(6) A. VBL in Regions 1 and 2

For the nMOS sensing scheme When the VBL is in Regions 1 and 2, FSPA-VLSA, DSPA-VLSA,
and FS-CLSA operate in the sensing dead zone because the pMOS
Pidle = (VDD −VBL ) IMP1 +(VDD −VBLB ) IMP2 +VDD Ileakage (7) access transistors in the FSPA-VLSA and DSPA-VLSA cause the
Psensing = VDD ISS . (8) voltage delivery problem and the nMOS input transistors in the
FS-CLSA cause the voltage-to-current conversion problem. Thus, the
For the pMOS sensing scheme
HSNA-VLSA, DSNA-VLSA, HS-CLSA, and DSTA-VLSA can be
Pidle = VBL IMN1 + VBLB IMN2 + VDD Ileakage (9) selected in terms of σOS , as shown in Fig. 6(a).

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 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 22, NO. 2, FEBRUARY 2014
The PSA of the HSNA-VLSA, DSNA-VLSA, HS-CLSA, and
DSTA-VLSA decreases with VBL because of the decrease in sens-
ing current. The TSA of the HSNA-VLSA, DSNA-VLSA, and
DSTA-VLSA decreases with VBL because the effect of the latching
nMOSs, which has larger driving strength than that of the latching
pMOSs due to the larger mobility, increases with VBL . In the
HS-CLSA, when VBL increases, the capacitance charging delay at
the output node increases, whereas the latching delay in the two
cross-coupled inverters decreases [3]. Because both delays change as
a function of VBL and compensate for each other, the TSA of the
HS-CLSA is almost flat in Regions 1 and 2.
The HSNA-VLSA exhibits the smallest PDP. Therefore, this SA
is recommended to be operated in Regions 1 and 2.
B. VBL in Regions 3 and 4
Because VBL in Regions 3 and 4 is in the intermediate voltage
region, the single switch schemes have the invalid current path, and
thus FSPA-VLSA and HSNA-VLSA operate in the sensing dead
zone. The FS-CLSA operates in the sensing dead zone when the
VBL is in Region 3 because of the voltage-to-current conversion
problem of the nMOS input transistors. Therefore, the DSNA-VLSA,
DSPA-VLSA, DSTA-VLSA, and HS-CLSA can be selected for
Regions 3 and 4, and the FS-CLSA can be selected for Region 4, as
shown in Fig. 6(b).
The PSA of the DSNA-VLSA, DSPA-VLSA, and DSTA-VLSA
is almost flat because of no invalid current and almost flat sensing
current. However, the PSA of the FS-CLSA (HS-CLSA) increases
(decreases) with VBL because of the increase (decrease) in sensing
current. The TSA of the FS-CLSA exponentially decreases and
the TSA of HS-CLSA exponentially increases with VBL because of
the different polarity of the input transistors, which leads to the
voltage-to-current conversion problem. The TSA of the DSNA-VLSA,
DSPA-VLSA, and DSTA-VLSA decreases with VBL (in the same
manner of as previously described in Section A).
DSNA-VLSA and DSPA-VLSA exhibit the smallest PDP.
Therefore, these SAs are recommended to be operated in
Regions 3 and 4.
C. VBL in Regions 5 and 6
When VBL is in Regions 5 and 6, HSNA-VLSA, DSNA-VLSA,
and HS-CLSA operate in the sensing dead zone because the nMOS
access transistors in the HSNA-VLSA and DSNA-VLSA cause the
voltage delivery problem and the pMOS input transistors in the
HS-CLSA cause the voltage-to-current conversion problem. Thus,
the FSPA-VLSA, DSPA-VLSA, FS-CLSA, and DSTA-VLSA can be
selected based on σOS , as shown in Fig. 6(c).
The PSA , TSA , and PDP of the SAs are the counterparts of those of
the SAs in Regions 1 and 2. Therefore, FSPA-VLSA is recommended
to be operated in Regions 5 and 6.
IV. C ONCLUSION
The input voltage region in which an SA cannot correctly detect
the input voltage difference is called the sensing dead zone. Because
each SA scheme has its own respective sensing dead zone, detailed
knowledge of this zone is important for designing a high-yield
memory. In this brief, we analyzed the sensing dead zones of the most
popular latch-type SAs and proposed a suitable SA scheme according
to the input voltage region. VLSAs with single switch have the fewest
number of transistors and the best performance. However, because
of the wide sensing dead zones caused by the invalid current paths,
single switch schemes were recommended in the regions 1 and 2 or
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429
5 and 6. Double switch schemes with both footswitch and headswitch
can be used to solve the invalid current problem. Double switch
schemes were recommended in the regions 3 and 4. Nonetheless,
SAs utilizing these schemes still showed sensing dead zones because
of the access transistors. Using transmission access transistors with
double switches, the sensing dead zone can be completely removed.
This applies to cases in which the input voltage range is from GND
to VDD .
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