HO CHI MINH CITY UNIVERSITY OF TECHNOLOGY

OFFICE FOR INTERNATIONAL STUDY PROGRAM

FACULTY OF ELETRICAL & ELECTRONICS ENGINEERING

MINI PROJECT
MICROPROCESSOR
Instructor: NGUYỄN TRUNG HIẾU

Students: Trương Huy Thịnh ID: 1851111

Nguyễn Ngọc Khánh 1851079
Đặng Đức Toàn 1951022
Table of Contents
MINI PROJECT TOPIC & THEOREM....................................................................... 3

Topic of mini project ....................................................................................................... 3

Topic analysis.................................................................................................................. 3

HARDWARE PROCESSING ........................................................................................ 3

Create VDHL file using DE10 Standard V1.0.1 ............................................................. 3

Open VHDL file by Quartus 18.1 and set up Platform Designer ................................... 4

SOLFWARE PROCESSING ......................................................................................... 9

Type chapter title (level 2) .............................................................................................. 5

 INDEX
I/ Introduction:
Topic of mini project: Build a system using NIOS II in kit DE10 to connect a
LCD 16 x 2 and H-bridge to control a motor. This system can do the following
tasks:
- When SW0 is ON, LCD blinks the sentence “Hello Word !!! ” in the middle
of row 1 with frequency Hz. (Using timer)
- When SW1 is ON, NIOS II controls the motor by sending PWM pulses to the
H-bridge. LCD displays the duty cycle and the frequency of PWM rules.
- When SW0 and SW1 is OFF, turn off the system.
Reference:
- Datasheet of LCD 16x2
- An instruction of LCD interference
- L298_H_bridge datasheet
II/ Process:
1. VHDL part:
• DE10 Kit:
Choose option as follows:
+) GIPO (default): need for connection with LCD 16x2 and 2 ports for H
bridge L298N.
+) Switch: need switch to the cases like the topic (SWITCH 0 and 1)

• Open Quartus 18.1 and open VHDL file:

 QUARTUS

--Declare & Body --

Flatform Designer:
We add blocks:

1. Systems and DRAM clocks for DE-Series Boards

2. Nios II Processor
3. On-Chip Memory
4. JTAG UART Intel FPGA IP
5. PIO (LCD, H-bridge, Switch)
6. System ID peripheral
7. Interval Timer
8. SDRAM controller
ECLIPSE
Simulation in Labaratory