MOS Theory and I-V characteristics

Prof. Jagannadha Naidu K

Ref : Weste “ CMOS VLSI Design”, 3rd edition, 2006

Outline
 Introduction
 MOS Capacitor
 nMOS I-V Characteristics
 pMOS I-V Characteristics
 Gate and Diffusion Capacitance
Introduction
 So far, we have treated transistors as ideal switches
 An ON transistor passes a finite amount of current
 Depends on terminal voltages
 Derive current-voltage (I-V) relationships
 Transistor gate, source, drain all have capacitance
 I = C (DV/Dt) -> Dt = (C/I) DV
 Capacitance and current determine speed
MOS Capacitor

 Gate and body form MOS capacitor

polysilicon gate
 Operating modes Vg < 0
+
silicon dioxide insulator

- p-type body
 Accumulation
 Depletion (a)

 Inversion 0 < V g < Vt

depletion region
+
-

(b)

V g > Vt
inversion region
+
- depletion region

(c)
Terminal Voltages
 Mode of operation depends on Vg, Vd, Vs Vg
 Vgs = Vg – Vs + +
Vgs Vgd
 Vgd = Vg – Vd - -
 Vds = Vd – Vs = Vgs - Vgd Vs Vd
- +
Vds
 Source and drain are symmetric diffusion terminals
 By convention, source is terminal at lower voltage
 Hence Vds  0
 nMOS body is grounded. First assume source is 0 too.
 Three regions of operation
 Cutoff
 Linear
 Saturation
nMOS Cutoff

 No channel
 Ids = 0
Vgs = 0 Vgd
+ g +
- -
s d

n+ n+

p-type body
b
nMOS Linear

 Channel forms
 Current flows from d to s Vgs > Vt
Vgd = Vgs
+ g +
 e
- from s to d - -
s d
 Ids increases with Vds n+ n+ Vds = 0

 Similar to linear resistor p-type body

b

Vgs > Vt
Vgs > Vgd > Vt
+ g +
- - Ids
s d
n+ n+
0 < Vds < Vgs-Vt
p-type body
b
nMOS Saturation

 Channel pinches off

 Ids independent of Vds
 We say current saturates
 Similar to current source
Vgs > Vt
g Vgd < Vt
+ +
- -
s d Ids

n+ n+
Vds > Vgs-Vt
p-type body
b
I-V Characteristics

 In Linear region, Ids depends on

 How much charge is in the channel?
 How fast is the charge moving?
Channel Charge

 MOS structure looks like parallel plate capacitor

while operating in inversion
 Gate – oxide – channel
 Qchannel =

gate
Vg
polysilicon + +
gate
W
source Vgs Cg Vgd drain
Vs - - Vd
tox
channel
n+ - + n+
L SiO2 gate oxide Vds
n+ n+ (good insulator, ox = 3.9) p-type body
p-type body
Channel Charge

 MOS structure looks like parallel plate capacitor

while operating in inversion
 Gate – oxide – channel
 Qchannel = CV
 C=

gate
Vg
polysilicon + +
gate source Vgs Cg Vgd drain
W
Vs - - Vd
tox
channel
n+ - + n+
SiO2 gate oxide
Vds
L
n+ n+ (good insulator, ox = 3.9) p-type body
p-type body
Channel Charge
 MOS structure looks like parallel plate capacitor
while operating in inversion
 Gate – oxide – channel
 Qchannel = CV
 C = Cg = oxWL/tox = CoxWL Cox = ox / tox
 V=
gate
Vg
polysilicon + +
gate source Vgs Cg Vgd drain
W
Vs - - Vd
tox
channel
n+ - + n+
SiO2 gate oxide
Vds
L
n+ n+ (good insulator, ox = 3.9) p-type body
p-type body
Channel Charge

 MOS structure looks like parallel plate capacitor while

operating in inversion
 Gate – oxide – channel
 Qchannel = CV
 C = Cg = oxWL/tox = CoxWL Cox = ox / tox
 V = Vgc – Vt = (Vgs – Vds/2) – Vt

gate
Vg
polysilicon + +
source Vgs Cg Vgd drain
gate
W
Vs - - Vd
tox channel
n+ - + n+
L SiO2 gate oxide Vds
n+ n+ (good insulator, ox = 3.9) p-type body
p-type body
Carrier velocity

 Charge is carried by e-
 Carrier velocity v proportional to lateral E-field
between source and drain
 v=
Carrier velocity

 Charge is carried by e-
 Carrier velocity v proportional to lateral E-field
between source and drain
 v = mE m called mobility
 E=
Carrier velocity

 Charge is carried by e-
 Carrier velocity v proportional to lateral E-field
between source and drain
 v = mE m called mobility
 E = Vds/L
 Time for carrier to cross channel:
 t=
Carrier velocity

 Charge is carried by e-
 Carrier velocity v proportional to lateral E-field
between source and drain
 v = mE m called mobility
 E = Vds/L
 Time for carrier to cross channel:
 t=L/v
nMOS Linear I-V

 Now we know
 How much charge Qchannel is in the channel
 How much time t each carrier takes to cross

I ds 
nMOS Linear I-V

 Now we know
 How much charge Qchannel is in the channel
 How much time t each carrier takes to cross
Qchannel
I ds 
t

nMOS Linear I-V

 Now we know
 How much charge Qchannel is in the channel
 How much time t each carrier takes to cross
Qchannel
I ds 
t
 mCox
W V  V  Vds V
 gs t  ds
L 2 

  Vgs  Vt 
Vds   = mCox
W
Vds
 2  L
nMOS Saturation I-V

 If Vgd < Vt, channel pinches off near drain

 When Vds > Vdsat = Vgs – Vt
 Now drain voltage no longer increases
current
I ds 
nMOS Saturation I-V

 If Vgd < Vt, channel pinches off near drain

 When Vds > Vdsat = Vgs – Vt
 Now drain voltage no longer increases
current
I ds   Vgs  Vt  dsat Vdsat
V
 
2
nMOS Saturation I-V

 If Vgd < Vt, channel pinches off near drain

 When Vds > Vdsat = Vgs – Vt
 Now drain voltage no longer increases
current

I ds   Vgs  Vt 
Vdsat V
 dsat
 2 

  Vt 
2
 Vgs
2
nMOS I-V Summary

 Shockley 1st order transistor models


 0 Vgs  Vt cutoff

  Vds V V  V
I ds    Vgs  Vt   ds linear
 2 
ds dsat

 
Vgs  Vt 
2
 Vds  Vdsat saturation
2
Example
 We will be using a 0.6 mm process for your project
 From AMI Semiconductor
 tox = 100 Å
 m = 350 cm2/V*s 2.5
Vgs = 5

 Vt = 0.7 V 2

 Plot Ids vs. Vds 1.5 Vgs = 4

Ids (mA)
 Vgs = 0, 1, 2, 3, 4, 5 1
Vgs = 3
 Use W/L = 4/2 l 0.5
Vgs = 2
Vgs = 1
0
0 1 2 3 4 5
W  3.9  8.85  1014   W  W Vds
  mCox   350   8  L   120 m A /V 2
L  100  10   L
pMOS I-V

 All doping and voltages are inverted for pMOS

 Mobility mp is determined by holes
 Typically 2-3x lower than that of electrons mn
 120 cm2/V*s in AMI 0.6 mm process
 Thus pMOS must be wider to provide same current
 In this class, assume mn / mp = 2
Capacitance

 Any two conductors separated by an insulator

have capacitance
 Gate to channel capacitor is very important
 Creates channel charge necessary for operation
 Source and drain have capacitance to body
 Across reverse-biased diodes
 Called diffusion capacitance because it is
associated with source/drain diffusion
Gate Capacitance

 Approximate channel as connected to source

 Cgs = oxWL/tox = CoxWL = CpermicronW
 Cpermicron is typically about 2 fF/mm

polysilicon
gate
W
tox
L SiO2 gate oxide
n+ n+ (good insulator, ox = 3.90)
p-type body
Diffusion Capacitance

 Csb, Cdb
 Undesirable, called parasitic capacitance
 Capacitance depends on area and perimeter
 Use small diffusion nodes
 Comparable to Cg
for contacted diff
 ½ Cg for uncontacted
 Varies with process
Effective Resistance
 Shockley models have limited value
 Not accurate enough for modern transistors
 Too complicated for much hand analysis
 Simplification: treat transistor as resistor
 Replace Ids(Vds, Vgs) with effective resistance R
 Ids = Vds/R
 R averaged across switching of digital gate
 Too inaccurate to predict current at any given time
 But good enough to predict RC delay
RC Delay Model
 Use equivalent circuits for MOS transistors
 Ideal switch + capacitance and ON resistance
 Unit nMOS has resistance R, capacitance C
 Unit pMOS has resistance 2R, capacitance C
 Capacitance proportional to width
 Resistance inversely proportional to width

d
s
kC
kC
R/k
d 2R/k
d
g k g kC
g k g
s kC kC
kC s
s
d
RC Values
 Capacitance
 C = Cg = Cs = Cd = 2 fF/mm of gate width
 Values similar across many processes
 Resistance
 R  6 KW*mm in 0.6um process
 Improves with shorter channel lengths
 Unit transistors
 May refer to minimum contacted device (4/2 l)
 Or maybe 1 mm wide device
 Doesn’t matter as long as you are consistent
Inverter Delay Estimate
 Estimate the delay of a fanout-of-1 inverter

2C

2C 2C
2C 2C
2 Y 2
A Y
1 1 R C
C
R C C

C
Inverter Delay Estimate
 Estimate the delay of a fanout-of-1 inverter

2C

2C 2C
2C 2C
2 Y 2
A Y
1 1 R C
C
R C C

d = 6RC