Design Of Asychronous FIFO

Chekuri Lavanya (21MVD0066) Hemangi Gaikwad (21MVD0012) Sakshi Gandhewar (21MVD0056)

VLSI Design, SENSE VLSI Design, SENSE VLSI Design, SENSE
VIT Vellore VIT Vellore VIT Vellore
TamilNadu, India TamilNadu, India TamilNadu, India
chekuri.lavanya2021@vitstudent.ac.in hemangi.vijaykumar2021@vitstudent.a sakshi.gandhewar2021@vitstudent.ac.i
c.in n

Abstract— FIFOs are used to transfer data from one
clock domain to another. Asynchronous FIFOs had
become an important building block for designing
new systems. By using an asynchronous FIFO design
with grey pointer and dual flip-flop synchronizers,
we can transmit data safely without any data loss,
while also improving design efficiency. We also
tested for FIFO Empty and FIFO Full conditions.
The purpose of this work is to simulate and analyze
an asynchronous FIFO design using Verilog coding
and simulation is done on modelsim.
Keywords—FIFO, Asynchronous FIFO,
Synchronizer, gray counter, FIFO Full, FIFO
Empty
I. INTRODUCTION
A first-in, first-out data buffer is known as a FIFO. It
differs from regular memory in that it does not have
external read and write address lines. It's incredibly easy
to use. The drawback is that it can only be read and
written in a specific order, rather than randomly. It is
used to pass data between two different systems with
same clock with different technologies
FIFOs are primarily of two types:
Synchronous FIFO
Asynchronous FIFO
In synchronous FIFO, a single clock is used for both
write and read operations, and the clock frequency is the
same.
Two independent clocks are required for read and write
pointers in an asynchronous FIFO, and both pointers
must be accessed with two different clock frequencies.
One clock is used to write data into the memory, while
another is used to read data from the memory.
Inherently, FIFO designs have the issue of
synchronizing with other clock domain pointer logic
and safely controlling the read and write operations of
FIFO memory locations with user logic. The write clock
domain writes data into the FIFO, whereas the read
clock domain reads data out of the FIFO.
FIFO Full and Empty Conditions:
There are two scenarios to consider. The first is when
the FIFO is full, and the second is when the FIFO is
empty. It can be seen that the findings in both
circumstances reveal the condition of the control signal.
A. under the border condition, when full =1
When using FIFO write only (WR), full = 1, read = 1,
and empty= 1.
As shown in Fig. 4, the FIFO is full, indicating that the
incoming data is full. As a result, no data will be stored
in the buffer until the control signal wr en, which is
dependent on wr clk, is high.
changing signals on the same clock edge. The first fact
to remember about a Gray code is that the code distance
between any two adjacent words is just 1 (only one bit
can change from one Gray count to the next). The
second fact to remember about a Gray code counter is
that most useful Gray code counters must have power-
of-2 counts in the sequence. It is possible to make a
Gray code counter that counts an even number of
sequences but conversions to and from these sequences
is generally not as simple to do as the standard Gray
code.

// judge full
always@(posedge wr_clk) begin
if(wr_rst) full <= 0;
else if( (rd_ptr_grr[$clog2(DATA_DEPTH) - 1 : 0]
== wr_ptr_g[$clog2(DATA_DEPTH) - 1 : 0])
&&(rd_ptr_grr[$clog2(DATA_DEPTH)] !=
wr_ptr_g[$clog2(DATA_DEPTH)] ) ) begin
full <= 1;
end
else full <= 0;
end

B. when the value of empty =1 under the boundary

condition
Scenario: read (RD) is the sole option, hence write
(WR) is zero.
full=0 and empty=1. Figure 5 shows how FIFO works.
FIFO is empty, which signals that the incoming data is
full and needs to be cleared to make room for new data.
As a result, data will be kept in the buffer until the
control signal rd en, which is dependent on rd clk,
reaches a high level.
// judge empty

always@(posedge rd_clk) begin

if(rd_rst) empty <= 0;
else if(wr_ptr_grr == rd_ptr_g) begin
empty <= 1;
end
else empty <= 0;
end

USE OF GREY COUNTER:

A common approach to FIFO counter-pointers, is to
use Gray code counters. Gray codes only allow one bit
to change for each clock transition, eliminating the
problem associated with trying to synchronize multiple
SYNCHRONIZERS:
Synchronizers are made up of two D Flip Flop's and are
very simple to use. Because the FIFO operates on two
different clock domains, the Write and Read pointers
must be synchronised in order to generate empty and
full logic, which is then used to address the FIFO
memory. The diagram below depicts how
synchronisation occurs; the logic is straightforward.
What we're trying to accomplish here is feed the Write
Pointer to a D Flip Flop that's driven by the Read clock,
and the Read Pointer to a D Flip Flop that's driven by
the Write clock, resulting in Read Pointer.
II. ASYNCHRONOUS FIFO DESIGN
a) Review of FIFO uses:
As noted in the last piece, before redesigning the
asynchronous FIFO circuit, it is required to explain the
function of FIFO:
The Domain of the Cross Clock
We need to create asynchronous FIFO to interact across
clock domains in order to make data secure, correct, and
reliable.
As previously said on my blog: Discuss the concept of
time series design (1) The scope of the cross-clock is
designed, not confined!
Because pseudo route limitations are frequently applied
across clock domain paths in time series analysis, we
must handle the cross-clock domain data transfer
problem at design time, which is where asynchronous
FIFO comes in handy.
• Buffer data before transmitting it off-chip (to DRAM
or SRAM, for example);
• Buffer data for later viewing by software;
• Store data for backup
They all essentially mean the same thing.
To summarise, FIFO can buffer or cache data that has
to be cached before being read out of FIFO for
processing, such as abrupt data. This also ensures that
no data will be lost.
According to some statements on the Internet, data is
written excessively quickly and at extended intervals,
causing data to be written abruptly.
It can temporarily store data and smooth subsequent
processing by setting a specific depth of FIFO.
III. REVIEW OF ASYNCHRONOUS FIFO PRINCIPLES
The underlying principle is the same whether
synchronous FIFO or asynchronous FIFO is used. The
adage "first in, first out" is self-evident. The link
between the read and write pointers is the basis for the
empty judgement. Asynchronous FIFO pointers must
also be handled, such as grey code processing, to reduce
read pointer to write pointer clock domain or write
pointer to read finger synchronisation. The possibility
of metastability in the clockwise domain is low since
the Gray code only changes one bit at a time, drastically
reducing the chance of metastability when data is sent
across the clock domain. The empty state of the FIFO is
then determined by comparing the synchronisation.
The read and write pointers are all zero at the start, and
the FIFO must be empty; after that, a sequence of read
and write operations on the FIFO have been performed,
resulting in changes in the read and write pointer
relationship, which can be classified into two situations:
Write is faster than read, or the Write Pointer bends
beyond the Append Pointer, and FIFO is full when the
Write Pointer goes around the back of the Read Pointer
again and coincides with the Read Pointer, that is, when
the two are equal.
IV. CALCULATION OF THE MINIMUM DEPTH OF
ASYNCHRONUS FIFO
The FIFO is only useful for short bursts of data, not for
continuous data output and input. If a continuous stream
of data is present, the needed FIFO size should be
unlimited. To establish the depth of the FIFO, it is
important to know the burst rate, burst size, frequency,
and so on.
FIFO DEPTH CALCULATION FLOW:
1.If fw>fr, determine the frequency fw of the read clock
fr and the write clock.
2.Calculate the cycle Tr and Tw of reading and writing
data once, using fr and fw as inputs and T= 1/f as output.
3.Calculate how long it takes to write so much data
based on the size of the burst write length.
Tw*len = tw
4.Calculate the amount of data read based on the writing
time tw n = tw/Tr.
5.The FIFO's minimum depth is equal to len-n.
Case 1: The write clock is faster than the read clock, and
there are no idle cycles in the process of writing and
reading
Writing frequency =fA=80MHz
Read frequency =fB=50MHz
Brust Length=No.of data items to be transferred =120
There are no idle cycles in both reading and writing
which means that,all the items in the brust will be
written and read in consecutive clock cycles.

Analysis process
write clock cycle Tw = 1000/80 ns = 12.5ns;
similarly, read clock cycle is 20ns;
burst write length is 120 data, and it takes 120*12.5 =
1500ns to write 120 data;
read out within 1500ns Data 1500/20ns = 75;
so the minimum FIFO depth is 120 - 75 = 45;

Case 2: The write clock is slower than the read clock,

and there are no idle cycles in the process of writing and
reading
Writing frequency =fA=30MHz
Read frequency =fB=50MHz
Brust Length=No.of data items to be transferred =120
There are no idle cycles in both reading and writing
which means that,all the items in the brust will be
written and read in consecutive clock cycles.
Analysis Process: In this case, data loss will never
happen the depth of the fifo is 1.
In order to obtain a more secure FIFO depth, we must
examine the worst-case scenario in the event of data
loss; in this situation, the gap between the data rates
for writes and reads should be the greatest. As a result,
the maximum data rate should be considered for write
operations, while the minimum data rate should be
considered for read operations. The fastest write data
rate should be the fourth example, as shown in the
table above, and the write operation should be finished
in the shortest time.

since the burst write length is 160, 160 clocks write

160 data;
since the read speed is 10 clocks read 8 data, so one
data needs 10/8 clocks;
so 160 clocks read 160 8/10 = 128 data;
so the minimum depth of the FIFO is 160-128=32.
 V. SIMULATION RESULTS

Fig1: Simulation of Asynchronous FIFO Write operation

Fig 5: Generated schematic of the presented asynchronous
FIFO design

VI. CONCLUSION
Since the data provided by the write clock domain to the
asynchronous fifo is identical to the data received from
the asynchronous fifo by the read clock domain.
Consequently, the Functionally, asynchronous fifo is
correct. As shown in Figure 1and 2. The application of
Grey coding scheme effectively improves the stability
of circuit. The proper use of level synchronizer greatly
decreases the probability of semi-stable state.
Fig2: Simulation of Asynchronous FIFO Read operation

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