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EX.NO: 3
DATE: 3.3.2011

SYSTEM DESIGN USING PLL

AIM:
To design and implement a system using Phase Locked Loop (PLL) using the
Modelsim tool and to verify its operation.

ALGORITHM:

Step1: Define the specifications and initialize the design.

Step2: Declare the name of the entity and architecture by using VHDL source
code.
Step3: Write the source code in VERILOG
Step4: Check the syntax and debug the errors if found, obtain the synthesis
report.
Step5: Verify the output by simulating the source code.
Step6: Write all possible combinations of input using the test bench.
Step7: Obtain the place and route report.

THEORY:

A Phase Locked Loop (PLL) is a closed loop feedback control system that
generates and output a signal in relation to the frequency and phase of an input signal. A
Phase Locked Loop (PLL) circuit responds to both the frequency and the phase of the input
signals, automatically raising or lowering the frequency of a control oscillator until its
matched to the reference in both frequency and phase. This type of mechanism is widely
used in radio, telecommunications, computers and other electronic applications where its
desired to stabilize a generated signal or to detect signals in the presence of noise. Since an
integrated circuit can hold a complete Phase Locked Loop (PLL) building block, the
technique widely used in modern electronic devices, with signal frequencies from a
fraction of a cycle Per second up to many gigahertz.
Frequency is the derivative of phase. Keeping the input and output phase in lock
step implies keeping the input and output frequencies in lock step. Consequently, a phase-
locked loop can track an input frequency, or it can generate a frequency that is a multiple
of the input frequency. The former property is used for demodulation, and the latter
property is used for indirect frequency synthesis.

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LOGIC DIAGRAM:

PROGRAM:

PLL VHDL SOURCE CODE:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity pll1 is
port(datain:in std_logic;
clock: in std_logic;
rx_clock: out std_logic;
dataout: out std_logic;
clrdcd: in std_logic;
dcd:out std_logic);
end pll1;

architecture Behavioral of pll1 is

signal counter:std_logic_vector(4 downto 0):="00000";
signal dcd_cntr:std_logic_vector(7 downto 0):="00000000";
signal edge:std_logic;

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signal dly_data:std_logic;
signal ql:std_logic;
signal qe:std_logic;
signal enable:std_logic;
signal increment:std_logic:='0';
signal decrement:std_logic:='0';
signal clear_dcd:std_logic:='0';
signal reset_dcd:std_logic:='0';
begin
rx_clock<=counter(4);
process(clock,clrdcd,reset_dcd)
begin
if(clock'event and clock='1')then
clear_dcd<=reset_dcd or clrdcd;
end if;
end process;
process(clock,datain)
begin
if(clock'event and clock='1')then
dataout<=datain;
end if;
end process;
process(clock,enable,clrdcd)
begin
if(clock'event and clock='1')then
if(enable='1')then
counter<=counter+'1';
else
counter<=counter;
end if;
end if;
end process;
process(counter)
begin
if(counter="10000"or counter="01111")then
ql<='0';
qe<='0';
elsif(counter(4)='1')then
ql<='1';
qe<='0';
else
ql<='0';
qe<='1';
end if;
end process;
process(clock,enable,clrdcd)

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begin
if(clock'event and clock='1')then
if(qe='1' and edge='1')then
increment<='1';
end if;
if(ql='1' and edge='1')then
decrement<='1';
end if;
if(enable='1')then
if(increment='1')then
increment<='0';
enable<='1';
else
enable<='0';
end if;
else
if(decrement='1')then
decrement<='0';
enable<='0';
else
enable<='1';
end if;
end if;
end if;
end process;
process(clock,edge,counter,clear_dcd)
begin
if(clear_dcd='1')then
dcd_cntr<=(others=>'0');
dcd<='0';
reset_dcd<='0';
elsif(counter(4)'event and counter(4)='0')then
if(edge='0')then
if(dcd_cntr=255)then
dcd<='1';
dcd_cntr<=dcd_cntr;
else
dcd<='0';
dcd_cntr<=dcd_cntr+1;
end if;
else
reset_dcd<='1';
end if;
end if;
end process;
process(clock,datain)

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begin
if(clock'event and clock='1')then
edge<=dly_data xor datain;
dly_data<=datain;
end if;
end process;
end Behavioral;

SYNTHESIS REPORT:

================================================================
=========
* Synthesis Options Summary *
================================================================
=========
---- Source Parameters
Input File Name : "pll1.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO

---- Target Parameters

Output File Name : "pll1"
Output Format : NGC
Target Device : xc3s400-5-pq208

---- Source Options

Top Module Name : pll1
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : lut
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : YES
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : YES
Resource Sharing : YES
Asynchronous To Synchronous : NO
Multiplier Style : auto
Automatic Register Balancing : No

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---- Target Options

Add IO Buffers : YES
Global Maximum Fanout : 500
Add Generic Clock Buffer(BUFG) :8
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Yes
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : auto
Equivalent register Removal : YES

---- General Options

Optimization Goal : Speed
Optimization Effort :1
Library Search Order : pll1.lso
Keep Hierarchy : NO
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator :/
Bus Delimiter : <>
Case Specifier : maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta :5

================================================================
=========

================================================================
=========
* HDL Compilation *
================================================================
=========
Compiling vhdl file "E:/pll/pll.vhd" in Library work.
Architecture behavioral of Entity pll1 is up to date.

================================================================

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=========
* Design Hierarchy Analysis *
================================================================
=========
Analyzing hierarchy for entity <pll1> in library <work> (architecture <behavioral>).

================================================================
=========
* HDL Analysis *
================================================================
=========
Analyzing Entity <pll1> in library <work> (Architecture <behavioral>).
WARNING:Xst:819 - "E:/pll/pll.vhd" line 120: The following signals are missing in the
process sensitivity list:
counter<4>.
Entity <pll1> analyzed. Unit <pll1> generated.

================================================================
=========
* HDL Synthesis *
================================================================
=========

Performing bidirectional port resolution...

Synthesizing Unit <pll1>.

Related source file is "E:/pll/pll.vhd".
Register <dly_data> equivalent to <dataout> has been removed
Found 1-bit register for signal <dataout>.
Found 1-bit register for signal <dcd>.
Found 1-bit register for signal <clear_dcd>.
Found 5-bit up counter for signal <counter>.
Found 8-bit up counter for signal <dcd_cntr>.
Found 1-bit register for signal <decrement>.
Found 1-bit register for signal <edge>.
Found 1-bit xor2 for signal <edge$xor0000> created at line 138.
Found 1-bit register for signal <enable>.
Found 1-bit register for signal <increment>.
Found 1-bit register for signal <reset_dcd>.
Summary:
inferred 2 Counter(s).
inferred 8 D-type flip-flop(s).
Unit <pll1> synthesized.

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================================================================
=========
HDL Synthesis Report

Macro Statistics
# Counters :2
5-bit up counter :1
8-bit up counter :1
# Registers :8
1-bit register :8
# Xors :1
1-bit xor2 :1

================================================================
=========

================================================================
=========
* Advanced HDL Synthesis *
================================================================
=========

Loading device for application Rf_Device from file '3s400.nph' in environment

C:\Xilinx92i.

================================================================
=========
Advanced HDL Synthesis Report

Macro Statistics
# Counters :2
5-bit up counter :1
8-bit up counter :1
# Registers :8
Flip-Flops :8
# Xors :1
1-bit xor2 :1

================================================================
=========

================================================================
=========
* Low Level Synthesis *
================================================================

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=========

Optimizing unit <pll1> ...

Mapping all equations...

Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block pll1, actual ratio is 0.
FlipFlop dataout has been replicated 1 time(s) to handle iob=true attribute.

Final Macro Processing ...

================================================================
=========
Final Register Report

Macro Statistics
# Registers : 22
Flip-Flops : 22

================================================================
=========

================================================================
=========
* Partition Report *
================================================================
=========

Partition Implementation Status

-------------------------------

No Partitions were found in this design.

-------------------------------

================================================================
=========
* Final Report *
================================================================
=========
Final Results
RTL Top Level Output File Name : pll1.ngr
Top Level Output File Name : pll1
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO

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Design Statistics
# IOs :6

Cell Usage :
# BELS : 45
# GND :1
# INV :4
# LUT1 :7
# LUT2 :5
# LUT2_L :1
# LUT3 :4
# LUT3_L :1
# LUT4 :5
# LUT4_D :2
# MUXCY :7
# VCC :1
# XORCY :7
# FlipFlops/Latches : 22
# FD :4
# FDCE :8
# FDCE_1 :2
# FDE :7
# FDS :1
# Clock Buffers :1
# BUFGP :1
# IO Buffers :5
# IBUF :2
# OBUF :3
================================================================
=========

Device utilization summary:

---------------------------

Selected Device : 3s400pq208-5

Number of Slices: 16 out of 3584 0%

Number of Slice Flip Flops: 20 out of 7168 0%
Number of 4 input LUTs: 29 out of 7168 0%
Number of IOs: 6
Number of bonded IOBs: 6 out of 141 4%
IOB Flip Flops: 2
Number of GCLKs: 1 out of 8 12%

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RTL SCHEMATIC:

SIMULATION RESULTS:

RESULT:
Thus the system was designed using Phase Locked Loop (PLL) using the
Modelsim tool and its operation was verified.

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