VLSI 設計導論 期末作業

2022/1/3
1. Design CMOS static logic gates with the Boolean functions below.
(a) 4-input NAND gate

(b) Y   A1  A2  A3  B1  B2  C1

(c) Y  A1 A2 A3  B1B2  C1C2C3

2. Draw the stick diagram of the logic gates in the following.

(a) 2-input NOR gate
(b) 4-input NAND gate
(Note : Blue=> Metal, Red=> Gate Poly, Black=> P+ Diffusion,
Gray (Pencil)=> N+ Diffusion, X=> Contact)
3. Consider the circuit shown in Fig. 3.
a. Determine the logic function F.
b. Design a circuit to implement the same logic function, but using NOR gates. Draw a
transistor-level schematic and use pseudo nMOS technology.
c. Design a circuit to implement the same logic function, but use an AOI
(AND-OR-INVERT) gate. Draw a transistor-level schematic and use CMOS technology.

Figure 3 Figure 4
4. Consider the logic circuit shown in Fig. 4, determine the logic function F.
5. Design a circuit to implement the truth table shown in Fig. 5. A gate-level design is
sufficient.

Figure 5
6. The circuit you have designed in Problem 5 is embedded in the larger circuit shown in Fig. 6.
Complete the timing diagram for the output.

Figure 6
7. Assume the rising and falling propagation delay of a positive-edge triggered D-Flip/Flop is
2ns and 1ns, respectively.
Please draw the timing diagram of the Q-output of D-Flip/Flop.
Let each division of time axis be 1ns. The initial condition of the Q-output is high.

Figure 7