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Minimization of Moore Incompletely Specified Finite State Machines by Merging Two States
Minimization of Moore Incompletely Specified Finite State Machines by Merging Two States
1. Introduction
A finite state machine (FSM) is a model used for the development of various
computation structures like sequential circuits, digital control systems, microprocessor control
circuits, digital communication systems, iterative networks, communication protocols, etc. For
various reasons the transitions between FSM states or FSM outputs are not completely specified.
An incompletely specified FSM (ISFSM) is one where either the next state or the output is not
specified for at least one input vector. A minimization of ISFSMs is an important task in the
optimal design of sequential circuits.
A general theory for incompletely specified machines was first developed in [1]. The
standard approach to the problem of ISFSM’s state reduction is based on a generation of sets of
compatible states (or compatibles) and the finding of a minimal closed cover. The problem of
minimization of ISFSMs is an NP-complete problem [2] and has been studied by several authors
[3-9]. In [3], prime classes are proposed and the minimization problem is solved by using an
integer linear programming approach. The exact and heuristic algorithms of FSM minimization
for using in practice are proposed in [4]. In [5], a program called STAMINA is presented; it runs
in exact and heuristic modes using explicit enumeration for the state minimization problem. An
exact state minimization technique using implicit enumeration of the compatibles is considered
in [6]. In [7], an exact state minimization algorithm based on mapping ISFSMs to tree FSMs is
presented. A heuristic called void that follows a strategy of handling the closure condition first
and satisfying the cover condition afterwards is proposed in [8]. In [9] a branch-and-bound
search technique for identification of sets of compatible states is described.
A new impulse to the development of the FSM theory was given by the modern circuitry
based on programmable logic such as Field Programmable Gate Array (FPGA), Complex
Programmable Logic Device (CPLD), and System on Programmable Chip (SOPC) [10]. The
new FSM’s structural models and methods for their synthesis were developed [11-13]; they
provide for efficient application of the architectural capabilities of modern programmable logic.
However, a necessary condition for the application of new synthesis methods is the requirement
that an FSM must be of a certain type: an automata Mealy [14] or an automata Moore [15].
Known programs of minimization of FSM internal states, for example the program STAMINA
[16], do not distinguish automaton types (Mealy or Moore). So after minimization, a Moore
automaton may be converted into a Mealy-type one. Therefore, the development of efficient
methods for minimization of large-size ISFSMs that do not change the type of the original FSM
is a topical problem. In other words, if the original FSM is a Moore one, its must remain a Moore
FSM after the minimization.
In this paper, a heuristic method for minimizing Moore ISFSMs with unspecified values
of the output variables is proposed. The presented method guarantees that after minimization an
FSM does not change its type. The method is based on an operation merging of two states. In
addition to reducing internal states, this method minimizes the number of FSM transitions and
FSM input variables. Moreover, to represent the FSM, a transition list is used, unlike the
traditional approaches that use flow and output tables. The use of the transition list instead of the
traditional flow and output tables allows applying this method for the minimization of FSMs of a
very big size. Note, the transition list is widely applied to describe FSM behavior in most
hardware description languages, such as VHDL, Verilog, AHDL, etc. A similar task for
completely specified FSMs has been considered in [17,18] (for automata Mealy) and [19,20] (for
automata Moore). The method of splitting internal states [21] is used for the transformation of
Mealy FSM to Moore FSM.
This paper is organized as follows. The preliminaries and a main strategy of the offered
approach are presented in Section 2. Problems of two states merging as well as the generation of
wait states at the state merging are considered in Section 3. A general algorithm for ISFSM
minimization is presented in Section 4 and various minimization algorithms are described here
too. Experimental researches are analyzed in Section 5. Finally, concluding remarks and future
work are discussed in Conclusions.
2. Preliminaries
An ISFSM can have incompletely specified outputs and incompletely specified
transitions between states. The incompletely specified outputs take place when a value of the
output variable does not influence on the functioning of the controlled object, for example, when
a carry voltage is not applied to the control object. The incompletely specified transitions arise
when the separate values of the input vectors never appear on the FSM inputs, for example, the
codes of hexadecimal figures A-F at work in a decimal notation.
In practice, designers usually redefine the unspecified transitions by transitions to a
present state, or to a reset state, or to an additional state, where an error signal is generated. It is
an increase of the functional reliability for the digital systems. In the offered approach, we define
the unspecified values only of the output variables and we keep the unspecified transitions
without any changes.
By L denote the number of FSM input variables of a set X = {x1,…,xL}, by N denote the
number of FSM output variables of a set Y = {y1,…,yN}, by M denote the number of FSM internal
states of a set A = {a1,…,aM}, and by R denote the minimal number of bits required to encode
internal states, where R = intlog2M.
An FSM behavior is described by the transition list. The transition list is a table with four
columns: am, as, X(am,as), and Y(am,as). Each row of the transition list corresponds to one the FSM
transitions. Column am contains the state where the transition begins (a present state), column as
contains the state where the transition ends (a next state), column X(am,as) contains the set of
values of the input variables that initiates this transition (a transition condition or a input vector),
and column Y(am,as) contains the set of values of the output variables that is generated by the
FSM at this transition (a output vector). Since in a Moore FSM output variables depend on the
present state only, the last column for Moore FSMs is often denoted as Y(am).
An ISFSM output vector is represented by ternary vector. For example, Y(am)=”01-0”,
where 0 denotes a zero value, 1 denotes a unity value, and dash (“-“) denotes a don’t care value
of correspondent output variable.
Let P(ai) be a set of the transitions from the state ai, let C(ai) be a set of the transitions to
state ai, let A(ai) be a set of the next states for the transitions from state ai, and let Z(ai) be a set of
the transition conditions from state ai, ai A.
Let zh be any transition condition from state ai, zh Z(ai), ai A. The transition condition
may be described in column X(am,as) in the form of a conjunction of FSM input variables. The
transition condition can also be represented by a ternary vector. For example, zh = “1-10-0”
where the unit (1) means that the corresponding input variable is included in conjunction with
the direct form, zero (0) means that the corresponding input variable is included in conjunction
with the inversed form, and dash (“-“) means that the value of the input variable does not affect
the FSM transition. Since FSM behavior must be deterministic, all transition conditions from
every FSM state should be mutually orthogonal.
Definition 1 Two transition conditions are orthogonal if they have different significant
values (0 or 1) in at least one position.
For instance, the transition conditions z1 = “00-10-“ and z2 = “11-10-“ are orthogonal
while z1 and z3 = “000101“ are not. The ternary vector of dashes only corresponds to the FSM
unconditional transition.
Two FSM states can be merged, i.e. ai and aj replaced by one state ai_j, if they are
equivalent. An equivalency of the FSM states means that FSM behavior does not change after
these states are merged. FSM behavior does not change after the states ai and aj are merged if the
transition conditions from states ai and aj that lead to different states are orthogonal. If there are
the transitions from states ai and aj that lead to the same states, the transition conditions for such
transitions should be equal. Moreover, the output vectors that are generated in states ai and aj
should not be orthogonal. Notice, that wait states can be formed at the merging of FSM states.
The main strategy of the offered approach consists in a finding of set D of all pairs of the
FSM states for which the merging conditions are satisfied. Then for each pair of states of set D, a
trial merging is carried out. From set D, such the pair (ai,aj) is selected for merging, that it leaves
the greatest possibilities for merging of other pairs of the FSM states. The given process repeats
until it is possible to merge at least one pair of the FSM states.
5. Experimental researches
The proposed method for minimization of Moore-type ISFSM was implemented in a
program called ZUBR [23]. To verify the efficiency of the offered method, the MCNC
benchmarks [16] of FSMs are used. The experimental results are presented in Table 4, where
Name is the name of the benchmark example; L, N, M0, and P0 are, respectively, the number of
inputs, outputs, internal states, and transitions of the initial FSM; M1, and P1 are the number of
internal states, and transitions of FSM after the transformation of the type Mealy automata to the
type Moore automata [21]; M2, and P2 are the number of internal states and transitions of FSM
after applying the proposed method; M1/M2, and P1/P2 are rations of the corresponding
parameters; and mid is the arithmetic mean value.
The analysis of Table 4 shows that the application of the proposed method allows
reducing the number of internal states of the initial FSM on average by 1.36 times, and on
occasion (an example train11) by 2.17 times. Similarly, the average reduction of the number of
FSM transitions is 1.91 times, and on occasion (an example tbk) 7.97 times.
Conclusions
In this paper, a heuristic method for minimization of Moore ISFSM with unspecified
values of the output variables has been considered. The main feature of the given approach is
that it does not change the type of FSM (as the program STAMINA), i.e. after minimization the
FSM remains a Moore-type FSM. In the proposed method, the initial FSM is represented by the
transition list and the minimization of the FSM states is performed by merging of two states, so it
allows applying this method for the minimization of FSMs of a very large size. In contrast to
traditional approaches, the proposed method allows minimizing not only the number of FSM
states, but also the number of FSM transitions and input variables. The efficiency of the
proposed method was verified by the results of the experimental researches for MCNC FSM
benchmarks. This method allows reducing the number of FSM states on average by 1.36 times
(on occasion by 2.17 times) and the number of FSM transitions on average by 1.91 times (on
occasion by 7.97 times).
The application of the given method during digital system design on programmable logic
will be favorable to decreasing the cost, and lowering power, as well as to increasing the speed
for FSM realization.
The presented method can be modified for the merging possibility of a group of states
consisting of more than two states. Besides, further perfection of the presented algorithm can go
by the way of a consideration of incompletely specified values for the transition functions as
additional conditions for the merging possibility of FSM internal states.
Acknowledgments
This study was supported in part by the Bialystok University of Technology, Faculty of
Computer Science, Bialystok, Poland, grant no. S/WI/4/2008.
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