IRF520

Data Sheet January 2002

9.2A, 100V, 0.270 Ohm, N-Channel Features

Power MOSFET • 9.2A, 100V
This N-Channel enhancement mode silicon gate power field
• rDS(ON) = 0.270Ω
effect transistor is an advanced power MOSFET designed,
tested, and guaranteed to withstand a specified level of • SOA is Power Dissipation Limited
energy in the breakdown avalanche mode of operation. All of • Single Pulse Avalanche Energy Rated
these power MOSFETs are designed for applications such
as switching regulators, switching convertors, motor drivers, • Nanosecond Switching Speeds
relay drivers, and drivers for high power bipolar switching • Linear Transfer Characteristics
transistors requiring high speed and low gate drive power.
• High Input Impedance
These types can be operated directly from integrated
circuits. • Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Formerly developmental type TA09594.
Components to PC Boards”

Ordering Information Symbol

PART NUMBER PACKAGE BRAND
D
IRF520 TO-220AB IRF520

NOTE: When ordering, use the entire part number.

G

Packaging
JEDEC TO-220AB

SOURCE
DRAIN
GATE

DRAIN (FLANGE)

©2002 Fairchild Semiconductor Corporation IRF520 Rev. B

 IRF520

Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified

IRF520 UNITS
Drain to Source Breakdown Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDS 100 V
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR 100 V
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID 9.2 A
TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID 6.5 A
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM 37 A
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS ±20 V
Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PD 60 W
Dissipation Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.4 W/oC
Single Pulse Avalanche Energy Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .EAS 36 mJ
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG -55 to 175 oC

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL 300 oC
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg 260 oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:
1. TJ = 25oC to 150oC.

Electrical Specifications TC = 25oC, Unless Otherwise Specified

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Drain to Source Breakdown Voltage BVDSS ID = 250µA, VGS = 0V (Figure 10) 100 - - V
Gate to Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA 2.0 - 4.0 V
Zero Gate Voltage Drain Current IDSS VDS = 95V, VGS = 0V - - 250 µA
VDS = 0.8 x Rated BVDSS, VGS = 0V, TJ = 150oC - - 1000 µA
On-State Drain Current (Note 2) ID(ON) VDS > ID(ON) x rDS(ON)MAX, VGS = 10V (Figure 7) 9.2 - - A
Gate to Source Leakage Current IGSS VGS = ±20V - - ±100 nA
Drain to Source On Resistance (Note 2) rDS(ON) ID = 5.6A, VGS = 10V (Figure 8, 9) - 0.25 0.27 Ω
Forward Transconductance (Note 2) gfs VDS ≥ 50V, ID = 5.6A (Figure 12) 2.7 4.1 - S
Turn-On Delay Time td(ON) VDD = 50V, ID ≈ 9.2A, RG = 18Ω, RL = 5.5Ω - 9 13 ns
MOSFET Switching Times are Essentially
Rise Time tr - 30 63 ns
Independent of Operating
Turn-Off Delay Time td(OFF) Temperature - 18 70 ns
Fall Time tf - 20 59 ns
Total Gate Charge Qg(TOT) VGS = 10V, ID = 9.2A, VDS = 0.8 x Rated BVDSS, - 10 30 nC
(Gate to Source + Gate to Drain) Ig(REF) = 1.5mA (Figure 14) Gate Charge is
Essentially Independent of Operating
Gate to Source Charge Qgs - 2.5 - nC
Temperature
Gate to Drain “Miller” Charge Qgd - 2.5 - nC
Input Capacitance CISS VDS = 25V, VGS = 0V, f = 1MHz - 350 - pF
(Figure 11)
Output Capacitance COSS - 130 - pF
Reverse Transfer Capacitance CRSS - 25 - pF
Internal Drain Inductance LD Measured From the Contact Modified MOSFET - 3.5 - nH
Screw On Tab To Center of Symbol Showing the
Die Internal Devices
Inductances
Measured From the Drain - 4.5 - nH
Lead, 6mm (0.25in) From D
Package to Center of Die LD
Internal Source Inductance LS Measured From the Source G - 7.5 - nH
Lead, 6mm (0.25in) From
LS
Header to Source Bonding
Pad S

Thermal Resistance Junction to Case RθJC - - 2.5 oC/W

Thermal Resistance Junction to Ambient RθJA Free Air Operation - - 80 oC/W

©2002 Fairchild Semiconductor Corporation IRF520 Rev. B

 IRF520

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Continuous Source to Drain Current ISD Modified MOSFET Symbol D

- - 9.2 A
Showing the Integral
Pulse Source to Drain Current (Note 3) ISDM - - 37 A
Reverse P-N Junction Diode

Source to Drain Diode Voltage (Note 2) VSD TJ = 25oC, ISD = 9.2A, VGS = 0V (Figure 13) - - 2.5 V

Reverse Recovery Time trr TJ = 25oC, ISD = 9.2A, dISD/dt = 100A/µs 5.5 100 240 ns

Reverse Recovered Charge QRR TJ = 25oC, ISD = 9.2A, dISD/dt = 100A/µs 0.17 0.5 1.1 µC

NOTES:
2. Pulse test: pulse width ≤ 300µs, duty cycle ≤ 2%.
3. Repetitive rating: pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3).
4. VDD = 25V, starting TJ = 25oC, L = 640mH, RG = 25Ω, peak IAS = 9.2A.

Typical Performance Curves Unless Otherwise Specified

1.2 10
POWER DISSIPATION MULTIPLIER

1.0 8
ID, DRAIN CURRENT (A)

0.8
6

0.6
4
0.4

2
0.2

0 0
0 25 50 75 100 125 150 175 25 50 75 100 125 150 175
TC , CASE TEMPERATURE (oC) TC, CASE TEMPERATURE (oC)

FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
TEMPERATURE CASE TEMPERATURE

10
THERMAL IMPEDANCE (oC/W)

0.5
ZθJC, TRANSIENT

1
0.2
0.1 PDM
0.05
0.1 0.02 t1
0.01 t2
NOTES:
SINGLE PULSE DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC + TC
0.01
10-5 10-4 10-3 10-2 0.1 1 10
t1, RECTANGULAR PULSE DURATION (s)

FIGURE 3. MAXIMUM TRANSIENT THERMAL IMPEDANCE

©2002 Fairchild Semiconductor Corporation IRF520 Rev. B

 IRF520

Typical Performance Curves Unless Otherwise Specified (Continued)

100 15
10V VGS = 8V PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
10µs
12

ID, DRAIN CURRENT (A)

VGS = 7V
ID, DRAIN CURRENT (A)

100µs
10
9
1ms VGS = 6V

6
OPERATION IN THIS 10ms
1 AREA IS LIMITED
BY rDS(ON)
3 VGS = 5V
TC = 25oC
TJ = MAX RATED
VGS = 4V
SINGLE PULSE
0.1 0
1 10 100 1000 0 10 20 30 40 50
VDS , DRAIN TO SOURCE VOLTAGE (V) VDS, DRAIN TO SOURCE VOLTAGE (V)

FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. OUTPUT CHARACTERISTICS

15 102
PULSE DURATION = 80µs VDS ≥ 50V

ID(ON), ON-STATE DRAIN CURRENT (A)

VGS = 10V
DUTY CYCLE = 0.5% MAX PULSE DURATION = 80µs
VGS = 8V DUTY CYCLE = 0.5% MAX
12
ID, DRAIN CURRENT (A)

VGS = 7V 10
9

6 VGS = 6V
1
175oC 25oC
3
VGS = 5V
VGS = 4V
0 0.1
0 1 2 3 4 5 0 2 4 6 8 10
VDS, DRAIN TO SOURCE VOLTAGE (V) VGS , GATE TO SOURCE VOLTAGE (V)

FIGURE 6. SATURATION CHARACTERISTICS FIGURE 7. TRANSFER CHARACTERISTICS

2.5 3.0
rDS(ON), DRAIN TO SOURCE ON RESISTANCE

PULSE DURATION = 80µs ID = 9.2A, VGS = 10V

DUTY CYCLE = 0.5% MAX PULSE DURATION = 80µs
NORMALIZED ON RESISTANCE

DUTY CYCLE = 0.5% MAX

2.0 2.4

1.5 1.8

VGS = 10V
1.0 1.2

0.5 0.6

VGS = 20V
0 0
0 8 16 24 32 40 -60 -40 -20 0 20 40 60 80 100 120 140 160 180
ID, DRAIN CURRENT (A) TJ, JUNCTION TEMPERATURE (oC)

FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE FIGURE 9. NORMALIZED DRAIN TO SOURCE ON

VOLTAGE AND DRAIN CURRENT RESISTANCE vs JUNCTION TEMPERATURE

©2002 Fairchild Semiconductor Corporation IRF520 Rev. B

 IRF520

Typical Performance Curves Unless Otherwise Specified (Continued)

1.25 1000
ID = 250µA VGS = 0V, f = 1MHz
CISS = CGS + CGD
NORMALIZED DRAIN TO SOURCE

1.15 800 CRSS = CGD

COSS ≈ CDS + CGD
BREAKDOWN VOLTAGE

C, CAPACITANCE (pF)
1.05 600

0.95 400 CISS

0.85 200 COSS

CRSS
0.75 0
-60 0 60 120 180 1 10 102
TJ, JUNCTION TEMPERATURE (oC) VDS, DRAIN TO SOURCE VOLTAGE (V)

FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
VOLTAGE vs JUNCTION TEMPERATURE

5 100
PULSE DURATION = 80µs
ISD, SOURCE TO DRAIN CURRENT (A) DUTY CYCLE = 0.5% MAX
gfs, TRANSCONDUCTANCE (S)

4 TJ = 25oC

10
3
TJ = 175oC

2 TJ = 175oC TJ = 25oC
1

1
VDS ≥ 50
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX 0.1
0
0 3 6 9 12 15 0 0.4 0.8 1.2 1.6 2.0
ID, DRAIN CURRENT (A) VSD, SOURCE TO DRAIN VOLTAGE (V)

FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE

20
ID = 9.2A
VGS, GATE TO SOURCE VOLTAGE (V)

16 VDS = 20V
VDS = 50V
VDS = 80V
12

0
0 3 6 9 12 15
Qg, GATE CHARGE (nC)

FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE

©2002 Fairchild Semiconductor Corporation IRF520 Rev. B

 IRF520

Test Circuits and Waveforms

VDS
BVDSS

L tP
VDS

VARY tP TO OBTAIN IAS

+ VDD
REQUIRED PEAK IAS RG
VDD
VGS -
DUT

tP
0V IAS
0
0.01Ω
tAV

FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS

tON tOFF

td(ON) td(OFF)

tr tf
RL VDS
90% 90%

+
VDD 10% 10%
RG
- 0

DUT 90%

VGS 50% 50%

PULSE WIDTH
VGS 10%
0

FIGURE 17. SWITCHING TIME TEST CIRCUIT FIGURE 18. RESISTIVE SWITCHING WAVEFORMS

VDS
CURRENT (ISOLATED
REGULATOR SUPPLY)
VDD

SAME TYPE Qg(TOT)

AS DUT VGS
12V
0.2µF 50kΩ Qgd
BATTERY
0.3µF
Qgs

D
VDS

G DUT
0

Ig(REF) S
0
VDS IG(REF)
IG CURRENT ID CURRENT
SAMPLING SAMPLING
RESISTOR RESISTOR 0

FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS

©2002 Fairchild Semiconductor Corporation IRF520 Rev. B

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Definition of Terms

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Advance Information Formative or This datasheet contains the design specifications for
In Design product development. Specifications may change in
any manner without notice.

Preliminary First Production This datasheet contains preliminary data, and

supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.

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any time without notice in order to improve design.

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that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.

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