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END SEMESTER EXAMINATION : JANUARY, 2022

CSE207 DIGITAL ELECTRONICS AND COMPUTER ORGANIZATION

[ET]
Time: 2½ Hrs Maximum Marks: 60
Note: Attempt questions from all sections as directed.

Section A: Attempt any four questions out of five. Each question carries 06 marks. [24 Marks]
Q1. A digital computer has a common bus system for 16 registers of 32 bits each. The bus is
constructed with multiplexers.
a. How many selection inputs are there in each multiplexer?
b. What size of multiplexers are needed?
c. How many multiplexers are there in the bus?
Q2. The content of AC in the basic computer is hexadecimal A937 and the initial value of E
is 1. Determine the contents of AC, E, PC, AR, and IR in hexadecimal after the execution
of the CLA instruction. Repeat 11 more times, starting from each one of the registers
reference instructions. The initial value of PC is hexadecimal 021.
Q3. An instruction is stored at location 300 with its address field at location 301. The address field has
the value 400. A processor register R1 contains the number 200. Evaluate the effective address if the
addressing mode of the instruction is (a) direct; (b) immediate; (c) relative; (d) register indirect; (e)
index with R1 as the index register.
Q4. An 8-bit computer has a 16-bit address bus. The first 15 lines of the address are used to select a bank
of 32K bytes of memory. The high-order bit of the address is used to select a register which receives
the contents of the data bus. Explain how this configuration can be used to extend the memory
capacity of the system to eight banks of 32K bytes each, for a total of 256K bytes of memory.
Q5. Consider the multiplication of two 40 X 40 matrices using a vector processor.
a. How many product terms are there in each inner product, and how many
inner products must be evaluated?
b. How many multiply–add operations are needed to calculate the product matrix?

Section B: Attempt any two questions out of three. Each question carries 10 marks. [20 Marks]
Q6. (a) The 8-bit registers AR, BR, CR, and DR initially have the following values:
AR =1 1 1 10010
BR =1 1 1 1 1 1 1 1
CR =101 11001
DR =1 1 101010
 Determine the 8-bit values in each register after the execution of the following
sequence of microoperations.
AR AR + BR -- Add BR to AR
CR  CR AND DR, -- AND DR to CR
BR  BR + 1 -- Increment BR
AR AR – CR -- Subtract CR from AR
(b) Design a combinational circuit with three inputs x, y, z and three outputs A, B, C.
When the binary input is 0, 1, 2, or 3, the binary output is one greater than the input.
When the binary input is 4, 5, 6, or 7, the binary output is one less than the input.
Q7. (a) An instruction at address 021 in the basic computer has I=0, an operation code of the AND
instruction, and an address part equal to 083 (all numbers are in hexadecimal). The memory word at
address 083 contains the operand B8F2 and the content of AC is A937. Go over the instruction cycle
and determine the contents of the following registers at the end of the execute phase: PC, AR, DR, AC,
and IR. Repeat the problem six more times starting with an operation code of another memory-
reference instruction.
(b) A relative mode branch type of instruction is stored in memory at an address equivalent
to decimal 750. The branch is made to an address equivalent to decimal 500.
a. What should be the value of the relative address field of the instruction (in
decimal)?
b. Determine the relative address value in binary using 12 bits. (Why must the
number be in 2’s complement?)
c. Determine the binary value in PC after the fetch phase and calculate the binary value of
500. Then show that the binary value in PC plus the relative address calculated in part (b)
is equal to the binary value of 500.
Q8. (a) Draw the logic diagram of all the cells of one word in an associative memory. Include
the standard read and write logic and the match logic.
(b) Draw the logic diagram of all cells along one vertical column (column j) in an
associative memory. Include a common output line for all bits in the same column.
(c) From the diagrams in (a) and (b) show that if output is connected to the read line
of the same word, then the matched word will be read out, provided that only one word
matches the masked argument.

Section C: Compulsory question. [16 Marks]

Q9.
a) Starting from an initial value of R=11011101, determine the sequence of binary
values in R after a logical shift-left, followed by a circular shift-right, followed by a logical
shift-right and a circular shift-left.
b) A computer uses a memory of 65,536 words with eight bits in each word. It has the
following registers: PC, AR, TR (16 bits each), and AC, DR, IR (eight bits each). A memory-
reference instruction consists of three words: an 8-bit operation- code (one word) and a 16-bit
address (in the next two words). All operands are eight bits. There is no indirect bit.
a. Draw a block diagram of the computer showing the memory and registers.
(Do not use a common bus).
b. Draw a diagram showing the placement in memory of a typical three-word
instruction and the corresponding 8-bit operand.
c. List the sequence of microoperations for fetching a memory reference
instruction and then placing the operand in DR. Start from timing signal T0.
c) Show the step-by-step multiplication process using Booth algorithm when the following binary
numbers are multiplied. Assume 5-bit registers that hold signed numbers. The multiplicand in
both cases is (+15).
a. (+15) X (+13)
b. (+15) X (+13)
d) From the standpoint of hardware structure and programming methodologies,
compare and contrast tightly linked versus loosely connected multiprocessors.
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