[Plot graphs clearly marking each and every critical/necessary points, slopes, time

constant etc. where required]

(Consider ideal opamps unless anything is mentioned)

Consider an inverting amplifier designed with opamp of gain -3 (Figure 1)

 Plot Vout VS Vin considering ideal opamp.

 Plot Vout VS time with Vin = unit step function.
 Plot Vout VS Vin considering ideal opamp except output voltage range limit (Explain
clearly what happens internally within the opamp at the two extremes of input )
 Interchange the +ve and –ve terminals of opamp and plot Vout VS Vin (consider
output voltage range limit)
 Vin = unit step function; Plot Vout VS time for different values of ‘C’ on the same
graph (Figure 2)
 Vin = unit step function; Plot Vout VS time for C1=C2 , C1 / (C1+C2)= ¼ , C1 / (C1+C2)= 1/3
on the same graph (Figure 3)
[I don’t remember the ratios accurately]

Next they went on dividing the resistances and putting a capacitor over it…
 Plot Vout VS time with Vin = unit step function (for both Figure 4a and 4b on the
same graph)
 For the Figure 4b can Vout at any instant be less than -3V, if so find that condition

(and with this question they started troubling me … facing the interview panel was a really difficult
task… my brain stopped working suddenly and thinking process got stagnant too…Well, ultimately I
was able to answer it but took few minutes; could have answered it much easily outside the interview
:p )

 Plot Vout VS time with Vin = unit step function for Figure 4b with different ratios of
C1/C2 : 1,2,10,100 (I took a pretty long time  )
 Find the equivalent resistance seen by capacitor C1
 Plot Vout VS time with Vin = unit step function (for both Figure 5a and 5b on the
same graph)
  Plot V1,V2,Vout VS time with Iin = unit step function
(they continued with making the circuit more and more complex- now dividing resistors in feedback path and
putting capacitor across it…screwed up)

DO REMEMBER these circuits are to be solved intuitively, no equations, absolutely NO!!

Finally they ended up with asking me solve a second order / third order circuit intuitively (I don’t remember the
circuit , I couldn’t solve it even , only drew waveforms approximately but they wanted slopes etc.)

I got thrashed many a times for not drawing the plots properly with time constants, slopes etc. :P

My second round of interview was comparatively easier – few questions from the written test and signal s and
systems.

Apart from these questions I was asked about my projects.

Ohhh I forgot to mention I was questioned about feedback through power supplies, how to reduce them, effect of
power supply variations on output node etc…