Electric Power Components and Systems

ISSN: 1532-5008 (Print) 1532-5016 (Online) Journal homepage: http://www.tandfonline.com/loi/uemp20

Direct Torque Control of Induction Motor with

Common-Mode Voltage Elimination

Yogesh N. Tatte & Mohan V. Aware

To cite this article: Yogesh N. Tatte & Mohan V. Aware (2016) Direct Torque Control of
Induction Motor with Common-Mode Voltage Elimination, Electric Power Components and
Systems, 44:20, 2310-2324, DOI: 10.1080/15325008.2016.1220998

To link to this article: http://dx.doi.org/10.1080/15325008.2016.1220998

Published online: 28 Nov 2016.

Submit your article to this journal

View related articles

View Crossmark data

Full Terms & Conditions of access and use can be found at

http://www.tandfonline.com/action/journalInformation?journalCode=uemp20

Download by: [ Visvesvaraya National Institute of Technology] Date: 28 November 2016, At: 19:57
Electric Power Components and Systems, 44(20):2310–2324, 2016
Copyright C Taylor & Francis Group, LLC

ISSN: 1532-5008 print / 1532-5016 online

DOI: 10.1080/15325008.2016.1220998

Direct Torque Control of Induction Motor with

Common-Mode Voltage Elimination
Yogesh N. Tatte and Mohan V. Aware
Electrical and Electronics Department, Visvesvaraya National Institute of Technology, Nagpur, India

CONTENTS
Abstract—If the common-mode voltage in the induction motor drive
1. Introduction is not eliminated, it may cause failure of motor bearings and mal-
2. CMV in DTC of Induction Motor Drive functioning of the electrical equipment associated with the drive.
This article proposes the modified direct torque control technique to
3. DTC with CMV Elimination control the induction motor fed by three-level inverter, commonly
4. DC-Link Capacitors Voltage Balancing in DTC-I and DTC-II called a neutral-point-clamped inverter. The selective voltage vectors
5. Simulation Results in three-level inverter determine elimination of the common-mode
voltage. The classic three-level direct torque control based on selec-
6. Experimental Results and Discussion
tion of 6-full, 6-half, and 2-zero voltage vectors out of available 27 is
7. Conclusion modified so that the 6-intermediate voltage vectors and a zero voltage
References vector are employed. A comparative investigation with another three-
Biographies level direct torque control method which reduces both common-mode
voltage and torque ripple is also carried out. These methods are com-
pared with classic two-level direct torque control method in context of
common-mode voltage, torque ripple, current total harmonic distor-
tion (THD) and DC-link utilization. The simulation and experimental
results validate the proposed common-mode voltage elimination and
common-mode voltage reduction direct torque control techniques.

Keywords: NPC-inverter, three-level DTC, CMV elimination, CMV
reduction, torque ripple, DC-link utilization
Received 29 May 2015; accepted 23 July 2016
Address correspondence to Yogesh N. Tatte, Electrical and Electronics
Department, Visvesvaraya National Institute of Technology, South Ambazari
Road, Nagpur, Maharashtra, 440010, India. E-mail: ytatte@gmail.com
Color versions of one or more of the figures in the article can be found online
at www.tandfonline.com/uemp.
1. INTRODUCTION
The direct torque control (DTC) technique is introduced in
1986 by Takahashi and Noguchi for three phase induction
motor [1]. After its introduction, numerous researches are pre-
sented which propose new modifications in DTC to solve its
limitations such as torque ripple, variable switching frequency,
common-mode emissions, and demagnetization during low
speed operation [2–6].
In pulse-width modulation (PWM) controlled induction
motor drives, the CMV is generated. When induction mo-
tor is controlled by DTC technique, the inverter is operated
with several kHz of switching frequency. In high switching
frequency drives, CMV is a surely occurring phenomenon.
The CMV results in common-mode currents (CMC) which
through parasitic capacitance between the different parts of
the induction motor drives and the ground flows to the ground.
This may cause motor bearing failure, unexpected operation
of ground current protection relays, and electromagnetic in-
terference (EMI) noise that may lead to tripping of complete
induction motor drives. To overcome this problem, several

2310
 Tatte and Aware: Direct Torque Control of Induction Motor with Common-Mode Voltage Elimination 2311

of induction motor fed by three-level inverter, some modifica-

tions in the classic structure of DTC are presented [17, 18].
Various topologies are presented in the three-level inverter
(NPC) by some researchers to eliminate or to reduce the CMV
[8, 27, 28]. In [8], a solution of three-level inverter is pre-
sented to eliminate the CMV without considering the dc-link
capacitor voltages balancing, wherein only those switching
states are employed which generate zero common-mode volt-
age (ZCM). In [27], among available 27 voltage vectors in the
NPC inverter, 19 voltage vectors are employed which generate
the CMV of magnitude less than or equal to one-sixth of DC-
FIGURE 1. Path of common-mode voltage in NPC inverter- bus voltage while balancing the DC-link capacitor voltages. In
fed induction motor. [28], the four-pole topology in the NPC inverter-fed induction
motor drive is proposed to reduce the CMV while balancing the
solutions have been proposed for two-level inverter [7–10]. DC-link capacitor voltages. In the last decade, several topolo-
The CMC is reduced by holding the common-mode voltage gies are presented for the open-end winding induction motor
(CMV) constant. This is achieved by using either odd switch- fed by dual two-level inverter [20, 29, 30], dual three-level
ing states or even switching states [7]. The hardware solutions inverter [20, 21], dual five-level inverter [22, 23], and dual
such as the four phase inverter topology and the output filter seven-level inverter [24] in order to eliminate the CMV. These
effectively reduce the CMV [9, 10]. topologies require two inverters for CMV elimination. In [31],
Neutral-point-clamped (NPC) or diode-clamped inverter three-phase induction motor fed by single inverter which is
has found wide applications in medium-voltage high power called as three-level flying capacitor inverter cascaded to the
drives and due to reduction in switch and machine stresses, H-bridge is presented in order to eliminate the CMV contrast
these inverters also have recently shown its potential in lower to dual-inverter fed open-end winding configuration.
voltage drive applications [11–15]. Due to availability of 27 The CMV elimination or reduction techniques are presented
voltage vectors in three-level inverters (NPC inverters) com- for the open-loop control of the induction motor drive [7–10,
pared to eight in two-level inverters, three-level inverters have
shown their ability to improve the low speed region demagne-
tization effect [6] and to reduce the torque ripple of the motor
[16], when used to feed the DTC-controlled induction motor
drives. This three-level DTC system has provided additional
controllability over the stator flux and the torque of the mo-
tor compared to its two-level counterparts. Among 27 voltage
vectors, some voltage vectors (6-intermediate vectors and a
zero vector) are available in three-level inverter which can be
used to eliminate the CMV, while providing the controllability
over the stator flux and the torque. By using only those voltage
vectors which eliminate the CMV and at the same time control
the torque ripple, the induction motor can be controlled by the
novel DTC technique.
The DC-link capacitors voltage balancing is the major con-
cern in the multilevel inverter fed induction motor drive. If the
DC-link capacitors voltage is not balanced, voltage stress on
the power switches increases. Due to this the vulnerability of
the power switches increases [17–19]. In most of the researches
which have been presented for CMV reduction or elimination
either in multi-level inverter fed induction motor drive or in
dual multi-level inverter fed open-end winding induction mo-
tor drive, the DC-link capacitors voltage balancing is achieved
[20–26]. For balancing the DC-link capacitors voltage in DTC FIGURE 2. Available switching states of three-level inverter.
2312 Electric Power Components and Systems, Vol. 44 (2016), No. 20

FIGURE 3. Selection of voltage vectors: (a) for CMV elimination (DTC-I), (b) for both CMV and torque ripple minimization (DTC-II),
and (c) two-level DTC.

20–28, 29–35]. The CMV status in DTC controlled induc- itors balancing in DTC-I and DTC-II. Section 5 details about
tion motor fed by two-level inverter is presented in [5], where the proposed control schemes. Simulation and experimental
common-mode emissions have been minimized by using ei- results are provided in sections 6 and 7, respectively. The
ther only odd voltage vectors or only even voltage vectors and final section deals with the conclusions from the presented
without using zero voltage vectors at the expense of increase work.
in torque ripple. Recently, the CMV suppression is achieved in
the fault tolerant three-phase induction motor fed by two-level
inverter by adding fourth leg [36]. In [37], the DTC strategy 2. CMV IN DTC OF INDUCTION MOTOR DRIVE
for reducing the CMV in induction motor fed by three-level The CMV is generated in the induction motor drives, when it
inverter is presented, wherein 19 voltage vectors are employed is fed by PWM inverter. The two-level or three-level inverters
out of available 27. These closed-loop control techniques [5, are used to feed the low and intermediate voltage induction
36, 37] are able to reduce the CMV. The CMV elimination in motor. The CMV (u cm ) in the star connected induction motor
DTC of induction motor drive has not yet been investigated. is given as:
This article proposes the modified DTC method called as
u sa + u sb + u sc
DTC-I for the induction motor capable of eliminating the CMV u cm = (1)
while maintaining the torque ripple equals to what is obtained 3
in classical two-level DTC scheme. This technique utilizes 6-
intermediate voltage vectors and a zero voltage vector out of
available 27 to design the control strategy. This is compared
with another proposed three-level DTC method called as DTC-
II which utilizes 6-full, 6-half, and a zero voltage vector. The
DTC-II reduces both the CMV and the torque ripple. Both
DTC-I and DTC-II are compared with classic two-level DTC
in order to check their capabilities of eliminating or reducing
the CMV. For DC-link capacitors voltage balancing in DTC-I
and DTC-II, the size of the capacitors are kept as 4700 μF. In
addition to this, both the types of half voltage vectors are em-
ployed alternately in DTC-II for balancing the DC-link capaci-
tors voltage. Simulation and experimental results are provided
to verify the proposed DTC control schemes.
This article is organized as follows. Section 2 discusses the
CMV in DTC controlled induction motor drive. Section 3 fo-
cuses on the methods of CMV elimination and reduction in
induction motor drive which is controlled by DTC technique FIGURE 4. Torque ripple pattern of two-level DTC, DTC-I,
fed by three-level inverter. Section 4 states the DC-link capac- and DTC-II.
 Tatte and Aware: Direct Torque Control of Induction Motor with Common-Mode Voltage Elimination
FIGURE 5. Representation of different hysteresis controllers:
(a) 3-level torque controller, (b) 5-level torque controller, and
(c) 2-level flux controller.
where usa , usb , and usc are the inverter output phase voltages
with respect to midpoint of the DC-link. Figure 1 shows the
path of the CMV in the NPC inverter-fed induction motor.
In the fraternity of adjustable speed drives (ASD), the DTC
technique has proved its novelty in controlling induction mo-
tor [1]. However, this classic DTC has some drawbacks. So,
there are modifications suggested to overcome the problem of
torque ripple, variable switching frequency, and demagneti-
zation during low speed operation [2–4, 6, 16]. In classic or
modified DTC techniques, one concept is very cleared that the
voltage vector must be selected in order to meet the torque,
speed, and flux requirement. The voltage vector selection ini-
tiates switching action in inverter. The switching frequency
of variable switching frequency classic switching table DTC
(ST-DTC), constant switching frequency space vector mod-
ulation DTC (SVM-DTC), torque ripple minimization DTC,
and low speed operation improvement DTC are in the range
of several kHz. Thus, CMV is generated in induction mo-
tor drive either fed by two-level inverter or three-level in-
verter and may be controlled by classic or modified DTC
techniques.
The high switching frequency operation in DTC induction
motor drive is responsible for high dv/dt voltage transition.
This leads to large current through the parasitic capacitance be-
tween different parts of the drive. This leakage current causes
motor bearing failure, unnecessary tripping of protection re-
lays, EMI, etc. Due to these drawbacks, the induction motor
drive may lose its reliability whether it is controlled by clas-
sic or modified DTC. Therefore, while designing the DTC
strategy for the induction motor, the effect of CMV should be
considered.
3. DTC WITH CMV ELIMINATION
The voltage vectors in two-level inverter cannot be used to
design the DTC technique for the induction motor in order to
eliminate the CMV effect because of unavailability of ZCM
2313
switching states; however, the hardware solutions, such as pas-
sive filters and four leg topology in two-level inverter, may di-
minish the CMV effect in DTC induction motor drive. These
hardware solutions may increase the overall cost of the drive.
In a two-level inverter, the output of each phase is either +Vdc
/ 2 or –Vdc / 2, where Vdc is the DC-bus voltage. Therefore,
it is clear from Eq. (1) that the CMV generated by two-level
inverters has four magnitudes, i.e., +Vdc / 6, –Vdc / 6, +Vdc
/ 2, and –Vdc / 2. For example, a non-zero voltage vector of
switching state (+ – –) gives the output voltages of usa = +Vdc
/ 2, usb = –Vdc / 2 and usc = –Vdc / 2. Therefore, from Eq. (1),
the CMV for this switching state is –Vdc / 6. The zero voltage
vector of switching state (+ + +) gives the output voltages of
usa = +Vdc / 2, usb = +Vdc / 2 and usc = +Vdc / 2. Therefore,
from Eq. (1), the CMV for this switching state is Vdc / 2. For
example, if Vdc is 400 V, the switching state (+ – –) generated
the CMV of magnitude –Vdc / 6, i.e., –66.67 V. It is cleared
that ZCM is not possible in case of two-level inverter-fed DTC
induction motor drive.
There are four groups of voltage vectors exist in three-level
inverter, i.e., full (V 1 – V 6 ), half (V 7 – V 12 ), intermediate (V 13
– V 18 ) and zero voltage vectors (V 0 , V 19 , V 20 ). The full and
intermediate voltage vectors have one switching state, whereas
half voltage vectors have two switching states (“+” type and
“–” type). Among these 27 voltage vectors, 6-intermediate
(V 13 – V 18 ) and a zero voltage vector (V 0 ) have been selected
to design the DTC strategy called as DTC-I for the elimination
of the CMV. These voltage vectors are located in between the
full voltage vectors and are shown by small circle in Figure 2.
In three-level inverter, the output of each phase has three lev-
els +Vdc / 2 (upper two switches are “ON”), 0 (middle two
switches are “ON”), and –Vdc / 2 (lower two switches are
“ON”). Therefore, it is cleared from Eq. (1) that the CMV
generated by three-level inverter has 7 levels, i.e., ±Vdc / 6,
±Vdc / 3, ±Vdc / 2, and 0. For example “+” type half volt-
age vector V 11 (0 0 +) gives the output voltages of usa = 0,
usb = 0 and usc = +Vdc / 2, whereas “–” type half voltage
vector V 11 (– – 0) gives the output voltages of usa = –Vdc / 2,
FIGURE 6. Effect of different voltage vectors on capacitors
voltage: (a) full voltage vector (+ – –), (b) “+” half voltage
vector (+ 0 0), (c) “–“ half voltage vector (0 – –), (d) inter-
mediate voltage vector (+ 0 –), and (e) zero voltage vector
(0 0 0).
2314 Electric Power Components and Systems, Vol. 44 (2016), No. 20

FIGURE 7. Simulation results of: (a) capacitors voltage of DTC-I, and (b) capacitors voltage of DTC-II.

usb = –Vdc / 2 and usc = 0. Therefore, from Eq. (1) the CMV for zero voltage vector are able to generate the ZCM in the induc-
“+” type V 11 (0 0 +) half voltage vector and “–” type V 11 (– – tion motor drive. Now it is clear that the obvious choice of the
0) half voltage vector are +Vdc / 6 and –Vdc / 3, respectively. voltage vectors for designing the DTC-I scheme are of only
The 6-half voltage vectors each having two switching states the intermediate voltage vectors and a zero voltage vector in
can generate four different levels of CMV, i.e., ±Vdc / 6 and order to eliminate the CMV. To design the control strategy, the
±Vdc / 3. The full voltage vector V1 (+ – –) gives the output intermediate voltage vectors are divided into six sectors. The
voltages of usa = +Vdc / 2, usb = –Vdc / 2 and usc = –Vdc / first sector occupies its space in the plane from 0 to 60◦ as
2. Therefore, from Eq. (1) the CMV for this switching state is shown in Figure 2.
–Vdc / 6. The 6-full voltage vectors having one switching state The stator flux (λs ) of the motor can be written as:
can generate the CMV of magnitude ±Vdc / 6. It is cleared that 
both full and half voltage vectors are unable to eliminate the λs = (Vs − i s rs )dt (2)
CMV; however, they can reduce the magnitude of the CMV
dλs = Vs Ts (3)
from ±Vdc / 2 in two-level to ±Vdc / 6. In addition to these full
and half voltage vectors which can generate the CMV of mag- Since the stator resistance rs is very small, the voltage drop
nitudes ±Vdc / 6, a zero voltage vector of switching state (0 0 is rs across the stator can be neglected for medium and rated
0) which can eliminate the CMV effect also used to design the speed operation of the motor. Thus, the stator flux directly
DTC strategy. Therefore the 6-full (V 1 – V 6 ) having switching depends on the space voltage vector Vs and the sampling period
states (+ – –, + + –, – + –, – + +, – – +, + – +), 6-half (V 7 Ts . The electromagnetic torque can be expressed as:
– V 12 ) having both “+” and “–” types of switching states (+ 3 Lm
Te = P Im[λs · λr∗ ] (4)
0 0, 0 0 –, 0 + 0, – 0 0, 0 0 +, 0 – 0) and a zero (V 0 ) having 2 σ Ls Lr
switching state (0 0 0) are used to design the DTC strategy where P is the number of pole pairs, λr is the rotor flux
called as DTC-II which reduces the CMV from ±Vdc / 2 in and “∗ ” denotes the complex conjugate, leakage coefficient
two-level to ±Vdc / 6. The switching states of these voltage
vectors are shown in Figure 2 by small squares.
If the switching states of intermediate voltage vectors are
used to construct the DTC technique, it is possible to produce
the ZCM in the drive. In addition to intermediate voltage vec-
tors, a zero voltage vector is also employed which produces
ZCM and also helps in maintaining the torque ripple of the mo-
tor under control. The switching states of intermediate voltage
vectors and a zero voltage vector, respectively, are as follows:
V 13 (+ 0 –), V 14 (0 + –), V 15 (– + 0), V 16 (– 0 +), V 17 (0 –
+), V 18 (+ – 0), and V 0 (0 0 0). For example, the switching
state V 18 (+ – 0) gives the output voltages of usa = Vdc / 2, usb
= –Vdc / 2 and usc = 0 V. Therefore, from Eq. (1), the CMV
is zero. The zero voltage vector V 0 (0 0 0) gives the output
voltages of usa = 0, usb = 0, and usc = 0. This switching state
also generates the CMV of magnitude zero. Therefore, only FIGURE 8. Control scheme block diagram of DTC-I and
the switching states of the intermediate voltage vectors and a DTC-II schemes.
 Tatte and Aware: Direct Torque Control of Induction Motor with Common-Mode Voltage Elimination 2315

L2
(σ ) = 1 – L s mL r , Lm is the mutual inductance, Ls is the stator
inductance, and Lr is the rotor inductance.
The voltage vector is selected for increasing or decreasing
the flux (FI and FD) and the torque (TI and TD), meanwhile
producing the ZCM in DTC-I scheme. In this scheme, when
(a) the stator flux enters into the first sector, when an increase
of the torque (TI) and decrease of the flux (FD) are required
then voltage vector V 15 is the only voltage vector available in
the three-level inverter for the required condition which can
fulfill the torque and flux requirement and produces ZCM as
explained in this section as shown in Figure 3(a). For this
scheme three-level torque and two-level flux controllers are
required, since only intermediate and a zero voltage vectors
(b)
are employed.
Figure 3(b) shows the selection of voltage vectors for the
DTC-II scheme with both CMV and torque ripple minimiza-
tion. For this scheme the location of the sectors is started
from –30◦ , i.e., the first sector occupies its space in the plane
from –30◦ to +30◦ . For the same requirement of sector, torque
and the flux as in DTC-I, the voltage vector V3 is selected. In
Figure 3(b), the selection of only full voltage vectors are shown,
(c) half voltage vectors can also be selected depending upon the
requirement of incrementing and decrementing the torque and
the flux. For the same requirement of sector, torque and the
flux, by selecting full (V 3 ), half (V 9 ), and a zero (V 0 ) voltage
vector, not only the CMV but also the torque ripple can be
reduced. For this purpose, five-level torque and two-level flux
controllers are required.
A five-level torque comparator has five-levels for select-
(d)
ing five different voltage vectors. In order to select full, half
and zero voltage vectors, five-level torque comparator is re-
quired. Out of five-levels, outer two levels on both sides of
hysteresis controller are used for increasing the torque (dT =
2) and decreasing the torque (dT = –2) at fast rate for which
the full voltage vectors are selected, inner two levels on both
sides of hysteresis controller are used for increasing the torque
(e) (dT = 1) and decreasing the torque (dT = –1) at slow rate
for which the half voltage vectors are selected. When the esti-
mated torque matches with the reference torque, i.e., when the
torque error becomes zero (dT = 0), last level (center level) is
used for which the zero voltage vector is selected. The outer
bands (levels) guarantee the dynamic performance of the mo-
tor and the inner bands reduce the torque ripple. These levels
are decided based on the magnitudes of the voltage vectors.
(f) As the ratio of the length of full (0.667 Vdc ) to half (0.333
Vdc ) voltage vectors is 2, the ratio of outer to inner band on
FIGURE 9. Simulation results of two-level DTC, (a) CMV, both sides of hysteresis controller is kept as 2 [38, 39]. This
(b) torque, (c) rotor speed, (d) ‘a’ phase current, (e) stator flux five-level torque comparator is formed by dividing the positive
magnitude and (f) dc-link utilization.
and the negative torque hysteresis band in two equal halves, so
2316 Electric Power Components and Systems, Vol. 44 (2016), No. 20
FIGURE 10. Simulation results of DTC-I: (a) CMV, (b) torque, (c) rotor speed, (d) “a” phase current, (e) stator flux magnitude, and
(f) DC-link utilization.
that the two levels are obtained in positive hysteresis band and
two are obtained in negative hysteresis band. The working of
five-level torque comparator is explained through Eqs. (7–11)
and presented in Figs. 3(b), 4, and 5(b) [6, 16, 38, 39].
In the case of two-level inverter-fed DTC, for the same
required condition of torque (TI), flux (FD) and location of
stator flux (–30o to 30o), the voltage vector V 3 will be selected,
as shown in Figure 3(c). This voltage vector satisfied the re-
quired condition of torque and flux but is unable to eliminate
the CMV. In two-level DTC scheme, only 6-full and 2-zero
voltage vectors are available. Since only full and zero voltage
vectors are available, three-level torque controller and two-
level flux controller are enough to design the DTC strategy
[2].
Table 1 depicts the selection of suitable voltage vectors
for both DTC-I (three-level torque comparator) and DTC-II
(five-level torque comparator) schemes according to the out-
put from flux hysteresis controller (dλ), torque hysteresis con-
troller (dT), and the location of d-q stator flux (γ ). In DTC-I,
for example when the stator flux lies in first sector, if both
the torque and flux are required to increase (dT = 2 and dλ
= 1), the full voltage vector V 14 is selected which eliminates
the CMV, where dT = 2 represents the demand of increase
in torque at fast rate and dλ = 1 represents the demand of
increase in stator flux. In DTC-II, suppose the torque error
comes down to negative full hysteresis band (–HB), the re-
spective full (Vf ) voltage vector is selected to decrease the
actual developed torque. When the actual torque reaches the
half hysteresis band (HB/2), the voltage vector is changed to
respective half voltage vector (Vh ) as shown in Figure 4. For
example, when the stator flux lies in the second sector, if both
the torque and flux are required to decrease (dT = –2 and
dλ = 0), the full voltage vector V 6 is selected, whereas if
dT = –1 and dλ = 0, the half voltage vector V 12 is selected,
where dT = –2 represents the demand of decrease in torque at
fast rate, dT = –1 represents the decrement in torque at slow
rate and dλ = 0 represents the demand of decrease in stator
flux.
 Tatte and Aware: Direct Torque Control of Induction Motor with Common-Mode Voltage Elimination 2317

Figures 5(a–c), respectively, represent the three-level torque
controller, five-level torque controller and two-level flux con-
troller. From these representations, the operational conditions
of the torque and flux controllers can be formulated as follows:
λs < λ∗s dλ = 1
λ∗s < λs dλ= 0
Te∗ − Te (Teerr .) ≥ HB dT = 2
HB > Te∗ − Te ≥ HB/2 dT = 1
−(HB/2) < Te∗ − Te < HB/2 dT = 0
−(HB) < Te∗ − Te ≤ −(HB/2) dT = −1
Te∗ − Te ≤ −(HB) dT = −2
where HB represents the hysteresis band.
4. DC-LINK CAPACITORS VOLTAGE BALANCING
IN DTC-I AND DTC-II
In DTC-I, 6-intermediate and a zero voltage vector are em-
ployed, whereas in DTC-II, 6-full, 6-half, and a zero voltage
vector are used. All these voltage vectors have different ef-
fects on DC-link capacitors voltage of the NPC inverter. Since
there is no connection between the neutral point of the inverter
(Z) and output point, the 6-full voltage vectors have no ef-
fect on capacitors voltage. For example the full voltage vector
V 1 having switching state “+ – –” connects the “A” phase to
+ve DC-link terminal and “B,” “C” to –ve DC-link terminal.
Therefore, there is no connection between the neutral point
of the inverter (Z) and output point (phase point) as shown
in Figure 6(a). Both the “+” type and “–” type half voltage
vectors influence the neutral point voltage, but their effect on
the neutral point voltage differs. The “+” type half voltage
vectors increase the voltage VC2 and the “–” type half voltage
vectors decrease the voltage VC2 as shown in Figure 6(b) and
6(c), respectively. In case of the intermediate voltage vectors,
the neutral-point voltage deviation is uncertain as shown in
(5) Figure 6(d). The zero voltage vector V 0 having switching state
(6) “0 0 0” does not influence the neutral-point voltage as shown
in Figure 6(e) [17–19].
(7)
As the size of the DC-link capacitors increases, the neutral-
(8) point voltage deviation decreases [19]. Hence, the size of
(9) the DC-link capacitors for both the DTC schemes is kept as
4700 μF. Therefore, in DTC-I, the DC-link destabilization or
(10) unbalancing does not occur. Figure 7(a) shows the capacitors
(11) voltages in DTC-I. It can be seen from Figure 7(a) that the
DTC-I scheme does not have DC-link destabilization or un-
balancing problem.
In DTC-II strategy, the half voltage vectors are applied
after the application of full voltage vectors in order to re-
duce the torque ripple through five-level torque comparator
as shown in Figure 4 [16]. In section 3, it is cleared that
both the type of half voltage vectors are employed alter-
nately in order to reduce the CMV and balance the DC-link
capacitors voltage [17, 40]. The simulated Figure 7(b) vali-
dates the capacitors voltage balancing in the DTC-II control
strategy.
Figure 7(a) and 7(b) show the capacitor voltages of DTC-I
and DTC-II, respectively. The load transient of 10 Nm is ap-
plied at 0.7 s. Since the load is applied at 0.7 s, the neutral
current Iz drawn from the neutral point and, therefore, at 0.7 s,
the capacitor C2 starts discharging. Since the size of the ca-
pacitors are kept as 4700 μF in both the DTC schemes, and
by utilizing both the type of half voltage vectors alternately in
DTC-II, after some time (under 0.6 s) the deviation in neutral-

Sector

1 2 3 4 5 6

dλ dT DTC-I DTC-II DTC-I DTC-II DTC-I DTC-II DTC-I DTC-II DTC-I DTC-II DTC-I DTC-II
1 2 V14 V2 V15 V3 V16 V4 V17 V5 V18 V6 V13 V1
1 × V8 × V9 × V10 × V11 × V12 × V7
0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0
−1 × V12 × V7 × V8 × V9 × V10 × V11
-2 V18 V6 V13 V1 V14 V2 V15 V3 V16 V4 V17 V5
0 2 V15 V3 V16 V4 V17 V5 V18 V6 V13 V1 V14 V2
1 × V9 × V10 × V11 × V12 × V7 × V8
0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0
-1 × V11 × V12 × V7 × V8 × V9 × V10
-2 V17 V5 V18 V6 V13 V1 V14 V2 V15 V3 V16 V4

TABLE 1. Voltage vector table for DTC-I and DTC-II.

2318 Electric Power Components and Systems, Vol. 44 (2016), No. 20

point voltage stops in both the DTC schemes as shown in

Figure 7.
Figure 8 shows the block diagram of DTC-I and DTC-II
schemes. This system consists of outer speed loop, inner torque
loop, and outer flux loop. Whenever the reference speed com-
mand (ω∗ r ) is given, system compare it with the actual speed
(ωr ). The error passes through proportional and integral (PI)
(a) controller which gives the torque reference (T∗ e ) for the motor.
The estimated values of stator flux (λs ) and the electromag-
netic torque (Te ) are calculated by Eqs. (3) and (4), respectively.
The reference torque and the reference flux (λ∗ s ) are compared
with their actual values. Both comparators give respective er-
rors which then passes through the respective hysteresis con-
trollers. Hysteresis controllers for flux and the torque give the
(b)
digital outputs (dT and dλ). Depending upon the digital output
from hysteresis controllers and the stator flux vector position
(γ ), the voltage vector is selected. This control scheme block
diagram which is shown in Figure 8 is common for both the
DTC-I and DTC-II schemes. Table 1 combines the selection
of voltage vectors in both the schemes. The only difference in
the operating strategy between the two schemes is the different
torque comparator, a three-level torque comparator is imple-
(c)
mented in DTC-I scheme and a five-level torque comparator
is implemented in the DTC-II scheme. Therefore, according
to control strategy, the voltage vector from Table 1 will be
selected.

5. SIMULATION RESULTS
The operation of three phase induction motor controlled by
(d)
two-level DTC, DTC-I, and DTC-II is carried out through
MATLAB (The MathWorks, Natick, Massachusetts, USA)
simulation. The three-level DTC schemes DTC-I and DTC-
II are compared with two-level classic ST-DTC [2] in order to
check the CMV elimination capability of DTC-I scheme and
CMV reduction along with torque ripple reduction capability
of DTC-II scheme. In all three strategies, the outer speed-loop
(e)
gives the reference torque through PI controller. This controller
for speed-loop are set with Kp = 28 and Ki = 1. These values
are obtained by manual tuning. At 0.7 s, the step load torque
of 10 Nm (rated torque) is applied to the motor to check the
rigidity of the control scheme in loaded condition. Hysteresis
band of three-level torque and two-level flux comparators are
set with ±0.5% of the rated torque and ±1.43% of the rated
flux in both the two-level DTC and DTC-I schemes. In DTC-
(f) II, five-level torque controller and two-level flux controller are
used. The outer and inner levels on positive side of the five-
FIGURE 11. Simulation results of DTC-II, (a) CMV, (b)
torque, (c) rotor speed, (d) ‘a’ phase current, (e) stator flux level torque hysteresis controller are set with 0.5 and 0.25% of
magnitude and (f) dc-link utilization. the rated torque for which the full- and half-voltage vectors are
selected for increasing the torque. Similarly, the levels are set
 Tatte and Aware: Direct Torque Control of Induction Motor with Common-Mode Voltage Elimination
for negative side of the five-level torque hysteresis controller.
Since the ratio of length of full (0.667 Vdc ) to half (0.333 Vdc )
voltage vectors is two, the ratio of outer to inner band is kept
two, i.e., 0.5 to 0.25% of the rated torque on both sides of
the torque hysteresis controller [38, 39]. The same two-level
flux controller is used in DTC-II which is used in DTC-I. The
values for both the flux and torque comparators in all the pre-
sented schemes are set to achieve the trade-off between the
average switching frequency of the inverter, CMV transitions
and torque and flux ripple [35, 39, 41]. With these settings
of PI controller parameters, hysteresis bands and load torque,
the DTC-I, DTC-II, and two-level DTC are simulated with the
same parameters of the motor detailed in Table 2.
Figure 9 summarizes the simulation results for the classic
two-level DTC method. As explained in section 3, the CMV
generated by two-level inverter has four levels, i.e., +Vdc / 6,
–Vdc / 6, +Vdc / 2, and –Vdc / 2 as shown in Figure 9(a).
Figure 9(b) shows the waveform of estimated torque with
its ripple in the zoom portion. The reference rotor speed,
i.e., 1500 rpm to the control scheme is successfully achieved
as shown in Figure 9(c). Figure 9(d) shows the “a” phase
current pertaining to the torque transient of 10 Nm. The
rated stator flux of the motor of magnitude 0.42 Wb is
shown in Figure 9(e). The DC-link utilization of two-
level DTC is shown in Figure 9(f). Figure 10 summa-
rizes the simulation results for DTC-I method. In this
method, by utilizing intermediate and a zero voltage vec-
tor, the CMV has been eliminated as shown in Figure 10(a).
Figure 10(b) shows the estimated torque which has almost the
same ripple as in case of classic two-level DTC because of the
utilization of same three-level torque comparator. The rotor
speed is shown in Figure 10(c). Figure 10(d) shows the wave-
form of “a” phase current with respect to torque transient of 10
Nm. The stator flux of the motor and the DC-link utilization
are shown in Figure 10(e) and 10(f), respectively.
Figure 11 summarizes the simulation results for DTC-II
method. Figure 11(a) shows the CMV for DTC-II which is
minimized compared to classic two-level DTC. Figure 11(b)
shows the estimated torque with reduced ripple compared to
Parameter Value Parameter Value
Stator resistance(rs ) 0.14  DC-link voltage 400 V
Rotor resistance(rr ) 0.2  Rotor inertia(J ) 0.13 kgm2
Sampling frequency 8 kHz Average switching 1.8 kHz(DTC-I),
frequency 2.1 kHz(DTC-II)
TABLE 2. Parameters and data of drive
2319
FIGURE 12. Comparison of RMS values of CMV in two-level
DTC, three-level DTC-I, and three-level DTC-II (ref. speed =
1500 rpm).
classic two-level DTC and DTC-I. Figure 11(c–f) show the
rotor speed, “a” phase current pertaining to the torque tran-
sient, the stator flux of magnitude 0.42 Wb and the DC-link
utilization respectively. In DTC-I scheme, the DC-link utiliza-
tion is less compared to classic two-level DTC because of
selecting only intermediate and zero voltage vectors. In DTC-
II scheme the full, half- and zero-voltage vectors are almost
getting applied in equal proportions. So by utilizing the half
voltage vectors, the DC-link utilization in DTC-II scheme is
decreased compared to two-level DTC and DTC-I.
Figure 12 shows the comparison of RMS values of CMV
generated in all three cases with respect to reference speed
of 1500 rpm. It is shown that both the DTC-I and DTC-II
strategies have effectively eliminated and reduces the CMV,
respectively, compared to classical two-level DTC scheme.
6. EXPERIMENTAL RESULTS AND DISCUSSION
6.1. Experimental Setup
Figure 13 shows an experimental setup block diagram of
the proposed DTC schemes which consists of three phase
induction motor with load, digital signal processor (DSP), an
insulated gate bipolar transistor (IGBT) 3-level inverter, two
current sensors, a DC-bus voltage sensor, speed encoder,
driver-cum protection circuit, diode bridge rectifier, isolation
transformer with 1:2 turns ratio to get high DC-link voltage,
single phase autotransformer and DC-link capacitors each
Parameter Value Parameter Value
Stator leakage (Lls ) 1.1 mH Mutual 33.7 mH
inductance inductance(Lm )
Rotor leakage (Llr ) 1.1 mH Pole pair (P) 2
inductance
Machine rating 0.75 kW Rated torque 10 Nm
2320 Electric Power Components and Systems, Vol. 44 (2016), No. 20

(a)

FIGURE 13. An experimental setup of three-level three-phase

inverter fed three-phase induction motor for DTC-I and DTC-
II schemes.

of size 4700 μF. An inverter is fabricated by using SKM

50GB063D super-fast NPT-IGBT modules and FRED DSEI 2
× 30 as clamping diode. An experiment is conducted for both
the proposed DTC-I and DTC-II schemes in order to eliminate (b)
and to reduce the CMV, respectively, which is conducted
on symmetrical 0.75 kW cage-rotor induction motor. The
control scheme is based on TMS320F28027 DSP board.
This is 60 MHz fixed point DSP. While writing C-codes for
the proposed DTC strategies, three ADC channels (two for
current sensors and one for DC-bus voltage sensor) for signal
conditioning circuit, one enhanced pulse width modulator
(ePWM) for starting of conversion from analog to digital and
six general purpose input/output (GPIO) for generating high
or low gating signals for three legs (6-modules), are used. The
sampling frequency of control scheme is 8 kHz. The average
switching frequency in DTC-I scheme is 1.8kHz and 2.1kHz (c)
in DTC-II scheme.

6.2. Results and Discussion

Figure 14 summarizes the experimental results of DTC-I
scheme. The CMV in the induction motor drive has been elim-
inated by the DTC-I technique as shown in Figure 14(a). The
load transient of 10 Nm is suddenly applied with the help of a
DC machine at 0.7 s as shown in Figure 14(b). The rotor speed
is dropped as soon as the load is applied and after some time (d)
it is regained as shown in Figure 14(c). The well-regulated
FIGURE 14. Experimental results of DTC-I scheme: (a) CMV,
phase current waveform with respect to the torque transient
(b) estimated torque, (c) rotor speed, and (d) stator current.
is shown in Figure 14(d). Figure 15 summarizes the experi-
mental results of DTC-II scheme. The peak–peak magnitude
of CMV according to the application of voltage vectors in exhibits almost same performance as that of Figure 14(c). The
DTC-II scheme is ±Vdc / 6 which can be observed as almost phase current waveform with respect to the torque transient is
equals to 66.67 V as shown in Figure 15(a). Like in DTC-I shown in Figure 15(d). It is seen that both the proposed DTC
scheme; the load transient of 10 Nm is applied at 0.7 s as schemes tightly controlled the motor with the actual torque
shown in Figure 15(b). The rotor speed shown in Figure 15(c) follows the reference torque (load torque) which proves the
 Tatte and Aware: Direct Torque Control of Induction Motor with Common-Mode Voltage Elimination 2321

novelty of DTC method. Due to utilization of five-level torque

comparator, the torque ripple in DTC-II scheme is reduced
compared to torque ripple in DTC-I scheme.
Figure 16(a) shows the DC-link capacitors voltage during
the transient operation of the induction motor with DTC-I
scheme. It is seen that the DC-link capacitors voltage are al-
most balanced (5 V difference compared to 400 V DC-link).
When the load of 10 Nm is suddenly applied with the help of
a DC machine, each capacitor voltage is reduced by 6 V. It is
seen that even after application of the load, that the DC-link
capacitors voltage maintained balanced and almost stabilized
(a) (reduced by 12 V compared to 400 V DC-link). Figure 16(b)
shows the DC-link capacitors voltage during the transient op-
eration of the induction motor with DTC-II scheme. It is seen
that the DC-link capacitor voltages are almost balanced (7 V
difference compared to 400 V DC-link). It is observed that each
capacitor voltage is reduced by 14 V, when the load of 10 Nm
is suddenly applied. Therefore, in DTC-II scheme also, the
DC-link capacitors voltage maintained balanced and almost
stabilized (reduced by 28 V compared to 400 V DC-link). The
available 372 DC voltage in DTC-II scheme is enough to gen-
erate the rated flux in the air gap of the machine during full
load operation. So with the availability of this much DC volt-
(b) age during full load operation, the DTC-II scheme can work
with the intended performance as can be seen in Figure 15.
Table 3 shows the comparison in between two-level DTC,
DTC-I, and DTC-II schemes based on RMS value of CMV,
current THD, torque ripple, and DC-link utilization. The data
for comparison is obtained from simulations and experimental
results. It is observed that the DTC-I has eliminated the CMV
(RMS value = 0.25 V in simulation and 0.27 V in experiment)
and also has maintained the torque ripple equals to what is
obtained in 2-level scheme. The CMV elimination is achieved
(c)

Peak-peak
RMS load torque DC-link
value of ripple utilization
CMV (V; Current (ref. = 10 VLL (RMS) /
DTC schemes approx.) THD (%) Nm) Vdc (average)
2-L DTC 84.6 12.09 4 0.73
(simulation)
DTC-I 0.25 12.02 4 0.64
(simulation)
DTC-II 66 10.96 2.4 0.61
(d)
(simulation)
FIGURE 15. Experimental results of DTC-II scheme, (a) DTC-I 0.27 10.80 4 0.63
CMV, (b) estimated torque, (c) rotor speed, and (d) stator (experimental)
current. DTC-II 64 12.44 2.4 0.6
(experimental)

TABLE 3. Simulation and experimental data of the different schemes

2322 Electric Power Components and Systems, Vol. 44 (2016), No. 20
FIGURE 16. Experimental results of capacitor voltages during
transient operation (10 Nm), (a) DTC-I scheme, and (b) DTC-
II scheme.
in the DTC-I scheme at the expense of reduction in the DC-
link utilization compared to classic two-level DTC scheme.
The DTC-II scheme has reduced the RMS value of CMV from
84.6 V in two-level DTC to 66 V. So it is reduced by 21.99%. It
has also reduced the peak-peak torque ripple from 4 to 2.4 N-
m. So the torque ripple is reduced by 40% compared to 2-level
DTC and DTC-I. The CMV and the torque ripple are reduced
in the DTC-II scheme at the expense of reduction in the DC-
link utilization compared to two-level DTC and DTC-I. Table 3
reveals that the simulation results and experimental results for
both the proposed DTC schemes almost match with each other.
7. CONCLUSION
The DTC technique for induction motor fed by three-level in-
verter is proposed to eliminate the CMV. Two solutions (DTC-I
and II) are proposed to deal with CMV, out of which DTC-I
gives elimination of CMV with controlled torque ripple. An-
other one, i.e., DTC-II has reduced the CMV as well as the
torque ripple. Both the schemes are compared with the clas-
sic two-level scheme. It is concluded that only DTC-I can
eliminate the CMV from the induction motor drive without
increasing the torque ripple of the motor. Due to utilization
of seven voltage vectors and by dividing them in six sectors,
the computational burden on DSP for DTC-I remains same as
in case of classic 2-level DTC. The drawback of DTC-I and
DTC-II is the reduced DC-link utilization compared to classic
two-level DTC. The current THD in both the proposed DTC
schemes remains within the limit as it is validated through
experimental results.
REFERENCES
[1] Takahashi, I., and Noguchi, T., “A new quick response and high
efficiency control strategy of an induction motor,” IEEE Trans.
Ind. Appl., Vol. IA-22, No. 5, pp. 820–827, September/October
1986.
[2] Shyu, K.-K., Lin, J.-K., Pham, V. T., Yang, M.-J., and Wang,
T.-W., “Global minimum torque ripple design for direct torque
control of induction motor drivers,” IEEE Trans. Ind. Electron.
Vol. 57, No. 9, pp 3148–3155, September 2010.
[3] El-Kholy, E. E., Mahmoud, S., Kennez, R., El-Refaei, A., and
Elkady, F., “Torque ripple minimization for induction motor
drives with direct torque control,” J. Elec. Power Comp. Syst.,
Vol. 33, No. 8, pp. 845–859, August 2005.
[4] Habetler, T. G., Profumo, F., Pastorelli, M., and Tolbert, L.
M., “Direct torque control of induction machines using space
vector modulation,” IEEE Trans. Indust. Appl., Vol. 28, No. 5,
pp. 1045–1053, September/October 1992.
[5] Cirrincione, M., Pucci, M., Vitale, G., and Cirrincione, G.,
“A new direct torque control strategy for the minimization of
common-mode emissions,” IEEE Trans. Ind. Appl., Vol. 42, No.
2, pp. 504–517, March–April 2006.
[6] Lee, K.-B., Song, J.-H., Choy, I., and Yoo, J.-Y., “Improvement
of low-speed operation performance of DTC for three-level
inverter-fed induction motors,” IEEE Trans. Ind. Electr., Vol.
48, No. 5, pp. 1006–1014, October 2001.
[7] Cacciato, M., Consoli, A., Scarcella, G., and Testa, A., “Re-
duction of common-mode currents in PWM inverter motor
drives,” IEEE Trans. Ind. Appl., Vol. 35, No. 2, pp. 469–476,
March/April 1999.
[8] Zhang, H., Von Jouanne, A., Dai, S., Wallace, A. K., and
Wang, F., “Multilevel inverter modulation schemes to elimi-
nate common-mode voltages,” IEEE Trans. Ind. Appl., Vol. 36,
No. 6, pp. 1645–1653, November/December 2000.
[9] Julian, A. L., Oriti, G., and Lipo, T. A., “Elimination of
common-mode voltage in three-phase sinusoidal power con-
verters,” IEEE Trans. Power Electr., Vol. 14, No. 5, pp. 982–989,
September 1999.
[10] Ogasawara, S., Ayano, H., and Akagi, H., “Measurement and re-
duction of EMI radiated by a PWM inverter-fed AC motor drive
system,” IEEE Trans. Ind. Appl., Vol. 33, No. 4, pp. 1019–1026,
July/August 1997.
[11] Rodriguez, J., Bernet, S., Steimer, P. K., and Lizama, I. E., “A
survey on neutral-point-clamped inverters,” IEEE Trans. Ind.
Electr., Vol. 57, No. 7, pp. 2219–2230, July 2010.
 Tatte and Aware: Direct Torque Control of Induction Motor with Common-Mode Voltage Elimination
[12] Ewanchuk, J., Salmon, J., and Vafakhah, B., “A five-/nine-level
twelve-switch neutral-point-clamped inverter for high-speed
electric drives,” IEEE Trans. Ind. Appl., Vol. 47, No. 5, pp.
2145–2153, September-October 2011.
[13] Shen, J., and Butterworth, N., “Analysis and design of a three-
level PWM converter system for railway-traction applications,”
IEEE Proc.—Elect. Power Appl., Vol. 144, No. 5, pp. 357–371,
September 1997.
[14] Steinke, J. K., Vuolle, R., Prenner, H., and Jarvinen, J., “New
variable speed drive with proven motor friendly performance for
medium voltage motors,” Electric Machines and Drives, 1999.
International Conference IEMD’ 99, pp. 235–239, Seattle, WA,
9–12 1999.
[15] Behera, R. K., and Das, S. P., “Multilevel converter fed induction
motor drive for industrial and traction drive,” Potentials, IEEE,
Vol. 29, No. 5, pp. 28–32, September–October 2010.
[16] Lee, K.-B., Song, J.-H., Choy, I., and Yoo, J.-Y., “Torque rip-
ple reduction in DTC of induction motor driven by three-level
inverter with low switching frequency,” IEEE Trans. Power
Electr., Vol. 17, No. 2, pp. 255–264, March 2002.
[17] Alias, N. F., Jidin, A., Ismail, H., Firdaus, R. N., Khairi Rahim,
M., Razi, A., and Halim, W. A., “A simple potential bal-
ancing strategy for neutral-point-clamped inverter fed direct
torque control induction machines,” 2015 IEEE 11th Interna-
tional Conference on Power Electronics and Drive Systems, pp.
1002–1006, Sydney, NSW, 9–12 June 2015.
[18] Alloui, H., Berkani, A., and Rezine, H., “A three level NPC in-
verter with neutral point voltage balancing for induction motors
direct torque control,” 2010 XIX International Conference on
Electrical Machines (ICEM), pp. 1–6, 6–8 September, 2010.
[19] Sadeghi, A., Mohamadian, M., Shahparasti, M., and Fatemi,
A., “A new switching algorithm for voltage balancing of a
three-level NPC in DTC drive of a three-phase IM,” 2013
Twenty-Eighth Annual IEEE Applied Power Electronics Con-
ference and Exposition (APEC), pp. 489–495, 17–21 March,
2013.
[20] Edpuganti, A., and Rathore, A. K., “New optimal pulsewidth
modulation for single DC-link dual-inverter fed open-end stator
winding induction motor drive,” IEEE Trans. Power Electr., Vol.
30, No. 8, pp. 4386–4393, August 2015.
[21] Kanchan, R. S., Tekwani, P. N., and Gopakumar, K., “Three-
Level Inverter Scheme With Common Mode Voltage Elimina-
tion and DC Link Capacitor Voltage Balancing for an Open-End
Winding Induction Motor Drive,” IEEE Trans. Power Electr.,
Vol. 21, No. 6, pp. 1676–1683, November 2006.
[22] Tekwani, P. N., Kanchan, R. S., and Gopakumar, K., “A dual
five-level inverter-fed induction motor drive with common-
mode voltage elimination and DC-link capacitor voltage balanc-
ing using only the switching-state redundancy—Part I,” IEEE
Trans. Ind. Electr., Vol. 54, No. 5, pp. 2600–2608, October
2007.
[23] Tekwani, P. N., Kanchan, R. S., and Gopakumar, K., “A dual
five-level inverter-fed induction motor drive with common-
mode voltage elimination and DC-link capacitor voltage bal-
ancing using only the switching-state redundancy—Part II,”
IEEE Trans. Ind. Electr., Vol. 54, No. 5, pp. 2609–2617, Octo-
ber 2007.
[24] Mondal, G., Sivakumar, K., Ramchand, R., Gopakumar, K., and
Levi, E., “A dual seven-level inverter supply for an open-end
2323
winding induction motor drive,” IEEE Trans. Ind. Electr., Vol.
56, No. 5, pp. 1665–1673, May 2009.
[25] Yaramasu, V., Wu, B., Rivera, M., Narimani, M., Kouro, S., and
Rodriguez, J., “Generalised approach for predictive control with
common-mode voltage mitigation in multilevel diode-clamped
converters,” IET Power Electr., Vol. 8, No. 8, pp. 1440–1450,
August 2015.
[26] Renge, M. M., and Suryawanshi, H. M., “Three-dimensional
space-vector modulation to reduce common-mode voltage for
multilevel inverter,” IEEE Trans. Ind. Electr., Vol. 57, No. 7,
pp. 2324–2331, July 2010.
[27] Kim, H.-J., Lee, H.-D., and Sul, S.-K., “A new PWM strategy
for common-mode voltage reduction in neutral-point-clamped
inverter-fed AC motor drives,” IEEE Trans. Ind. Appl., Vol. 37,
No. 6, pp. 1840–1845, November/December 2001.
[28] Cuzner, R. M., Bendre, A. R., Faill, P. J., and Semenov, B., “Im-
plementation of a four-pole dead-time-compensated neutral-
point-clamped three-phase inverter with low common-mode
voltage output,” IEEE Trans. Ind. Appl., Vol. 45, No. 2, pp.
816–826, March–April 2009.
[29] Kalaiselvi, J., and Srinivas, S., “Bearing currents and shaft volt-
age reduction in dual-inverter-fed open-end winding induction
motor with reduced CMV PWM methods,” IEEE Trans. Ind.
Electr., Vol. 62, No. 1, pp. 144–152, January 2015.
[30] Baiju, M. R., Mohapatra, K. K., Kanchan, R. S., and Gopaku-
mar, K., “A dual two-level inverter scheme with common mode
voltage elimination for an induction motor drive,” IEEE Trans.
Power Electr., Vol. 19, No. 3, pp. 794–805, May 2004.
[31] Kumar, P. R., Rajeevan, P. P., Mathew, K., Gopakumar, K.,
Leon, J. I., and Franquelo, L. G., “A three-level common-mode
voltage eliminated inverter with single DC supply using flying
capacitor inverter and cascaded H-bridge,” IEEE Trans. Power
Electr., Vol. 29, No. 3, pp. 1402–1409, March 2014.
[32] Hava, A. M., and Ün, E., “A high-performance PWM algo-
rithm for common-mode voltage reduction in three-phase volt-
age source inverters,” IEEE Trans. Power Electr., Vol. 26, No.
7, pp. 1998–2008, July 2011.
[33] Payami, S., Behera, R. K., Iqbal, A., and Al-Ammari,
R., “Common-mode voltage and vibration mitigation of a
five-phase three-level NPC inverter-fed induction motor drive
system,” IEEE J. Emerging Select Topics Power Electr., Vol. 3,
No. 2, pp. 349–361, June 2015.
[34] Hoseini, S. K., Adabi, J., and Sheikholeslami, A., “Predic-
tive modulation schemes to reduce common-mode voltage in
three-phase inverters-fed AC drive systems,” IET Power Electr.,
Vol. 7, No. 4, pp. 840–849, April 2014.
[35] Chee, S. J., Ko, S., Kim, H. S., and Sul, S. K., “Common-
mode voltage reduction of three-level four-leg PWM con-
verter,” IEEE Trans. Ind. Appl., Vol. 51, No. 5, pp. 4006–4016,
September–October 2015.
[36] Garg, P., Essakiappan, S., Krishnamoorthy, H. S., and Enjeti,
P. N., “A fault-tolerant three-phase adjustable speed drive topol-
ogy with active common-mode voltage suppression,” IEEE
Trans. Power Electr., Vol. 30, No. 5, pp. 2828–2839, May 2015.
[37] Behera, R. K., Das, S. P., and Ojo, O., “Analysis and experimen-
tal investigation of CM voltage mitigation of a high performance
induction motor drive,” 2012 IEEE International Conference on
Power Electronics, Drives and Energy Systems (PEDES), pp.
1–6, Bengaluru, India, 16–19 December 2012.
2324 Electric Power Components and Systems, Vol. 44 (2016), No. 20
[38] Gao, L., Fletcher, J. E., and Zheng, L., “Low speed control
improvements for a 2-level 5-phase inverter-fed induction ma-
chine using classic direct torque control,” IEEE Trans. Ind.
Electr., Vol. 58, No. 7, pp. 2744–2754, July 2011.
[39] Ren, Y., and Zhu, Z. Q., “Reduction of Both Harmonic Current
and Torque Ripple for Dual Three-Phase Permanent-Magnet
Synchronous Machine Using Modified Switching-Table-Based
Direct Torque Control,” IEEE Trans. Ind. Electr., Vol. 62, No.
11, pp. 6671–6683, November 2015.
[40] du Toit Mouton, H., “Natural balancing of three-level neutral-
point-clamped PWM inverters,” IEEE Trans. Ind. Electr., Vol.
49, No. 5, pp. 1017–1025, October 2002.
[41] Casadei, D., Grandi, G., Serra, G., and Tani, A., “Effects of flux
and torque hysteresis band amplitude in direct torque control of
induction machines,” 20th International Conference on Indus-
trial Electronics, Control, and Instrumentation, 1994. IECON
‘94, Vol. 1, pp. 299–304, Bologna, Italy, 5–9 September 1994.
BIOGRAPHIES
Yogesh N. Tatte was born in India in 1988. He received
his B.E. in Electrical Engineering from Nagpur University,
Nagpur, India in 2010, and his M. Tech. from Raisoni Eng.
College, Nagpur, India in 2013. He is working toward his Ph.D.
at Visvesvaraya National Institute of Technology, Nagpur, In-
dia. His current research interests include power electron-
ics, drives, control and digital-signal-processing-based control
applications.
Mohan V. Aware received his B.E. in Electrical Engineering
from College of Engineering, Amravati, India, in 1980, his
M-Tech. from the Indian Institute of Technology, Bombay, in
1982, and his Ph.D. for his research work on “Direct Torque
Controlled Induction Motor Drives” from Nagpur University,
India, in 2002. From 1982 to 1989, he was a Design Officer
with Crompton Greaves Ltd., Nasik, India. From 1989–1991,
he was a Development Engineer with Nippon Denro Ispat Ltd.,
Nagpur. During 2001–2002, he was a Research Fellow with
Electrical Engineering Department, Hong Kong Polytechnic
University, Hong Kong. Currently, he is a Professor in Electri-
cal Engineering Department at Visvesvaraya National Institute
of Technology, Nagpur, India. He has published more than 100
technical articles in different journals and conferences. He is a
commonwealth academic Fellow. His main research areas are
electrical drives, distributed generation with energy storage,
and power electronics.