NRAM Defines a New Category of

“Memory Class Storage”

Bill Gervasi
Principal Systems Architect

11 April 2019
 2

NRAM
Technology
Value Test
Proposition Results
Agenda
Market Product
Position Designs
Future
Roadmaps
 3

When was the last time you read about a new volatile memory?

NRAM
MRAM PCM

3DXP ReRAM

The non-volatile memory revolution is under way

 The Value Proposition for NVRAM is Obvious 4

NVDIMM

Know DRAMs used for caches lose data on power fail

Your An energy store is needed to save data

Non-volatile memory eliminates this problem

Enemy

Batteries or SuperCaps?
NVMe
Step on glass or a LEGO?
Checkpointing Eats Energy & Performance 5

DRAM Non-Volatile Memory

Run Run

Checkpoint SSD/HDD Run

Run Run

Checkpoint SSD/HDD Run

Run Run

Checkpoint SSD/HDD Run

 6

Imagine…

A Non-Volatile

DDR Drop-In

Replacement…
……………..
……………..
……………..
 7

…Using
Carbon
Nanotubes
 8

With…  DRAM speed

 Non-volatility

 Unlimited write endurance

 Wide temperature range

 Scalable beyond DRAM

 Flexible fabrication & application

 Low power

 Low cost
Carbon Nanotubes (CNT) 9

Nanotubes are in full production today

Fundamental resistance is constant

Length and diameter can be selected

Mechanically, thermally, & electrically stable

CNT Nonvolatile Memory Cell 10

ELECTRODE

ELECTRODE

Van der Waals energy barrier keeps CNTs apart or together

Data retention >10 years (more like >1000 years)

Stochastic array of hundreds nanotubes per each cell

 CNT Mechanism Animation 11
TOP METAL

+
RESET:
Void F↑
stretches
above BE

SET: Void
Shrinks
above BE F

BOTTOM ELECTRODE
Resistance Measurements, 0 and 1 12

No calibration required across the wafer

MLC has been tested as well

 No Temperature Sensitivity in Timing 13

No change from -55 ֯C to +300 ֯C

5 ns read/write per cell

No write endurance limits seen in 1013 cycles

 Scalability 14

Key factor is the number of CNT junctions per bit (>100 needed)

Switching demonstrated from 180nm to 15nm

Modeling shows viability to 1 nm logic process

Flexible Fabrication & Application 15

Either…
Or Both

nR Crosspoint 1T-1R matrix

1T-1R matrix
nR Crosspoint 1T-1R matrix
1T-1R matrix
nR Crosspoint

nR Crosspoint
Function of
Design Efficiency

Crossover around
Logic/Memory process High Mb or low Gb
Substrate
 Transistors in the Array 16

More like traditional DRAM; better for small arrays

Plate

Drain Drain Drain

Wafer / Circuits

1T-1R NRAM in Memory Process

 Memory Crosspoint Structure 17

Cells constructed from resistive elements between lines

Self-selecting due to extremely low leakage

V1<0>

V2<0>

V1<1>

V2<1>

V1<2>

V2<2>

V1<3>

V2<3>

V1<4>

V2<4>

V1<5>

V2<5>

V1<6>

V2<6>

V1<7>

V2<7>
H1<0>
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
H2<0> 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2
V1
H1<1>
H2 H2<1>
0 1
3 2
0 1
3 2
0 1
3 2
0 1
3 2
0 1
3 2
0 1
3 2
0 1
3 2
0 1
3 2

V2
H1<2>
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
H2<2>
H1
3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2

V1 H1<3>
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
H2<3> 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2
Making a DRAM Replacement With CNT 18
X
Y NRAM LAYER

Drivers Receivers

Tune the array size to the size of drivers & receivers

Chip-level timing is a function of bit line flight times
Replicate this “tile” as needed for device capacity
Add I/O drivers to emulate any PHY needed
64 Kb tile
X
256 K tiles
=
16 Gb I/O PHY
Many I/O Types Possible 19

NRAM
Core
eRAM Custom
Technology

HBM GDDR

HMC LPDDR
DDR4/DDR5
DDR4 NRAM 20

A0:16
BG0:1 3DS
stackable
BA0:1
DDR4 NRAM
PAR
C0:2
16 Gb per die
CMD 128 Gb per stack
CK

DQ0:3 LDQS DQ4:7 UDQS

 DDR4 NRAM Overview 21

Carbon Nanotube Arrays

72 bits
Row Column Bank
Decode Decode Decode SECDED ECC Engine

Address 64 bits

FIFO FIFO
Chip ID Die Selector
x4/x8

Data Strobe Strobe Data

 Latching Sense Amps & Persistence Control 22

CNT Array

ACTIVATE Background
transfers data shadow buffers
from array to allow commits
sense amps Latching Sense Amp Shadow Buffer to NV array

READs and
WRITEs flow Vs DDR4,
through sense amps Slightly longer tRCD,
significantly shorter tAA
tPERSIST = 46.25 ns

ACT WRITE
tAA
External
Benefit: Fixed latency to
tRCD DATA Internal

CNT
data persistence
Loads LSA Updates LSA
Shadow copy
from CNT with ext data
 Timing Similar to DDR4E, Faster than DDR5 23

Parameter DDR4-2666-D 3DS NRAM4-2666 DDR5-4400C

tRC Activate to activate 47.00 46.25 50.18

tRCD RAS to CAS 15.0 23.0 18.18
tAA Read to data 17.14 13.5 18.18
tRP Precharge 15.0 14.25 18.18
tRAS Activate to precharge 32.0 32.0 32.0
tWR Write recovery 15.0 23.0 45.0
tFAW Four activate window limit 21.0 0 21.0
tRFC Refresh time 550 0 295
_L / _S Bank group to bank group _S Slower No penalty _S Slower
3DS Chip to chip in stack 2ck penalty No penalty 4ck penalty

Latency: smaller is better

 Bus Efficiency Comparison at Same Frequency 24

15-20%
DDR4/DDR5

NRAM

Base throughput

Elimination of refresh Architectural improvements

improve data throughput
Elimination of tFAW restrictions 15% or greater at the same
Elimination of bank group restrictions clock frequency

Elimination of power states

Elimination of inter-die delays

Bandwidth: larger is better

 DDR NRAM Scalability 512 Gb
7 nm logic
25
8 layers CNT
Add layers
~100 mm2
256 Gb
7 nm logic
128 Gb 4 layers CNT
14 nm logic
8 layers CNT DDR5
New process
Design Add layers
Done 64 Gb
14 nm logic
4 layers CNT DDR4
16 Gb New process
28 nm logic
4 layers CNT
Add layers
16-die stacks
8 Gb
28 nm logic 8-die stacks
2 layers CNT
 Next Generation Main Memory Issues 26

A quick peek at DDR5 protocol reveals a dirty little secret…

DDR5 bus is limited to 16H x 32Gb = 8H x 64Gb

NRAM likely to scale to at least 256Gb/die in DDR5 timeframe

We need to correct this restriction in JEDEC

Driving Adoption of Higher Densities 27

Nantero is chair of the JEDEC

Non-Volatile Memory Committee

Developing DDR5 NVRAM Specification

REXT ACTIVATE READ/WRITE

12 extended row bits enable up to 128Tb/die

Introducing “Memory Class Storage” 28

Hard Disk Storage Memory Class

SSD
Storage
Flash Storage Class > DRAM performance
NVMe Memory = DRAM endurance
Phase Change > DRAM capacity
3D Xpoint < DRAM price
Resistive RAM
Wasteland Magnetic RAM
3D NOR
Future
SCM
NRAM
DDR
DRAM
DDR
NRAM
 29
Carbon nanotubes
attract or repel
electrostatically
Memory cell
Batteries &
performance = 5ns
SuperCaps are the
with no wear-out
enemy to be
or temperature
defeated
issues
Summary
NRAM defines a Memory cells
new category: arranged in tiles
Memory Class can emulate any
Storage standard interface
Device capacity
roadmaps for
NRAM exceed
DRAM