Users Guide

TopSpice 8
For Windows XP/7/8/10
Mixed-Mode Circuit Simulator
User’s Guide
Revision 8.80
Copyright  2019 by Penzar Development

PO Box 900847, Palmdale, CA 93590 USA
www.penzar.com
Copyright © 1991-2019 by Penzar Development. All rights reserved.
No part of this publication may be copied or distributed, transmitted, transcribed, stored in a retrieval
system, or translated into any human or computer language, in any form or by any means, electronic,
mechanical, magnetic, optical, manual, or otherwise, or disclosed to third parties without the express
written permission of Penzar Development, PO Box 900847, Palmdale, CA 93590 U.S.A.
Printed in U.S.A.
TopSpice is a trademark of Penzar Development.
Microsoft and Windows are registered trademarks or trademarks of Microsoft Corporation. PSpice is a
registered trademark of Cadence Design Systems, Inc. HSPICE is a registered trademark of Synopsys
Inc. LTspice is a registered trademark of Linear Technology Inc. Other brand and product names are
trademarks or registered trademarks of their respective holders.
CONTENTS
Contents
1 GETTING STARTED .......................................................................................................................... 1-1

1.1 Introduction .................................................................................................................................. 1-1
1.1.1 Schematic Capture ............................................................................................................... 1-1
1.1.2 Circuit File Editor .................................................................................................................. 1-1
1.1.3 TopSpice Simulator .............................................................................................................. 1-2
1.1.4 TopView Graphical Post-Processor ..................................................................................... 1-3
1.1.5 Output File Browser ............................................................................................................. 1-3
1.1.6 Model Libraries and Database ............................................................................................. 1-3
1.2 Native Mixed-Mode Simulation .................................................................................................... 1-4
1.3 Analog Behavioral Modeling ........................................................................................................ 1-4
1.4 Installation ................................................................................................................................... 1-5
1.4.1 System Requirements .......................................................................................................... 1-5
1.4.2 Installation Procedure .......................................................................................................... 1-5
1.4.3 Upgrade Installation ............................................................................................................. 1-6
1.4.4 Uninstalling TopSpice .......................................................................................................... 1-6
1.5 Configuration File Setup .............................................................................................................. 1-7
1.5.1 [TopSpice] Section ............................................................................................................... 1-7
1.5.2 [Schematic] Section ............................................................................................................. 1-8
1.5.3 [Simulator] Section ............................................................................................................... 1-9
1.5.4 [TopView] Section ................................................................................................................ 1-9
1.5.5 [JobStatus] Section ............................................................................................................ 1-10
1.6 Documentation and Manuals ..................................................................................................... 1-11
1.7 Documentation Notation Conventions ....................................................................................... 1-11
1.8 Simulation Basics ...................................................................................................................... 1-12
2 USING TOPSPICE ............................................................................................................................. 2-1
2.1 User Interface .............................................................................................................................. 2-1
2.2 General Operation ....................................................................................................................... 2-1
2.3 Starting TopSpice ........................................................................................................................ 2-2
2.3.1 New Circuit ........................................................................................................................... 2-2
2.3.2 Open Last Project ................................................................................................................ 2-3
2.3.3 Open As Options .................................................................................................................. 2-3
2.3.4 Open Saved Schematic ....................................................................................................... 2-3
2.3.5 Open Saved SPICE (text) File ............................................................................................. 2-3
2.3.6 Apps ..................................................................................................................................... 2-3
2.3.7 Help ...................................................................................................................................... 2-3
2.4 Examples ..................................................................................................................................... 2-4
2.4.1 Running Example Schematics ............................................................................................. 2-4
2.4.2 Running Example SPICE Circuit Files ................................................................................. 2-5
2.5 TopSpice Files ............................................................................................................................. 2-5
2.6 General Syntax and Design Rules .............................................................................................. 2-6
2.6.1 Names .................................................................................................................................. 2-6
2.6.2 Node Names ........................................................................................................................ 2-6
2.6.3 Global Nodes........................................................................................................................ 2-6
2.6.4 Voltage and Current Variables ............................................................................................. 2-7
2.6.5 Number Formats .................................................................................................................. 2-7
2.6.6 Component and Model Parameter Values ........................................................................... 2-8
2.6.7 Circuit Topology Rules ......................................................................................................... 2-8
2.7 Creating Design Projects ............................................................................................................. 2-9
2.8 How to Create a Schematic ......................................................................................................... 2-9
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TopSpice User's Guide
2.8.1 Selecting Symbols .............................................................................................................. 2-10

2.8.2 Placing Parts ....................................................................................................................... 2-10
2.8.3 Specifying Part Attributes ................................................................................................... 2-10
2.8.4 Rotate, Mirror and Flip ........................................................................................................ 2-10
2.8.5 Wiring the Circuit ................................................................................................................ 2-10
2.8.6 Electrical Connections ........................................................................................................ 2-11
2.8.7 Node Labels and Numbers ................................................................................................. 2-11
2.9 Simulating Your Circuit .............................................................................................................. 2-12
2.10 Waveform Plotting and Analysis ............................................................................................ 2-12
2.10.1 Cursor Measurements ........................................................................................................ 2-12
2.10.2 Plot Axis Limits and Options ............................................................................................... 2-13
2.11 TopSpice Simulator ................................................................................................................ 2-13
2.11.1 Simulator Input File ............................................................................................................. 2-13
2.11.2 Simulator Output Files ........................................................................................................ 2-13
2.11.3 Simulator Command Line Operation .................................................................................. 2-13
2.11.4 Simulator Memory Usage ................................................................................................... 2-14
2.12 Simulator Engine Options ...................................................................................................... 2-14
2.12.1 XSPICE Option ................................................................................................................... 2-14
2.12.2 LTspice Simulator ............................................................................................................... 2-15
2.12.3 Other Simulator................................................................................................................... 2-15
2.13 TopSpice Circuit Netlist File ................................................................................................... 2-15
2.14 Tutorial Session...................................................................................................................... 2-17
2.14.1 Drawing the Circuit ............................................................................................................. 2-17
2.14.2 Adding Device Models ........................................................................................................ 2-19
2.14.3 Simulation Setup................................................................................................................. 2-19
2.14.4 Run Simulation ................................................................................................................... 2-20
3 INPUT/OUTPUT FILE EDITORS........................................................................................................ 3-1
3.1 Circuit Netlist File Editor............................................................................................................... 3-1
3.1.1 User Interface ....................................................................................................................... 3-2
3.1.2 Toolbar Functions ................................................................................................................. 3-5
3.1.3 Menu Commands ................................................................................................................. 3-5
3.1.4 Operation .............................................................................................................................. 3-9
3.1.5 Multiple Open Files ............................................................................................................... 3-9
3.1.6 Simulation ............................................................................................................................. 3-9
3.1.7 Syntax Highlighting ............................................................................................................... 3-9
3.1.8 Bookmarks .......................................................................................................................... 3-10
3.2 Output File Browser ................................................................................................................... 3-11
3.2.1 User Interface ..................................................................................................................... 3-11
3.2.2 Menu Commands ............................................................................................................... 3-13
3.2.3 Operation ............................................................................................................................ 3-15
3.2.4 E-mail Output File ............................................................................................................... 3-15
4 SPICE DEVICES AND MODELS ....................................................................................................... 4-1
4.1 Simulator Circuit Elements .......................................................................................................... 4-1
4.1.1 Passive Devices ................................................................................................................... 4-2
4.1.2 Independent Sources ........................................................................................................... 4-2
4.1.3 Signal Sources...................................................................................................................... 4-2
4.1.4 Dependent Sources .............................................................................................................. 4-2
4.1.5 Special Function Sources ..................................................................................................... 4-3
4.1.6 Analog Behavioral Modeling Sources................................................................................... 4-3
4.1.7 Semiconductor Devices ........................................................................................................ 4-3
4.1.8 Digital Devices ...................................................................................................................... 4-4
4.1.9 Analog/Digital Interfaces ....................................................................................................... 4-4
4.2 Device Models ............................................................................................................................. 4-5
4.2.1 TopSpice Built-in Models ...................................................................................................... 4-5
4.3 Subcircuits ................................................................................................................................... 4-6
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CONTENTS
4.4 Simulation Models ....................................................................................................................... 4-7

4.5 Model Libraries and Files ............................................................................................................ 4-9
4.5.1 SPICE Model Libraries ....................................................................................................... 4-10
4.5.2 Using Models as Schematic Parts ..................................................................................... 4-12
4.5.3 Importing Models ................................................................................................................ 4-14
4.6 TopSpice Model Libraries and Database .................................................................................. 4-15
4.6.1 Model Database Commands.............................................................................................. 4-16
4.6.2 Model Database Operation ................................................................................................ 4-17
4.6.3 TopSpice Model Libraries Search ...................................................................................... 4-18
4.6.4 .INC/MDB Command ......................................................................................................... 4-20
4.7 HSPICE Libraries ...................................................................................................................... 4-20
4.7.1 HSPICE Library File Definition ........................................................................................... 4-21
4.8 Include Files .............................................................................................................................. 4-22
4.9 Encrypted Model Files ............................................................................................................... 4-22
5 SIMULATION ..................................................................................................................................... 5-1
5.1 Introduction .................................................................................................................................. 5-1
5.1.1 TopSpice Simulator Commands .......................................................................................... 5-1
5.1.2 Simulation Setup .................................................................................................................. 5-2
5.2 DC Analysis ................................................................................................................................. 5-2
5.3 AC Small-Signal Analysis ............................................................................................................ 5-3
5.3.1 Noise Analysis ...................................................................................................................... 5-4
5.3.2 Distortion Analysis ................................................................................................................ 5-5
5.3.3 Open Loop Gain Measurement ............................................................................................ 5-5
5.4 Transient Analysis ....................................................................................................................... 5-6
5.4.1 Fourier Harmonic Analysis ................................................................................................... 5-6
5.4.2 Frequency Response Analysis............................................................................................. 5-7
5.5 Analysis at Different Temperatures ........................................................................................... 5-10
5.6 Analysis for Different Component Values ................................................................................. 5-11
5.6.1 Parametric Analysis ........................................................................................................... 5-12
5.6.2 Alter Circuit ......................................................................................................................... 5-14
5.6.3 Monte Carlo Analysis ......................................................................................................... 5-16
5.6.4 Worst Case Analysis .......................................................................................................... 5-18
5.7 Data Output and Post-Processing Commands ......................................................................... 5-19
5.8 Simulation Commands .............................................................................................................. 5-20
5.9 Simulation Setup Menu ............................................................................................................. 5-20
5.9.1 DC Bias Point Setup .......................................................................................................... 5-21
5.9.2 DC Sweep Setup ................................................................................................................ 5-21
5.9.3 Transient Analysis Setup ................................................................................................... 5-21
5.9.4 AC Sweep Setup ................................................................................................................ 5-22
5.9.5 Temperature Setup ............................................................................................................ 5-22
5.9.6 Parametric Step Setup ....................................................................................................... 5-22
5.9.7 Monte Carlo and Worst Case Setup .................................................................................. 5-23
5.9.8 .ALTER Setup .................................................................................................................... 5-23
5.9.9 Post-Processor Directives Setup ....................................................................................... 5-23
5.9.10 Save Data Setup ................................................................................................................ 5-24
5.9.11 Print Data Setup ................................................................................................................. 5-24
5.9.12 Auto Plot Setup .................................................................................................................. 5-24
5.10 SPICE Netlist and Circuit File ................................................................................................ 5-26
5.10.1 Map File.............................................................................................................................. 5-28
5.10.2 Netlisting Error Messages .................................................................................................. 5-28
5.11 Running Simulations .............................................................................................................. 5-28
5.11.1 Multiple/Parallel Simulations .............................................................................................. 5-29
5.11.2 Pause-Plot-Resume Simulation ......................................................................................... 5-29
5.12 Bias Voltages and Currents Display ...................................................................................... 5-29
5.13 Simulation Output Files .......................................................................................................... 5-30
5.14 Convergence.......................................................................................................................... 5-31
iii
5.14.1 DC Convergence ................................................................................................................ 5-32

5.14.2 Transient Convergence ...................................................................................................... 5-33
6 DIGITAL SIMULATION ...................................................................................................................... 6-1
6.1 Introduction .................................................................................................................................. 6-1
6.2 Digital Circuit Netlist ..................................................................................................................... 6-2
6.3 Logic States ................................................................................................................................. 6-3
6.4 Logic Simulation Time Step ......................................................................................................... 6-4
6.5 Logic Simulation Errors and Glitches ........................................................................................... 6-4
6.6 Digital Primitives .......................................................................................................................... 6-4
6.6.1 Digital Primitive Models ........................................................................................................ 6-6
6.6.2 Stimulus Generators ............................................................................................................. 6-7
6.6.3 Boolean Gates ...................................................................................................................... 6-7
6.6.4 Tri-State Gates ..................................................................................................................... 6-8
6.6.5 Delay Gate ............................................................................................................................ 6-8
6.6.6 Flip-flops ............................................................................................................................... 6-8
6.6.7 RAM Static Random-Access Memory .................................................................................. 6-9
6.6.8 ROM Read-Only Memory ..................................................................................................... 6-9
6.6.9 N-Bit Shift Registers ........................................................................................................... 6-10
6.6.10 N-Bit Counters .................................................................................................................... 6-11
6.6.11 Decoders, Encoders and Multiplexers ................................................................................ 6-12
6.6.12 Arithmetic Logic Units ......................................................................................................... 6-12
6.6.13 PULSE Pulse Generator and Multivibrator ......................................................................... 6-13
6.7 Digital Macro Models ................................................................................................................. 6-13
6.8 Analog/Digital Interface .............................................................................................................. 6-14
7 ANALOG BEHAVIORAL MODELING ............................................................................................... 7-1
7.1 Introduction .................................................................................................................................. 7-1
7.2 POLY Polynomial Source ............................................................................................................ 7-2
7.3 VALUE Source ............................................................................................................................. 7-4
7.4 TABLE Source ............................................................................................................................. 7-5
7.5 FREQ Source ............................................................................................................................... 7-6
7.5.1 S-Parameter Tables ............................................................................................................. 7-7
7.6 LAPLACE Source ........................................................................................................................ 7-8
7.6.1 Laplace Transform State Space Model .............................................................................. 7-10
7.7 RESISTOR Source .................................................................................................................... 7-11
7.8 ABM Expressions ....................................................................................................................... 7-11
7.8.1 Predefined Constants ......................................................................................................... 7-12
7.8.2 Circuit State Variables ........................................................................................................ 7-12
7.8.3 Math Functions ................................................................................................................... 7-13
7.8.4 User Defined Functions ...................................................................................................... 7-14
7.8.5 Logical Expressions ............................................................................................................ 7-15
7.8.6 Relational Expressions ....................................................................................................... 7-15
8 ABOUT SPICE .................................................................................................................................... 8-1
8.1 SPICE Program ........................................................................................................................... 8-1
8.2 SPICE Reference Books ............................................................................................................. 8-1
INDEX............................................................................................................................................................ 1
iv
INTRODUCTION
CHAPTER
1 GETTING STARTED
1.1 Introduction
TopSpice is a native full-featured mixed-mode, mixed-signal, circuit simulator capable of simulating
circuits containing any arbitrary combination of analog devices, digital functions and high-level behavioral
blocks. With TopSpice you can verify and optimize your design from the system to the transistor level. By
using the built-in logic simulator to simulate the digital sections of your circuit instead of analog
equivalents, mixed-mode simulation times can be reduced by orders of magnitude.
TopSpice offers a fully integrated environment to capture, simulate, and analyze your circuit designs. Its
flexible architecture allows the designer to integrate all the design tools, including third party tools and
model libraries, into a complete CAD system. TopSpice is also unique in that it offers you the choice to
design from schematic drawings, SPICE netlist (text) files or mix of schematic and netlist, or switch
between them. All design and simulation functions are available from either the schematic or netlist editor
front-ends.
The TopSpice software consists of the following integrated component programs: Schematic Editor,
Circuit File Editor, Simulator, Output File Browser, TopView post-processor, and extensive library of
device models with Model Libraries Database tool.
1.1.1 Schematic Capture

The TopSpice Schematic Editor front-end provides an easy way to create and edit circuit drawings, run
simulations, and plot and analyze the results. The Schematic Editor features:
• Multiple schematic pages (up to 100).

• Support for hierarchical designs.
• Powerful symbol attribute handling and custom user parts to encapsulate models.
• Auto-repeat, auto-junction, wire rubberbanding and auto-incrementing of part names.
• Auto symbol generator for user parts, hierarchical blocks, subcircuits and logic functions.
• Group, area and subcircuit edit operations.
• Bias voltage and current display on schematic drawing.
• Large library of over 400 symbols includes all SPICE elements and library parts, plus most common
analog and digital devices.
• Import model function automatically converts SPICE models and s-parameters data files to schematic
user parts.
• Menu commands integrate all the simulation setup, run and plot functions.
See the “Schematic Editor User’s Guide” manual for detailed information.
1.1.2 Circuit File Editor

The Circuit File Editor is the text editor front-end for TopSpice. It allows you to create, edit and simulate
SPICE netlists. It can also be used to edit command and model files, or any other text file. It operates
much like any other Windows text editor, but with added features that makes it convenient to perform all
the design functions:
1-1
• Color highlighting for SPICE syntax.

• Menu commands integrate all the simulation setup, run and plot functions.
• Model library database function.
• Toolbar “Go” button runs simulation with a single click.
• Unlimited file size (limited by available system resources).
• “Bookmarking” feature.
• Online syntax and command help.
See Chapter 3 for detailed information.
1.1.3 TopSpice Simulator

The TopSpice mixed-mode circuit simulator offering many advanced features:
• Native mixed-mode, mixed-signal simulation with built-in event-driven logic simulator.

• Industry standard SPICE simulator supports many PSpice ™ and HSPICE™ syntax enhancements,
and works with most vendor SPICE model libraries.
• Simulator supports large circuit sizes (up to available system resources).
• BSIM3 v3.2, BSIM4 v6 and EKV v2.6 submicron MOSFET models with HSPICE compatible ACM
and noise model support.
• "Curtice", "Statz" and Triquint GaAs FET models.
• VBIC bipolar transistor model.
• Jiles-Atherton nonlinear magnetic core model.
• Table look-up modeling of capacitors and inductors.
• Built-in advanced ferroelectric capacitor model.
• Lossy transmission line model.
• Analog behavioral modeling using arbitrary equations, logical expressions and look-up tables.
• Frequency domain modeling using Laplace transforms, frequency response tables and s-parameters.
• Built-in special analog functions such as op amps and comparators for fast simulation of SMPS
circuits.
• Macromodeling (subcircuits) with parameter passing.
• Automatic model library search.
• Support for HSPICE model library files and MOSFET model binning.
• HSPICE compatible behavioral resistor and capacitor options.
• User defined parameters, expressions and functions.
• Advanced convergence aid algorithms solve tough convergence problems.
• Monte Carlo and worst case analyses with device and lot tolerances.
• Parametric stepping of component, user defined parameter and tolerance values.
• Non-uniform device temperatures.
• Advanced noise analysis features with custom noise source options.
• Frequency response analysis in the time domain for nonlinear circuits.
• "ALTER" iteration command supports all devices, models and subcircuits.
• "Pause-plot-resume" simulation capability to view partial run results.
• Data output support for device currents, source impedances, magnetic flux and digital states.
• Binary file output option saves all voltages, device currents and digital node states.
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INTRODUCTION
See the “Simulator Reference” manual for detailed information.
1.1.4 TopView Graphical Post-Processor

TopView is the interactive graphical SPICE post-processor program to plot and analyze SPICE simulation
output data. Features:
• Smart auto-plotting.
• Multiple plot axes.
• Analog and digital waveforms on the same graph.
• Zooming and scrolling of plots.
• Cursor measurements.
• Waveform expression plots.
• Powerful waveform analysis functions.
• Statistical and performance measurements.
• FFT, Smith chart, polar chart, histogram and “eye display” plots.
• Complex-number expressions and plots.
• Support for importing and plotting CSDF, audio WAV, Touchstone, CSV and user data files.
• Many formatting options for creating custom graphs.
• Options to export graphs to other Windows applications.
• Script files to automate complex post-processing analysis and plotting.
• Publication quality printed output.
See the “TopView User’s Guide” manual for more detailed information.
1.1.5 Output File Browser

The TopSpice File Browser allows the user to browse the simulation output text file which contains
information on the circuit, devices, models, operating point, tabulated data, simulation statistics, error and
warning messages, etc. If there are simulation error messages, the File Browser automatically jumps to
and displays the first error message.
1.1.6 Model Libraries and Database

The TopSpice software package comes with an extensive set of model libraries with over 32,000 parts.
They include discrete devices (diodes, transistors, power semiconductors, etc.), analog functions,
optoelectronic devices, magnetic parts, SMPS models, digital logic families and vendor model libraries.
The Model Database tool allows convenient searching, browsing and extraction of models in the libraries.
The simulator also automatically searches the model database when a circuit uses undefined device
models and extracts the necessary model codes from the libraries.
TopSpice also supports standard SPICE library files, HSPICE™ format library files and model files. These
are available from component vendors, CAD vendors, IC foundries, other third parties, Internet, or they
can be user created.
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1.2 Native Mixed-Mode Simulation

TopSpice implements a fully integrated mixed-mode simulation technology. The analog electrical
simulation and the logic simulation algorithms are merged into one unified simulator architecture. The
logic simulator implemented in TopSpice is fully event-driven. The digital section of the circuit is only
evaluated when a logic event takes place during the simulation. TopSpice also implements a common
SPICE like input syntax for both analog and digital sections for getting those designers familiar with
SPICE rapidly on board.
TopSpice features many advanced analog/digital mixed-mode capabilities:
• True event-driven state-machine representation of logic circuits.

• Separate analog/digital time step control.
• No limitations in analog/digital connections.
• Nine-state logic simulation: 0, 1, X states plus low, T and Z impedance levels.
• User specified gate propagation delays.
• Glitch and race condition detection.
• Large flexible set of built-in digital primitives: Boolean gates, flip-flops, tri-state gates, delay gate,
ROM, RAM, counters, shift registers, decoders, encoders, multiplexers, adders, comparators,
multivibrators, parity generators/checkers, pulse generators, and clock and data generators.
• Analog-to-digital interface element and models with supply tracking logic threshold voltages, user
specified impedances and switching parameters.
• Library of standard TTL, CMOS and ECL series parts.
1.3 Analog Behavioral Modeling

The analog behavioral modeling capability allows the designer to describe electronic components and
circuit functional blocks using transfer functions. This "black box" approach is a very powerful tool for
modeling complex devices, speeding up simulation of large systems and developing a top-down design
methodology. Analog behavioral modeling also lets TopSpice users easily include arbitrary high-level
analog functions and model non-electrical components. The following options for specifying transfer
functions are available in TopSpice:
• User defined equations and parameters. Equations can be arbitrary functions of voltage, current, time
and temperature.
• Many built-in math functions and support for user defined functions.
• Look-up tables.
• Laplace transforms (arbitrary equations of complex variable s).
• Frequency response tables and s-parameter tables for high-frequency device modeling.
• Logical and relational expressions.
TopSpice supports both AC and transient analyses for Laplace transforms, frequency response tables
and s-parameter tables. This capability allows convenient linear modeling of high frequency devices and
networks.
1-4
INTRODUCTION
1.4 Installation
TopSpice is distributed either as an ESD (electronic software download) or CD packaged product. The
CD distribution package you received should contain the following:
• Software CD with serial number.

• Registration form with serial number.
For either distribution, the product serial number is required to install the software. The following sections
describe the software installation requirements and procedures.
After the installation is completed, please take a moment to register the product. You may register using
the Help|User Registration menu command options or one of the user registration buttons in the
TopSpice launch Help window. Registration is required to obtain technical support and to download online
service updates from our Web site. This will also ensure that you are informed of product updates, special
offers to registered users, and other important information. Note: one registered user per license allowed.
We also recommend that you browse through the Readme file which contains important, up-to-date
information concerning this product. You have the option to read this file at the end of the installation
process, or afterwards by clicking on the Readme button in the TopSpice launch Help window.
1.4.1 System Requirements

To install TopSpice, your PC system must have the following minimum hardware and software configu-
ration:
• Windows XP, Vista, 7, 8 or 10 operating system (32 or 64 bits).

• Pentium compatible or better CPU.
• 1 GB RAM.
• 500MB hard disk drive free space.
• Display with minimum 1000x800 screen resolution.
• Built-in CD-ROM drive if installing from the CD product. A network CD drive cannot be used.
1.4.2 Installation Procedure

To install the software properly, you must run the installation setup program. For the ESD (download)
distribution, use the following procedure:
1. Run or open from Windows Explorer the downloaded installation executable file.
2. Enter the installation password when prompted. The password is listed on the product download and
installation instructions you received with your order.
3. Follow the screen prompts.
For the CD distribution, use the following procedure:
1. Insert CD in CD drive (must be built-in CD drive).

2. Autorun start: wait briefly for the installation Setup program to start. If the Setup program does not
start, select Run from the Start menu and enter:
d:\SETUP
d is the letter for the applicable CD drive.
1-5
3. Follow the screen prompts.
After the software files are installed, the activation start window is displayed. The installation must be
activated to be functional. The activation process verifies the installation is authorized. An internet
connection is required to perform the activation.
Successfully completing the installation and activation process installs all the TopSpice program files,
model library files and sample circuit files. The folder “TopSpice” will be added to the Windows Start
programs menu, which contains the shortcut icons to launch TopSpice, support programs and
documentation files. The setup program will also add the following folders and subfolders:
[TopSpice]\Models contains all the simulation model library files.

[TopSpice]\Symbols contains schematic symbol library files.
[User Documents]\TopSpice\Parts default folder for user part files.
[User Documents]\TopSpice\Lib default folder for user model and library files.
[User Documents]\TopSpice\Circuits default folder for user project files.
[User Documents]\TopSpice\Examples contains example circuit files.
The installation setup can add the following Windows Explorer filename extension associations (this is
optional and only for user convenience):
Extension Open Command

.SCH TopSpice Schematic Editor
.CIR TopSpice Circuit File Editor
.MIS TopSpice Circuit File Editor
.OUT TopSpice File Browser
.LIB TopSpice File Browser
.SAV TopView Post-processor
.RAW TopView Post-processor
1.4.3 Upgrade Installation

If you are installing the Upgrade product, we recommend that you “uninstall” the previous installation of
TopSpice in your system before proceeding with the new installation. See next section “Uninstalling
TopSpice”. If you choose not to uninstall, you must specify a different installation folder (directory) and
program group name for the new installation.
Note: the above does not apply to service or maintenance updates. Follow the installation instructions
provided with the downloaded updates instead.
1.4.4 Uninstalling TopSpice

To properly uninstall TopSpice from your system, use the following procedure:
• From the Control Panel open the "Add/Remove Programs" icon.

• Select "TopSpice" from the list of programs.
• Click on the Add/Remove or Uninstall button.
Some of the program components and user files will not be removed automatically. You can delete the
TopSpice installation folder (directory) if you want after performing the “uninstall” procedure.
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INTRODUCTION
1.5 Configuration File Setup

The file TOPSPICE.INI contains several software default and configuration settings. It is located in the
TopSpice installation folder (if this folder is write protected, the copy in the Windows folder is used). This
is a text file that can be modified using any text editor such as Windows Notepad, or opened from
Windows Explorer.
The file is divided into several sections corresponding to the different programs in the TopSpice package.
A section starts with the section title name enclosed in brackets. For example, the configuration
parameters for the TopView graphics post-processor are found under [TopView]. Each section contains
one or more parameters, which follow the format:
keyword = value
keyword is the name of the parameter and value may be a number or string. For example,
LibraryFolder=d:\mylibs
When specifying colors, use the color code numbers given by the following table:
Code Color
0 black
1 blue
2 green
3 cyan
4 red
5 magenta
6 brown
7 light gray
8 gray
9 light blue
10 light green
11 light cyan
12 light red
13 light magenta
14 yellow
15 white
Some of the parameters and sections in the TOPSPICE.INI file are updated by the program during its
operation. These should not be changed by the user manually.
The following sections and parameters in the TOPSPICE.INI configuration file are user modifiable.
1.5.1 [TopSpice] Section
Keyword Description
ProjectFolder Default folder (directory path) for user project files.
LibraryFolder Directory path where the model library files are located. The simulator
will look for a library file here if it cannot find it in the current working
folder where the circuit file is located.
ExamplesPath Directory path where the example files are located.
1-7
SchematicCommand Command for schematic program.
EditFileCommand Command for text editor program.
BrowseFileCommand Command for output file browser program.
SetupSimulationCommand Command for simulator setup program.
SimulationCommand Command for simulator program.
XSpiceCommand Command for the XSPICE simulator engine option.
XSpiceOption If set to 1, it enables the XSPICE simulator engine option menu item.
LTSpiceCommand Command for the LTspice simulator option. The default value is the
default installation folder for LTspice.
LTSpiceCommandMode Specified the run mode for the LTspice simulator option: batch or
window (default).
LTSpiceOption If set to 1, it enables the LTspice simulator option menu item.
PostProcessorCommand Command for post-processor program.
PDFViewCommand Command for displaying PDF help files.
1.5.2 [Schematic] Section
Keyword Description
PartsFolder Default folder directory path where user part files are located.
PrinterPenWidth Sets the printer line width in dots. Default is determined by printer
resolution (dpi).
ScreenPenWidth Sets the screen line width in dots. Default is 1. The pen width
applies to all drawing elements on the screen except for text
characters. A value of more than 2 is not recommended.
WireColor Sets screen wire color code. Default value is 9 (light blue).
JunctionColor Sets screen junction dot color code. Default value is 0 (black).
SymbolColor Sets screen part symbol color code. Default value is 0 (black).
LabelColor Sets screen node label color code. Default value is 9 (light blue).
TextColor Sets screen text object color code. Default value is 0 (black).
CursorWireOption Selects one of the following wiring cursors: 0=arrow, 1=pencil

(default), 2=black pen, 3=crosshair, 4=black arrow.
CopyClipboardMetafileFormat Sets the graph format used for the “copy to clipboard” function as
follows: 0=auto select (default*), 1=Windows metafile (WMF),
2=Enhanced metafile (EMF).
1-8
INTRODUCTION
1.5.3 [Simulator] Section
Keyword Description
MaxMem Maximum simulator data memory space allowed in Kbytes (a value larger
than available physical RAM memory is not recommended). Default is
500000 (500MB). For example,
MaxMem=250000
This sets the maximum data memory to 250 MB.
MemSize Maximum available memory space in Kbytes. If 0, auto detect amount of

available memory. If greater than 0, assumes specified amount of memory in
Kbytes is available without checking (not recommended).
HSPICE$Syntax Selects the following HSPICE™ syntax priority rules: the character sequence
“ $” marks an in-line comment; the node names GND, GND! and GROUND
are assumed to be node 0. If 1, selected as default.
1.5.4 [TopView] Section
Keyword Description
CalculatorCommand Run command for Tools|Calculator menu command. This can be
any Windows application.
CopyClipboardMetafileFormat Sets the graph format used for the “copy to clipboard” function as
follows: 0=auto select (default*), 1=Windows metafile (WMF),
2=Enhanced metafile (EMF).
DisplayMode Selects display mode: 0=default (black background), 1=reverse
background (white), 2=monochrome mode.
DisplayRenderMode Selects screen plot rendering mode: 0=direct (default), 1=bitmap
mapping. You should select the "bitmap mapping" mode if you
experience screen display problems when plotting a large number
of data points using the direct mode.
FFTMaxSampleSizeN2 Sets the FFT function sample size limit power of 2 exponent. The
default value is 25 (32M points). Valid range is 2 to 29..
HistoryMaxKeep Sets the maximum number of history sessions to keep. The default
value is 10. The maximum number is 100. If set to 0, the history
function is disabled.
PlotArea Selects default plot area format: 0=square (default), 1=rectangular.
PrinterFontRatio Sets the printer/screen font ratio in percent. Default is 75. For
example, to make the printer and screen font sizes the same, set to
100.
PrintGridLineStyle Selects printed plot grid line style: 0=use printer dotted line
(default), 1=user “fine dotted” line style. If the grid lines on your
printed plot look very “coarse”, you can set this parameter to 1. This
produces a “fine dotted” grid line on the printed copies. However,
this will also considerably increase the printing time especially on
slow PostScript printers.
1-9
PrintGridLineThick Allows you to set the thickness of the grid lines on your printed
plots. To change the thickness, set to the desired thickness in
printer dot units (default is 1). For instance, if you want the grid
lines to be 2 dots thick, set it as follows:
PrintGridLineThick=2
PrintTraceColorn Sets color printer trace color mapping using color code numbers. n
is a trace number between 1 and 12. For example,
PrintTraceColor2=11
This sets the 2nd trace to "light cyan" color on the printed plots.
UnitScaleLabelMode Selects default axis unit scaling labeling mode: 0 append to axis
tick value 1 prefix to unit name on axis caption.
WaveFileSampleRate Sets the sample rate for saving audio .WAV wave files. Default is
22000. The allowed range is between 100 and 150000.
1.5.5 [JobStatus] Section
Keyword Description
ProjectPath Default directory path for your project files.
1-10
INTRODUCTION
1.6 Documentation and Manuals

The following manuals in PDF format are included:
User’s Guide General guide to product installation, operation and circuit simulation.
Simulator Reference Documentation of the simulator netlist syntax rules, circuit elements, models,
commands and postprocessor directives.
Schematic Editor Guide to Schematic Editor application.
TopView Guide to TopView postprocessor application.
A PDF document file viewer application is required to view these manuals (we recommend Adobe
Reader). If your system does not have a default PDF viewer installed and you don't want to install Adobe
Reader, you need to edit the TopSpice setup configuration file TOPSPICE.INI to use the included PDF
viewer to display the help and documentation files as follows:
1. Open Windows Explorer and navigate to the TopSpice 8 installation folder (for 64-bit systems the
default is "C:\Program Files (x86)\TopSpice\ver80").
2. Open the TOPSPICE.INI configuration file.
3. Under the [TopSpice] section header, add the following line
PDFViewCommand=[TopSpice 8 folder]\pdfview.exe
"[TopSpice 8 folder]" is your system TopSpice 8 installation folder full path.
4. The line can be inserted anywhere within the section.
5. Save and close the configuration file.
1.7 Documentation Notation Conventions

This document uses the following typographic conventions:
Examples Description
File|Open The names of menus and commands are in bold face. The | character indicates
a menu item or submenu.
Filename.txt File names, sample netlists, literal commands entered from the keyboard and
output produced in computer print appear in “typewriter face.”
node Words in italic indicate places for information that users must supply (for
example, a numeric value or name).
<model name> Italic words enclosed by <> describe a single item that the user must supply.
<parameter …> The ellipsis (…) indicates that a list of one or more items can be specified.
[IC=value] Items inside [ ] brackets, denote optional specifications.
1-11
1.8 Simulation Basics

The following chapters describes how to create a circuit, select the appropriate type of analysis, how to
interpret the output file data, and other general principles of circuit simulation. A "hands-on" approach is
best for learning how to work with circuit simulators. Running some sample simulations using small
circuits for which you can estimate the output results is the best approach.
Before going into the details of entering a circuit and running a simulation, some of the terminology used
throughout this manual are defined here:
Circuit Any electrically connected grouping of two or more components.
Circuit description Schematic drawing or SPICE netlist describing the circuit components and their
interconnections. A schematic drawing is created using the Schematic Editor. A
SPICE netlist file (circuit file) can be created directly using the Circuit File Editor.
Schematic file File containing a schematic drawing created using the Schematic Editor. To
simulate the circuit, the schematic drawing is compiled into a SPICE netlist,
which is saved in a circuit file.
Netlist A collection of text statements that describe the components in a circuit and their
interconnections.
Circuit file File containing one or more SPICE netlists along with the necessary simulator
control statements. This is actually the input file to the simulator program even
when the simulation is done from a schematic.
Stimulus An input (signal) source affecting the state of the circuit to evaluate its response.
TopSpice offers a variety of both analog (voltage and current) and digital stimulus
sources.
Analysis To analyze the response of a circuit you must simulate it. Before running a
simulation, you must tell the simulator what types of analysis to perform and the
output options you want. You can do this either using the simulation setup menu
options or directly by SPICE command statements.
Convergence SPICE uses numerical methods to solve the system of circuit equations. It
converges to the correct solution using an iterative technique. In some cases,
SPICE might not converge (i.e.: cannot find an acceptable solution within the
specified error tolerances).
Pre-processing Any processing of the input file prior to the start of the actual simulation. For
example, model library searches.
Post-processor A program that further processes and/or plots the output data file generated by
the SPICE simulator.
When using a SPICE circuit simulator, it is a good practice to keep these points in mind:
• The simulator does not analyze circuits for topology errors (except those that violate the simulator
rules). The results you obtain are "correct" only if your circuit input file is correct. If you get
unexpected results check your circuit description carefully.
• Most device models are accurate only over a limited range of the device’s operating range. If a device
in your circuit is operating outside the "typical" operating range, you should check that the model is
still accurate.
1-12
INTRODUCTION
• Numerical simulations are subject to round-off errors and approximation errors in the solution
algorithms. These errors tend to accumulate for long simulations, very large circuit sizes, and circuits
with large dynamic ranges. Always keep a skeptical attitude when analyzing simulation results. If the
simulation output seems to be physically impossible probably it is wrong.
• Real life circuits are subject to parasitic effects. In high gain or high frequency circuits parasitic effects
may dominate their performance and behavior. The only parasitic effects included in a SPICE
simulation are those you put in.
• When the signal wavelengths become comparable or shorter than the circuit physical dimensions,
distributed effects must be modeled to accurately simulate such circuits. TopSpice allows you to
include distributed effects using transmission lines, Laplace transforms, frequency response tables
and s-parameter tables. You can also develop an approximate equivalent model using lumped
elements.
• SPICE is an electrical simulator. Although it is possible to simulate systems that are not purely
electrical, such as motors and lamps, you must develop an electrical analog of the non-electrical
system first.
• All circuit voltage values are defined with respect to the ground node. The simulator ground node is a
mathematical reference point only. It is not equivalent to "earth" ground.
• Circuit branch currents are not explicitly calculated in SPICE simulations. All simulation current output
values are device currents. A current value sign is defined by convention. For sources, current flowing
out of the "positive" (first) terminal is negative. For other two terminal devices, current flowing into the
first terminal is positive. For devices with more than two terminals, such as a transistor, current
flowing into any terminal is positive. Hence, the sum of all the device terminal currents is zero.
1-13
1-14
RUNNING TOPSPICE
CHAPTER
2 USING TOPSPICE
2.1 User Interface

TopSpice uses the Microsoft Windows graphical user interface. All commands are invoked through pull-
down menus or dialog boxes (pop-up menus). If you are not familiar with the Windows interface, we
recommend that you review the Windows documentation.
All the TopSpice programs also follow these general rules:
• Many of the menu functions have matching keyboard “shortcut keys”, that are equivalent to selecting
the menu item using the mouse (see the appropriate sections for the schematic editor, text editor and
TopView programs for a list of the available keys).
• If a menu command description is followed by an ellipsis (…), this indicates that a subsequent dialog
will be displayed when the command is selected.
• If a toolbar is available, it allows quick access to commonly used menu commands. Hovering the
mouse over a toolbar icon displays a tool tip with a description of the command it performs.
• The left mouse button activates a function or command. The right mouse button either displays a
popup menu or cancels the current operation (the Esc key also cancels an operation).
• On all dialog text edit or entry boxes, the standard Windows shortcut keys can be used to perform
text editing functions (cut, copy and paste) to, and from, the Windows clipboard. This can be useful
when copying entries from one menu to another.
2.2 General Operation

The general operating procedure for designing and simulating circuits using TopSpice is as follows:
• Create or edit the circuit schematic drawing using the TopSpice Schematic Editor. Or, create or edit
the circuit SPICE netlist (text) file using the TopSpice Circuit File Editor.
• Include links to any SPICE model files or library files necessary to simulate the circuit.
• Setup the desired simulation analyses.
• Setup the desired simulation output and “auto-plotting” options.
• Simulate the circuit. When the simulation completes successfully, the simulator window is closed and
the TopView post-processor is started automatically. If there were simulation errors, you can choose
to browse the output file for error messages using the TopSpice File Browser.
• The TopView post-processor automatically plots any “auto-plot” commands, if any, or displays the
“probe” selection menu. At this point, the user can plot any desired simulation data and perform
further analysis of the simulation results.
• After you are finished with all the desired post-processing operations, you should exit and close
TopView. This will return you to either the Schematic Editor or the Circuit File Editor window. If you
run another simulation without closing the plot window, TopView will open another plot window after
the new simulation is finished. However, if the TopView "auto close" option is enabled, the previous
2-1
Figure 2.1 TopSpice launch screen
plot window is automatically closed before opening a new one. The data and plots for an already
open TopView window are not updated after each simulation.
Most circuit designs involve an iterative process of modifying the circuit and repeating the simulation until
the desired performance is achieved. To speed up this process, the TopSpice “zip mode” allows quick
cycling between the editing, simulation and plotting functions. From the schematic or text editor, pressing
Alt+Z saves the circuit, starts the simulation and plots the results without going through any menus. If you
are in TopView, Alt+Z saves the current plot options, exits TopView and returns to the editor screen.
2.3 Starting TopSpice

The recommended way to start TopSpice is to open the "TopSpice 8" icon/tile in the Start menu
"TopSpice 8" folder or on the Windows desktop. For example, choose Start > Programs > TopSpice 8 >
TopSpice 8. If you installed TopSpice in a different folder, choose that folder from the Start > Programs
menu.
You can also choose to start directly the different component applications if this is more convenient. The
Schematic Editor application can be started by opening its icon/tile either in the TopSpice Start menu or
from the Apps window. The other component applications can be opened from the Apps window.
The TopSpice launch screen menu simplifies the task of starting a new or previously saved circuit design
project, switching between schematic or circuit file editors, and opening the example circuit files.
2.3.1 New Circuit

Use the New Circuit button to start a new circuit project. Depending on the Open As preference setting
it will start the Schematic or Circuit File (text) editor with an empty working area. By default, your circuit
project files are saved in the TopSpice projects subfolder “[User Documents]\TopSpice\Circuits” – you can
choose to open a different folder when you specify your project file name.
2-2
RUNNING TOPSPICE
2.3.2 Open Last Project

Use the Open Last Project button to resume working on the last circuit project. The “Last Project” box
shows the last project file name and title. You can also select to open any of the most recent projects
listed by clicking on the desired file name first.
2.3.3 Open As Options

TopSpice offers the convenience of working with a schematic drawing or a SPICE netlist directly
depending on your needs or preference. The Open As Schematic option launches the TopSpice
Schematic Editor. The Open As Circuit (text) file option launches the TopSpice Circuit File Editor. You
must select the Open As option before clicking on the New Circuit or Open Last Project buttons.
You can switch between the schematic and SPICE circuit file modes at any point during the project. If
you start the project in schematic mode and then switch to the SPICE circuit file mode, the Circuit File
Editor loads the last SPICE circuit file created by the schematic editor from the circuit drawing.
If you start the project in SPICE circuit file mode and later switch to the schematic mode, the Schematic
Editor starts with an empty sheet (TopSpice cannot create a schematic drawing from the SPICE circuit
file). However, you can insert a previously created netlist to the schematic using the .INC command.
Hence, when switching from circuit file to schematic, you should either open a new schematic under a
different name or rename the existing circuit file.
Whenever the Schematic Editor generates a SPICE circuit file, it overwrites the existing circuit file.
Hence, any manual changes to the SPICE circuit file you make will be lost. If you need to make manual
changes or entries to the SPICE circuit file, you should add them into the “miscellaneous commands”
(.MIS) file.
2.3.4 Open Saved Schematic

Use this button to browse for and open any previously saved TopSpice circuit schematic (.SCH) files. By
default, it opens the last working folder, if any, or the TopSpice “\Circuits” subfolder.
2.3.5 Open Saved SPICE (text) File

Use this button to browse for and open any previously saved SPICE netlist circuit (.CIR) files. By default,
it opens the last working folder, if any, or the “\Circuits” subfolder.
2.3.6 Apps
The Apps icon/tile and button on the TopSpice launch screen opens the “TopSpice 8 Applications”
window with buttons to open the following product component applications: Schematic Editor, Circuit File
Editor, TopView post-processor, Model Library Database and Flat Netlist Utility (converts SPICE netlists
with subcircuit calls into a flat netlist).
2.3.7 Help
The Help icon/tile and button on the TopSpice launch screen opens the “TopSpice 8 Help” window with
buttons to open the following help functions:
User support services: information and contacts; the Email Support Request button opens your system
default email client program with a message containing your TopSpice product details and addressed to
Penzar Development support, the user must add the request message and send it; the Online Support
Request Form button opens the online form using your system default browser.
Open documentation: User’s Guide, Simulator Reference, Schematic Editor, TopView, Readme file.
2-3
Examples: Open Example File, List of Example Circuits.
Online services: the Check Update Information button opens the TopSpice Update information
webpage using your system default browser; the Email Update Request button opens your system
default email client program with a update request message containing your TopSpice product details and
addressed to Penzar Development support, the user must add any other required details to the message
and send it; the Online Registration Form button opens the online registration form using your system
default browser; the Email User Registration button opens your system default email client program with
a message containing your TopSpice product user registration details and addressed to Penzar
Development support, the user must add any other required details to the message and send it.
These same help functions are available under the Schematic Editor Help menu.
2.4 Examples
The included example circuit files are located in the “[User Document]\TopSpice\Examples” subfolder.
Examples for both schematic drawing circuits and SPICE netlist (text) circuits are included. The complete
list of example circuits and descriptions is available in the text file Examples.txt which can be opened
using the List of Examples Circuits button on the Help window.
The example circuits are sorted into subfolders by category. For instance, the "General" subfolder
contains examples of general TopSpice features applicable to any type of circuit.
The example files can be conveniently opened using either the Open Example File button on the
TopSpice launch screen Help menu or the Help|Examples menu command. To display the example
schematic circuit files, select “Schematic files (*.sch)” from the “File types” box (default). To display the
example SPICE netlist circuit files, select “SPICE circuit text files (*.cir)” from the “File types” box.
2.4.1 Running Example Schematics

To simulate an example schematic circuit, follow this procedure:
1. Open the desired example schematic file listed on the “Open Example” dialog window (such as
Example.sch). When the schematic file is opened, the Schematic Editor is launched and the
example schematic loaded.
2. To view and navigate the schematic use the zoom commands, scroll bars, arrow keys, shortcut keys,
or place the mouse at the edge of the drawing window to automatically pan the schematic (if auto-
panning is on). You can also select View|Full Page command to fit the entire schematic to the
drawing window.
3. To view the schematic title block, which includes the circuit title and other descriptive information, you
can either zoom in on the lower right corner or use the Edit|Title block command.
4. To view the analysis commands specified, select Simulation|Setup menu. Additional commands are
defined under the Simulation|Open User SPICE Commands File.
5. Simulate the circuit by selecting the Simulation|Run Simulation command. After the simulation is
completed, the results are automatically plotted by the TopView post-processor program.
6. To return to the schematic, select File|Exit from the TopView menu.
2-4
RUNNING TOPSPICE
2.4.2 Running Example SPICE Circuit Files

To simulate an example SPICE netlist circuit, follow this procedure:
1. On the “Open Example” dialog window, select the “SPICE circuit (text) files (*.cir)” file types option.
Open the desired example circuit filename (such as "DC motor.cir"). When the circuit file is
opened, the TopSpice Circuit File Editor is launched and the sample circuit loaded.
2. Simulate the circuit by selecting the Simulation|Run Simulation menu command. After the
simulation is completed, the results are automatically plotted by the TopView post-processor
program.
3. To return to the circuit file, select File|Exit from the TopView menu.
2.5 TopSpice Files

After a TopSpice session is completed several files may be generated on the project working directory for
the following purposes:
*.SCH schematic drawing files.

*.HSC schematic hierarchical block drawing files.
*.SBK schematic backup files.
*.CIR circuit SPICE netlist files.
*.MIS miscellaneous commands files.
*.ALT .ALTER commands files.
*.PPD post-processor directives files.
*.MAP schematic node cross reference map files. The .MAP file gives a listing of the wires and
devices connected to each node in a schematic.
*.OUT simulation output listing files.
*.SAV simulation binary output data files.
*.OPB simulation bias voltages binary output data files.
*.Fnn plot format files.
*.Wnn plot trace history data files.
*.Onn plot trace history output files.
TopSpice also creates several temporary files while it is running. These are normally deleted when you
exit the program. However, if there is an abnormal termination or system crash, your project directory may
contain files with names such *.TMP, *.$$$, and *.PRE. These files are not needed and you should delete
them.
When working with schematic symbols, parts and simulation models, the following files may be created:
*.SYM schematic symbol files.

*.IDX symbol library index files.
*.TSP schematic user part files.
*.LIB model library files.
2-5
2.6 General Syntax and Design Rules

The following general syntax rules for names, numbers and component values, and circuit design rules
apply to both schematic designs and SPICE text netlists. See the Simulator Reference manual for more
detailed descriptions of all the simulator syntax rules.
2.6.1 Names
Names are used to identify different instances of circuit elements, device models, subcircuits and nodes.
Element instance reference names are formed by appending to the element type letter an alphanumeric
string (e.g., RLOAD1 for a resistor). TopSpice allows device model names to start with any character
including numeric digits (e.g., 2N3903 is a valid model name).
All names can be any alphanumeric string up to 64 characters long. Names that exceed the length limit
are truncated. Names can contain any of the following characters:
A through Z (upper and lower cases – SPICE syntax is case insensitive)

0 through 9
$ _ @ & # ! %? (to avoid incompatibility with HSPICE, a name should not start with the $
character)
Names cannot contain spaces or punctuation characters. In addition, the following characters are not
allowed in names:
+-=*^/<>()[]{}"'`
The use of other characters not explicitly listed here should also be avoided because they could cause
syntax conflicts under some conditions or not be valid with other SPICE versions.
2.6.2 Node Names

Node names are used to identify the electrical nodes to which the device terminals are connected to form
the circuit. Older versions of SPICE only allowed integer node numbers as node names. TopSpice allows
the use of any alphanumeric string up to 64 characters long as node names. The following names are all
valid node names:
0 Gnd 2 2A CLOCK A15 #12 B_SUPPLY
Node names are always treated as strings even if they are numbers or start with a digit. Hence, nodes
"0" and "00" are different nodes. This is the convention used by most SPICE programs. There are no
naming differences between analog and digital nodes.
Node names should be kept as short as possible for convenience when referencing them in commands
and expressions, and to avoid cluttering the output plots with long trace names. The common practice is
to use numbers to name nodes for which no meaningful name is needed.
2.6.3 Global Nodes

Global nodes are common throughout the entire circuit including subcircuit definitions. Unlike local nodes
in a subcircuit, there is no need to declare global nodes as external nodes to be accessed outside the
subcircuit. Global nodes are useful for defining common supply nodes and signals such as clock and
reset signals. See the Simulator Reference manual for more detailed description for specifying global
nodes.
2-6
RUNNING TOPSPICE
In addition to user defined global nodes, the following node names are reserved as predefined global
nodes in TopSpice:
Node Name Description

0 Analog ground
$G_0 Analog ground (same as 0)
$G_DPWR Analog supply node for A/D interfaces
$D_LO Digital fixed 0 signal
$D_HI Digital fixed 1 signal
$D_X Digital fixed X signal
$D_NC Digital no-connection node (floating)
_D_LO Digital fixed 0 signal
_D_HI Digital fixed 1 signal
_D_X Digital fixed X signal
_D_NC Digital no-connection node (floating)
GND Analog ground (.HSPICE$ syntax option)
GND! Analog ground (.HSPICE$ syntax option)
GROUND Analog ground (.HSPICE$ syntax option)
The above node names should only be used for the purposes described.
2.6.4 Voltage and Current Variables

Some statements require the user to specify voltage or current variable names. A voltage variable
specifies the voltage at a circuit node. The following syntax is used for voltage variable names:
V(node)
or
V(node1,node2)
node is the node name. The second form specifies the voltage difference between nodes node1 and
node2. Examples: V(5) V(out) V(3,8)
A current variable specifies the branch current through a voltage source. The syntax for current variable
names is
I(x)
x is the reference name of a device. Depending on the context, different device types are supported. V or
E voltage sources are always supported for current variables. Examples: I(Vdd) I(E2)
Positive current flows from the source positive terminal, through the source, to the negative terminal. The
simulator analog behavioral modeling and data output commands also support current variables for all
two terminal devices and transistors. For transistors, the current variable format is
Ip(x)
where p is the transistor pin letter (ex.: C for collector or D for drain).
2.6.5 Number Formats

A number field required by the simulator may be specified using an integer number (ex: 12, -48), a
floating point number (ex: 3.14159), either an integer or floating point number followed by an integer
exponent, a.k.a. “Fortran scientific format” (ex: 1E-12, 2.54E3), or either an integer or floating point
number followed by one of the following scale factors:
2-7
Factor Name Value

f femto 10-15
p pico 10-12
n nano 10-9
u micro 10-6
m milli 10-3
mil mils 25.4×10-6
K kilo 103
MEG mega 106
G giga 109
T tera 1012
% percent 0.01
Note: “M” is the same as “m” (10-3) not “MEG” because SPICE syntax is case insensitive. Windows
extended Greek character µ (ASCII code 181) is also accepted as the micro scaling factor (same as u).
Letters immediately following a number that are not scale factors are ignored, and letters immediately
following a scale factor are ignored (except for math operator characters which are not allowed). Hence,
10, 10V, 10Volts, and 10A all represent the same number, and m, mA, msec, and mF all represent the
same scale factor. You should choose the most convenient number format. For example, 1000, 1000.0,
1000Hz, 1E3, 1.0E3, 1KHz, and 1K all represent the same number. However, if a number field contains
any of the following characters: + - * / ^ & | < > ~, after the scale factor, a warning message is generated.
This is to warn about possible incorrect use of expressions.
-15
Note: as listed above the letter “f” or “F” is the scaling factor for 10 . Hence, when specifying capacitor
-15
values “2F” is 2×10 farads not 2 farads.
2.6.6 Component and Model Parameter Values

Passive component (resistors, capacitors and inductors) and device model parameter values can be
specified in integer, floating point or scientific format, with or without a scaling factor.
Linear resistors, capacitors and inductors may also be given negative component values. This can be
helpful for designing certain types of circuits in dc or ac analysis. However, use of negative values during
transient analysis can lead to convergence problems.
Component values of zero are not allowed for resistors, capacitors and inductors.
Instead of numeric values, expressions can be specified for component and device model parameter
values. For example,
C1 3 5 {2*PI*TAU/RMAX+1.2u}
2.6.7 Circuit Topology Rules

TopSpice circuit files must follow these general circuit topology rules:
• The circuit cannot contain a loop of voltage sources and/or inductors, and it cannot contain a cutset of
current sources and/or capacitors.
• Voltage sources (V, E and H elements) with shorted output terminals are not allowed.
• Zero value resistors are not allowed.
• There must be at least one connection to the ground (0) node in the circuit.
2-8
RUNNING TOPSPICE
• Each node in the circuit must have a dc path to ground except for digital nodes and grounded voltage
source output nodes (this requirement can be bypassed for some simulations using the NODCPATH
option).
• Every node must have at least two connections except for transmission line nodes (to permit
unterminated transmission lines), MOSFET substrate nodes (which have two internal connections
anyway), grounded voltage source outputs, DTOA output and digital output nodes.
• With respect to branch voltages and currents, SPICE uniformly uses the associated reference
convention (current flows in the direction of voltage drop).
2.7 Creating Design Projects

Creating a TopSpice circuit design project involves these steps:
1. Enter the circuit design. You can enter your circuit as a schematic drawing, as a circuit (SPICE netlist
text) file, or a combination of both. The most convenient way to start is to click on the New Circuit
button on the "Launch TopSpice" window.
2. Label all the circuit nodes on the schematic that you are interested in observing or need to reference
later on. Although you could use the node numbers assigned by the schematic editor, these might
change as you edit the schematic.
3. If any device models are used in the circuit, you need to provide the model definitions for them,
and/or specify the model files or model library files where they can be found. This is not necessary if a
model is in one of the default model libraries (these are automatically searched).
4. Specify the simulation analysis commands. Before you can simulate your circuit, you need to specify
the type of analyses you want (DC, AC, transient, etc.), operating conditions such as temperature,
output data options, and/or other simulator run-time options. This is analogous to setting up the
measurements you want to perform when working with circuits built on breadboards. TopSpice offers
several options for specifying simulation and analysis commands: using the Simulation|Setup menu
(the easiest way), add the commands directly on the drawing as schematic text objects (useful for
documentation purposes), enter them manually under the Simulation|Open User SPICE
Commands File option, or use a combination of any of the previous methods.
5. Simulate the circuit. Compared to working with breadboards, running the simulation corresponds to
turning the power on and recording the responses.
6. View the simulation results. After the simulation is successfully completed, TopView is automatically
invoked and the results plotted. TopView functions as an oscilloscope that lets you view waveforms,
perform measurements and other analyses of the data.
If you are using TopSpice for the first time, it is recommended that you run some of the example circuits
provided before starting your own circuit (see the section “Running Example Schematics” in this chapter).
2.8 How to Create a Schematic

This section gives a brief description of the procedures for creating a typical schematic drawing. See
Chapter 3 for more detailed descriptions of the Schematic Editor commands and features.
1. From the “Launch TopSpice” screen, select Open As Schematic if not already selected.
2. Click on the New Circuit button. Enter your project file name.
3. The Schematic Editor is invoked with a blank sheet with the project name “untitled”. Select the
File|Save as command, and specify the desired project file name.
2-9
4. Select Edit|Title block to add a title for your circuit and other descriptive information.
5. Draw your circuit schematic using the Insert menu commands as described in following subsections.
If you are new to using schematic capture programs, it is highly recommended that you hand draw your
circuit on paper first. This will minimize the need to edit and move components around the schematic,
which is the most time consuming part of drawing a schematic on screen.
2.8.1 Selecting Symbols

The TopSpice Schematic part symbol names are not arbitrary. The first letter in the symbol name
indicates the type of SPICE element it represents. For example, any name starting with the letter Q
describes a bipolar transistor. The only exceptions are the ground and power supply symbol names. The
name may include a description, which is preceded by the semicolon character.
In the default symbol library the names for the standard SPICE elements are kept as short as possible
(usually one or two characters) so they can be selected using a single keystroke if possible. Names for all
the macromodel symbols start with the letter X since they are SPICE subcircuit elements.
2.8.2 Placing Parts

To place a new part on the schematic, select the Insert|Part menu command. You have the option of
placing a "generic" symbol, a part from the TopSpice model libraries, a user part, a hierarchical block or a
U logic element symbol. For instance to place a generic part such as a resistor, choose Insert|Part. A
part selection dialog box appears which shows the previously placed part (if any) in the input box and
options for selecting parts from different sources. For the resistor, you can select it from the “Common
part symbols” list.
To specify a new part, either pick from the list using the mouse or keyboard, or type the new part name
(you don't need to enter the description portion which is preceded by the character ";"). To choose the
previous part, just click Ok.
The selected part symbol is displayed on the screen in red. Move the symbol to the desired location
using the mouse. To place the part, click or press Enter. To cancel, right-click or press the Esc key.
2.8.3 Specifying Part Attributes

Most parts require that you specify the following set of attributes: reference name, value or model name,
and optional parameters. To specify part attributes, select the Edit|Attributes menu command while
placing the part or afterwards. TopSpice Schematic automatically increments the reference name as the
parts are added to the schematic. You can also change the attributes by double-clicking on a part on the
schematic.
2.8.4 Rotate, Mirror and Flip

You can change the view of most symbols by performing the following operations: rotate, mirror and flip.
The rotate, mirror and flip commands can be combined in any sequence to obtain the desired symbol
orientation and view. If you perform more than 8 rotate, mirror or flip operations the symbol is restored to
its original state. Some symbols might not support the rotation operation.
2.8.5 Wiring the Circuit

Wires and junctions are used to wire together parts and indicate electrical connections. To draw a wire,
select the Insert|Wire menu command. Move the cursor to the wire starting position, and click or press
the Enter key. Now move the other wire end to the desired location, and click to complete the wiring.
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RUNNING TOPSPICE
When wiring, the wire will form a right angle at the point where you move the cursor away from a vertical
or horizontal line. Hence, you can draw a straight wire or bent wire. If you want to change the direction of
the wire being drawn (for example, if you started out as a vertical wire but you want to make it horizontal)
the cursor must be moved back to the starting point, and then moved in the desired new direction. To
cancel the wiring operation, press the right mouse button or the Esc key.
A right angle wire is saved as two wire segments (one horizontal and one vertical). Hence, edit
operations such as cut and copy will apply to each segment separately.
The junction symbol (a large dot) indicates an electrical connection between wires or between a wire and
a part pin. To draw a junction, select the Insert|Junction menu command and move the cursor to the
desired junction point. Click or press the Enter key. A junction must be manually placed to indicate
connections between two wires crossing at right angles. For all other connections the junction symbol is
optional or it is automatically placed if the “auto-junction” feature is enabled.
2.8.6 Electrical Connections

TopSpice Schematic uses a set of rules to determine if wires and part pins make electrical connection
when generating the SPICE netlist for the schematic. Electrical connections can be made by physical
(wired) connections or by using node labels and pin names (labeled connections).
The basic rule for a physical connection is that a wire end, or a part pin “connecting” end (indicated by a
small square), must contact another wire anywhere, or pin connecting end, to make electrical connection
between the two. If the “auto-junction” function is enabled, junction dots are automatically placed as
required. However, the junctions are optional for these connections. To connect two wires crossing at
right angles you must place a junction dot manually.
Note: a part pin can only be connected by its connecting end.
The alternative to wired connections is to use labeled connections, which consist of any set of wires and
pins with the same label names (see next section).
2.8.7 Node Labels and Numbers

Node labels serve three purposes: to document meaningful points on the circuit; to provide a name so a
node may be referenced somewhere else; to connect together nodes with the same names without the
need of wire connections, which sometimes are impractical.
To assign a node label to a wire or pin, select the Insert|Label Node menu command and enter the label
text at the prompt. Move the label to a point near the wire or pin to be labeled. The label must be within
one grid unit of a wire or pin to be assigned to it. To place the label, click or press the Enter key. If the
label was positioned properly next to a wire or pin it will be displayed using the same color as the wire
indicating that it is a node label. Right-click or press the Esc key to cancel a label drawing operation.
TopSpice Schematic automatically assigns node numbers to nodes without user assigned labels. The
default starting node number is 1 and the node number is incremented by one for subsequent nodes. To
display these node numbers, select the View|Node Numbers menu command.
Node names for ground, power rails and I/O pins are special cases. The ground node is always named
"0" regardless of any user assigned label. A ground node is any wire or pin connected to the ground
symbol (0 or GND). Power rails are represented by the V+ (or POWER+) and V- (or POWER-) symbols.
Any wire or pin connected to a power rail symbol pin is assigned a node name, which is identical to the
power rail name (reference attribute). For example, if the power rail is given the name VCC the node will
also be named VCC. Hence, all power rail nodes with the same node are tied together as they should be.
Any wire or pin connected to an I/O pin symbol is assigned the I/O pin name as the node label.
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2.9 Simulating Your Circuit

Most simulation analysis commands can be specified by selecting the "Simulation Setup" menu options.
Experienced SPICE users also have the option of entering commands in text form directly on the
schematic drawing or a separate command file.
1. After the circuit drawing is complete, select Simulation|Setup to specify the desired analyses to be
simulated and the results to be plotted.
2. Select Simulation|Run Simulation to simulate your circuit and plot the results.
3. If the simulation does not proceed because of an error, you can browse the output file by selecting
Simulation|Browse Output File for error messages. Most error messages are self-explanatory.
After making the necessary changes run the simulation again.
See Chapter 5 for detailed information on running simulations.
2.10 Waveform Plotting and Analysis

The TopView post-processor and plotting program is automatically invoked when a simulation run is
completed successfully. Then, TopView performs any specified post-processing and plotting commands
on the simulation output data. See Chapter 8 TopView Reference for more detailed descriptions of the
TopView commands and features.
Normally, the user should exit TopView (close the plot window) when finished viewing the plot and before
running another simulation. However, if the "Auto Close Option" is enabled (default), TopView
automatically closes the plot window and exits the program when the next simulation run is finished and it
is ready to plot again. This avoids the need to manually close the plot window when performing multiple
simulation runs.
When TopView is first invoked, it will attempt to “auto-plot” the simulation results. TopView can auto-plot
either #AUTOPLOT commands specified by the user or .PRINT data. If there are more than one possible
auto-plot, a selection menu is displayed which allows the user to pick the desired plot.
To display a new plot, select the Plot|Autoplot command.
The Plot|Probe command allows the user to choose and plot any of the simulation output data variables
available. Probe mode is automatically invoked if there is nothing to auto-plot.
A TopView graph can include up to 8 separate plots. All the plots share the same X axis. TopView
attempts to put different type of variables into different plots. For example, voltages and currents are
automatically plotted in two separate plots. You can add or remove plots, or move traces to different plots
using thet Traces menu command.
2.10.1 Cursor Measurements

Two plot cursors are available. To place cursor 1 on a trace, select Cursors|Cursor 1 active/select
command. A “Cursor window” will pop-up displaying the name of the trace and data point values for the
cursor. Then use the up and down arrow keys to move the cursor to the desired trace. To place cursor 2
on a trace, select Cursors|Cursor 2 active/select command.
To move the cursor over the trace, you can click anywhere inside the plot at the desired X value (you
don’t have to click over the trace), or use the left and right arrow keys. You can use the Home and End
keys to quickly move to the start or end of the trace. To rapidly step along the trace, use the Tab key.
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RUNNING TOPSPICE
2.10.2 Plot Axis Limits and Options

There are two ways to set the plot axis limits. To quickly zoom in to a section of the plot, use the
View|Zoom command. To precisely change the axis limits, select Axis|Limits command. After zooming
in or manually setting the axis limits, the user can scroll the plot X axis left-right and the Y axis up-down
using the cursor keys.
The user can add, edit or delete the plot axis captions using the Labels|Axis command. Several plot axis
options can be changed using the Axis|Options command such as linear or log scale, unit name and
scaling factor.
2.11 TopSpice Simulator

The TopSpice simulator is an enhanced version of the industry standard SPICE circuit simulator program.
The simulator is a separate Windows application that can be run either from the Schematic Editor and
Circuit File Editor menu commands or directly in "command line" mode. The only interface between the
user front-end applications and the simulator are the input and output files.
2.11.1 Simulator Input File

The TopSpice simulator input files are text (ASCII) files using the standard U.C. Berkeley SPICE format.
The TopSpice netlist syntax is a superset of the standard SPICE2G6 syntax with extensions to handle
digital elements, behavioral modeling and other TopSpice enhanced features. TopSpice also accepts
tm tm
many SPICE3, PSpice and HSPICE netlist syntax extensions.
The circuit to be analyzed is described to the simulator by a set of circuit element statements, which
define the circuit components and their electrical connections. See the "TopSpice Circuit Netlist File"
section for more details.
2.11.2 Simulator Output Files

Most TopSpice simulations create two output files: an output listing (.OUT) file and a binary data (.SAV)
file. The output listing file is in SPICE2G6 output format, and it can be examined using the TopSpice File
Browser or any other text file editor program.
The binary data file is created contains simulation results data in a proprietary compact binary format. By
default TopSpice will not store any simulation data unless at least one output command is specified in the
circuit file – the Schematic Editor includes the .PROBE command by default.
2.11.3 Simulator Command Line Operation

The TopSpice simulator program can be run in "command line" mode to directly simulate a SPICE netlist
circuit file. The command line syntax is
[<topspice directory path>\]TSIM32.EXE filename [option]
<topspice directory path> is the TopSpice installation folder directory path – this is required to run the
command from a different directory.
filename is the SPICE netlist circuit file name. The default file name extension ".CIR" is appended if no
extension is given. File name directory path is only needed when running from a different directory. If the
file name contains spaces it must be enclosed between quotation marks.
option is one of the following command line options:
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Option Effect
-tss Runs simulation, plots results and closes simulator window.
-batch Runs simulation and closes simulator window.
-noshow Runs simulation without displaying simulator window (minimized window mode).
The simulator command can be given from the Windows Start|Run menu command dialog, a batch file, a
script file, the MS-DOS command prompt, or as a system command from within another program.
Examples:
TSIM32.EXE AMP.CIR
TSIM32.EXE "\My Circuits\AMP.CIR" –batch
"C:\Program Files\TopSpice\TSIM32.EXE" AMP.CIR –tss
The TopView post-processor program can also be run in batch mode. See the TopView section for more
details.
2.11.4 Simulator Memory Usage

The TopSpice simulator program will “lock” for its own use all the available system memory up to the
value specified by the parameter MaxMem (default is 100 Mbytes), in the configuration file TOPSPICE.INI
(see Sec. 1.6), when performing a simulation. For maximum system reliability, we recommend that you
limit MaxMem to the smallest value that will allow simulating all your circuits, especially if you are
performing any kind of intensive multi-tasking. The actual amount of data memory available to the
simulator is given by
1. Total free memory available after loading the simulator module if less than MaxMem value.
2. MaxMem value if available free memory is larger.
3. At least 500 Kbytes is always available.
As a rule of thumb, the simulator can handle approximately 1000 components per megabyte of RAM.
Circuits with high transistor content or long transient analysis will require substantially more memory.
2.12 Simulator Engine Options

The TopSpice framework allows other simulators to be used for performing the simulation besides the
default TopSpice simulator. An alternate simulator engine can be selected using the
Simulation|Simulator Engine Option menu command. The following options are available: XSPICE
TM
option, LTspice simulator and other simulator. You must select the option before running the simulation.
2.12.1 XSPICE Option

This is basically the public domain XSPICE simulator modified to work within the TopSpice design
framework. This option is available from Penzar Development. This is not an active product. Support for it
is limited. To enable the XSPICE option, the following TOPSPICE.INI file configuration parameters must
be specified under the [TopSpice] section:
Parameter Description
XSPICECommand Specifies the location of the XPICE simulator program file. There is no need to
specify this if the XSPICE Option was installed to the TopSpice default installation
folder.
XSPICEOption Must be set to 1 to enable XSPICE Option menu item. Set to 0 to disable it.
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RUNNING TOPSPICE
2.12.2 LTspice Simulator

TM
LTspice is a simulator available from Linear Technology Inc. To use this option, you must install
LTspicein your system. This option can be useful if you need to simulate LTspice encrypted models. The
entire simulation must be compatible with the LTspice simulator syntax rules. The LTspice simulator can
be run either in window or batch mode. TopView can open LTspice simulation *.log files and plot LTspice
*.raw files in ASCII mode data only. In batch mode, TopSpice waits until the LTspice simulation is
finished, then, it opens TopView. Note: LTspice does not open any windows or show any progress
information when running in batch mode.
To enable the LTspice option, the following TOPSPICE.INI file configuration parameters must be
specified under the [TopSpice] section:
Parameter Description
LTspiceCommand Specifies the location of the LTspice simulator program SCAD3.EXE file.
Default value is the LTspice default installation folder.
LTspiceCommandMode Specifies the run mode: batch or window (default).
LTspiceOption Must be set to 1 to enable LTspice Simulator menu item. Set to 0 to disable it.
For example,
LTspiceCommand=C:\Program Files (x86)\LTC\LTspiceIV\scad3.exe

LTspiceCommandMode=batch
LTspiceOption=1
2.12.3 Other Simulator

Any other SPICE simulator program can be used to simulate the circuit if it meets the following conditions:
• It can run in command line mode using the following format:
name.exe [parameters] inputfile outpufile
• It accepts standard SPICE or PSpice compatible circuit netlist files as input.
To enable the Other Simulator menu option, the TOPSPICE.INI configuration file SimulationCommand
parameter must be specified under the [TopSpice] section.
2.13 TopSpice Circuit Netlist File

The TopSpice simulator input is a SPICE netlist in text form. The Schematic Editor will create a netlist
circuit file automatically before running a simulation from the circuit schematic. If you prefer, you can
manually create the circuit netlist file using the Circuit File Editor instead of drawing the schematic.
TopSpice circuit netlist files must follow these general format rules:
• The first line in the input file must be the title statement. The title statement can contain any text.
• The last line must be ".END".
• Except for the title and .END statements, the order of the remaining statements is arbitrary. Certain
command statements to turn on or off optional features are position sensitive.
2-15
• Comment lines, indicated by "*" in column 1, can contain any text and can be used to clarify the
circuit description. Comment lines can also be placed between continuation lines. TopSpice also
allows in-line comments marked by ";" (all text on the line after it is ignored) and multiple comment
lines enclosed between "/*" and "*/" comment start and end markers.
Fig. 2.2 is the circuit netlist file for the sample circuit in the next tutorial section. It includes the SPICE
netlist statements of the circuit components and the simulation commands. The following is a line-by-line
description of this circuit file:
Line 1 Title line. This is also the default simulation data plot title.
Line 2 Comment line.
Line 3 An independent (ideal) voltage source used as a power supply.
Line 4 An independent voltage source, which provides the time varying input signal to the circuit.
Lines 5-9 Describes the rest of the components in the circuit.
Line 11 Defines the transistor model NDRV.
Line 13 Specifies a transient analysis with a time step of 10ns and duration of 130ns.
Line 14 Specifies that a tabular output of the listed variables be printed to the output file.
Line 15 Saves all circuit voltages, currents and digital node states in a binary file.
Line 16 A post-processor directive that tells TopView to automatically plot the listed variables when
the simulation is completed.
See Chapter 1 of the Simulator Reference manual for detailed description and complete syntax rules.
SMALL SAMPLE CIRCUIT

* Circuit description
VCC VCC 0 5V ;Supply voltage
VIN IN 0 PULSE (0 4.5V 4ns 5ns 5ns 60ns) ;signal source
X1 IN A 7404 ;TTL inverter from digital library
R1 A 1 10K ;10K resistor
Q1 OUT 1 0 NDRV ;Bipolar transistor
R2 VCC OUT 1K ;1K resistor
COUT OUT 0 0.1PF ;0.1pF capacitor
* Device model
.MODEL NDRV NPN( BF=20 RB=100 TF=0.1ns CJC=2pF)
* Control statements
.TRAN 10ns 130ns ;do transient analysis
.PRINT TRAN/ALL V(IN) D(IN) D(A) V(OUT)
.PROBE ;save all circuit voltages and currents
#AUTOPLOT V(IN) D(IN) D(A) V(OUT) ;do autoplot
.END
Figure 2.2 Sample SPICE circuit file file
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RUNNING TOPSPICE
Figure 2.3 Small sample circuit schematic
2.14 Tutorial Session

In this tutorial session we will provide step-by-step instructions to create and complete the design project
for the small sample circuit shown in Fig. 2.3. We will draw the circuit schematic, define the device models
needed, specify the analysis commands, simulate the circuit and plot the results. All the files for this
sample project are available in the “\Examples” folder. The SPICE netlist for the circuit is also explained.
2.14.1 Drawing the Circuit

1. From the Launch TopSpice screen select New Circuit. Make sure the Open As Schematic option is
selected. Enter the design project filename SAMPLE and click OK. The Schematic Editor is invoked
with a blank sheet.
2. Select the Edit|Title block command. In the title line, enter the following title:
SMALL SAMPLE CIRCUIT
Click OK.
3. You can now start drawing the circuit. Select

Insert|Part|Symbol command. Select the “V
;voltage source” symbol from the symbol list, or
you can type “V” at the symbol name box, and
click OK. Place the red part outline approximately
one inch from the left margin and two inches from
the top and click. Immediately after placing the
part the same part will be redisplayed. Since we
don’t want to repeat this part, right click to cancel.
The program automatically assigns the part
reference name “V1”. This will be changed to
“VIN” later by editing its attributes.
4. The 7404 TTL inverter is a TopSpice model library

part. To place it, Select Insert|Part|TopSpice
Model Library command and place it
approximately as shown in the figure. The
program automatically assigns the part number Figure 2.4 Part attributes dialog
“7404” to it.
2-17
5. Repeat step 3 for the resistor R1 (“R” symbol) and transistor Q1 (“Q” symbol). Make sure the right
resistor pin end contacts the transistor base pin end.
6. For the resistor R2 and capacitor COUT we will use the “vertical” symbols: “RV” for the resistor and
“CV” for the capacitor. Although we could rotate the standard symbols, the vertical symbol shows the
attribute labels horizontally.
7. The parts attributes can now be specified or edited. Double-click on the R1 part. The “Part Attributes”
dialog box is displayed as shown in Fig. 2.4. In the “Value/name” box enter 10K (it can also be
specified as 10000 or 1E4). Click OK. Repeat for R2, but this time, enter 2K. For Q1 change the
model name, Q, assigned by the program as default, to NDRV. For the capacitor part we need to
change both the reference and value. Edit the entry in the “Reference” box to COUT. For value enter
0.1pF.
Figure 2.5 VIN PULSE source setup dialog for step 8
8. The voltage signal source part is a special case. Instead of the normal “Part Attributes” dialog, the
“Independent Source Setup” dialog is displayed. Change the entry in the “Reference name” box to
VIN. In the “TRANsient Spec” box select the PULSE radio button. This brings up the “PULSE Source
Setup” dialog. Fill the entries as shown in Fig. 2.5.
9. To add the VCC power rail symbol, select Insert|Power rail. On the “Add Power Rail” dialog, enter
the supply name, VCC, and its value 5V. Make sure the “positive” polarity option is checked.
10. Add all the ground symbols by selecting Insert|Ground.
11. The circuit is now ready to be wired. Select the Insert|Wire command. The cursor changes to the
wiring cursor shape. Click at the VIN top pin end point. Move to the X1 input pin end and click.
Repeat the procedure to wire the X1 output pin to the R1 left pin, and the Q1 collector pin to the
COUT top pin. After you are finished with the wiring, right click to exit the wiring mode.
12. The junction symbol (dot) at the point where the Q1 collector pin, R2 bottom pin and the wire to
COUT meet is automatically added by the program. This is only to give a visual indication of an
electrical connection.
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RUNNING TOPSPICE
13. Some of the nodes in the circuit needs to be labeled so they can be referenced in the simulation
setup commands. Select the Insert|Label node command. Enter the node name IN. Place the label
outline above the wire connecting VIN to X1 and click. You must place the label within 2 grid marks of
a wire or pin. To label the next node, click again anywhere on an empty spot on the schematic. Enter
the node name A and place it at the output of X1. Repeat for node name OUT and place it above the
wire connecting COUT.
2.14.2 Adding Device Models

Every active device and component requires a device model definition. The digital inverter 7404 is a
standard TTL library component. No model definition is needed for it because the simulator will
automatically search all the TopSpice model libraries. The Q1 model “NDRV” is not in the default model
libraries, hence we must add a model definition for it. Select the Simulation|Open User SPICE
Commands File command. The text editor is invoked with the file name SAMPLE.MIS. Type the
following model definition:
.MODEL NDRV NPN (BF=20 RB=100 TF=0.1ns CJC=2pF)
Select File|Exit when you are finished.
2.14.3 Simulation Setup

Before you can simulate the circuit, you need to specify the type of analysis you want to perform on the
circuit. For this example, we will perform a transient analysis. Select the Simulation|Setup command.
The “Simulation Setup” dialog is displayed. Check the enable box for Transient Analysis. The “Transient
Analysis Setup” dialog box pops up as shown in Fig. 2.6. In the “Step time” box enter 10ns. In the “Stop
time” box enter 130ns. Select OK when finished.
TopSpice does not save any simulation results unless output commands are specified. Check the enable
box for “Save Data”. On the “Save Setup” dialog make sure the “Save everything” is checked. Click OK.
This specifies that all the circuit variables will be saved to the binary output data file.
Figure 2.6 Simulation transient analysis setup dialog
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Figure 2.7 Auto plot setup
Next we want to specify to the TopView post-processor program to automatically plot some of the circuit
variables when the simulation is completed. Check the “Auto Plot” enable box. The “Auto Plot Graph
Setup” dialog is displayed. Click Add Plot to display the new plot setup dialog. In the
“Variable/expression list” box enter the following variable names:
V(IN) D(IN) D(A) V(OUT)
V(x) specifies a node voltage and D(x) specifies a digital node. For the node IN we can specify both an
analog voltage and digital outputs because this is an analog/digital interface node. Click OK on all open
dialogs.
2.14.4 Run Simulation

To simulate the circuit, select the Simulation|Run Simulation command. During the simulation,
TopSpice displays the simulation status information such as sweep voltage value or time, and the
elapsed time since the simulation started. After the simulation is successfully completed, the TopView
graphics post-processor is automatically invoked and the waveforms plotted as shown in Fig. 2.8.
The normal operating procedure is to close the plot window, exit the TopView program, after finishing
viewing the plot. Then, one can make any necessary changes to the circuit and repeat the simulation run.
However, if the TopView "auto close" option is enabled, the previous plot window is automatically closed
before plotting the next simulation run so there is no need to manually close the plot window.
If errors occur during the simulation (the most common are syntax errors), the simulation is aborted and
error messages are printed to the output file. The user has the option to run the Output File Browser,
which opens the output file and highlights the first error message.
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RUNNING TOPSPICE
Figure 2.8 TopView simulation results plot
2-21
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SCHEMATIC EDITOR
CHAPTER
3 INPUT/OUTPUT FILE EDITORS
3.1 Circuit Netlist File Editor

The TopSpice Circuit File Editor program is the SPICE netlist (text) file editor front-end for the TopSpice
simulator. It can be used to create and edit SPICE netlists, command or model files, or any other text file.
It operates much like any other Windows text editor, but with added features that makes it convenient to
perform all the design functions:
• Analysis menu commands integrate all the simulation setup, run and plot functions.
• SPICE syntax color highlighting.
• Simulation Setup dialog screen.
• Model library utility functions.
• Toolbar “Go” button runs simulation with a single mouse click.
• “Bookmarking” function.
• Unlimited file sizes (limited by available system resources).
• Simulation session original circuit file backup/restore option.
• TopSpice syntax and commands help.
Figure 3.1 TopSpice Circuit File Editor screen
3-1
3.1.1 User Interface

The Circuit File Editor uses the Microsoft Windows graphical user interface. All commands are invoked
through pull-down and pop-up (dialog box) menus, or the toolbar icons. On dialog text edit or entry boxes,
the standard Windows shortcut keys can be used to perform text editing functions (cut, copy and paste)
to, and from, the Windows clipboard. If you are not familiar with the Windows interface, we recommend
that you review the Windows documentation.
The mouse wheel, if available, is supported to perform vertical scrolling, and the right mouse click brings
up the “quick” popup menu to conveniently access commonly used commands.
3.1.1.1 Function and Shortcut Keys

Many of the menu functions have matching keyboard “shortcut keys”, that when pressed is equivalent to
selecting the menu item. The following is a list of the available keys:
Key Menu Item/Command

F1 Help
F2 View|More Bookmarks|Next Bookmark
F2+Shift View|More Bookmarks|Previous Bookmark
F2+Ctrl View|More Bookmarks|Toggle Bookmark
F3 Edit|Find Next
F3+Shift Edit|Find Previous
F6 Next Window
F6+Shift Previous Window
F8 Simulation|Setup
F9 Simulation|Run Simulation
F11 Simulation|Plot Data
F12 Simulation|Browse output file (.out)
Backspace+Ctrl Delete word left
Backspace+Alt Edit|Undo
Delete Edit|Delete
Delete+Shift Edit|Cut
End+Ctrl Go to end of file
End+Shift Select text to end of line
Home+Ctrl Go to start of file
Home+Shift Select text to start of line
Insert Toggle insert/overstrike typing mode
Insert+Shift Edit|Paste
Insert+Ctrl Edit|Copy
PageDown+Shift Select text next page
PageUp+Shift Select text previous page
←+Ctrl Go to word left
→+Ctrl Go to word right
←+Shift Select text left
→+Shift Select text right
↑+Shift Select text previous line
↓+Shift Select text next line
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SCHEMATIC EDITOR
A+Ctrl Edit|Select All

C+Ctrl Edit|Copy
F+Ctrl Edit|Find
H+Ctrl Edit|Replace
N+Ctrl File|New
O+Ctrl File|Open
P+Ctrl File|Print
S+Ctrl File|Save
V+Ctrl Edit|Paste
X+Ctrl Edit|Cut
X+Alt File|Exit
Y+Ctrl Edit|Redo
Z+Ctrl Edit|Undo
Z+Alt Simulation|Run Simulation (“zip” mode)
0+Alt View|Bookmarks|Go to Bookmark 0
0+Ctrl View|Bookmarks|Toggle Bookmark 0
The following is a list of shortcut keys sorted by command:
Command Shortcut Key

Go to word left ←+Ctrl
Go to word right →+Ctrl
Go to end of file End+Ctrl
Go to start of file Home+Ctrl
Select text left ←+Shift
Select text right →+Shift
Select text previous line ↑+Shift
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Select text next line ↓+Shift

Select text to end of line End+Shift
Select text to start of line Home+Shift
Select text next page PageDown+Shift
Select text previous page PageUp+Shift
File|Exit Alt+X
File|New Ctrl+N
File|Open Ctrl+O
File|Print Ctrl+P
File|Save Ctrl+S
Edit|Copy Ctrl+C
Edit|Copy Ctrl+Insert
Edit|Cut Ctrl+X
Edit|Cut Shift+Delete
Edit|Delete Delete
Edit|Find Ctrl+F
Edit|Find Next F3
Edit|Find Previous Shift+F3
Edit|Paste Shift+Insert
Edit|Paste Ctrl+V
Edit|Redo Ctrl+Y
Edit|Replace Ctrl+H
Edit|Select All Ctrl+A
Edit|Undo Alt+Backspace
Edit|Undo Ctrl+Z
View|Bookmarks|Go to Bookmark 0 Alt+0
View|Bookmarks|Toggle Bookmark 0 Ctrl+0
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SCHEMATIC EDITOR
View|More Bookmarks|Next Bookmark F2

View|More Bookmarks|Previous Bookmark Shift+F2
View|More Bookmarks|Toggle Bookmark Ctrl+F2
Simulation|Setup F8
Simulation|Run Simulation F9
Simulation|Plot Data F11
Simulation|Browse Output File F12
Simulation|Run Simulation (“zip” mode) Alt+Z
3.1.2 Toolbar Functions

Toolbar buttons provide shortcuts for initiating commonly used menu commands. Choosing a toolbar
button evokes the same response as would selecting the corresponding menu item. To display the
"tooltip" text description of a toolbar button function, hover the mouse over the button.
Icon Function Performed

File commands: New, Open, Save, Print
Edit commands: Cut, Copy, Paste
Edit commands: Undo, Redo
Edit commands: Find, Find Next, Find Previous, Replace
View|Bookmark commands: Toggle Bookmark, Next Bookmark, Previous

Bookmark, Clear All Bookmarks
Run Simulation command
Help|Simulator Reference command
3.1.3 Menu Commands

3.1.3.1 File Menu
Command Function
New Opens a new empty edit window.
Open Opens another file in a new edit window. In addition to SPICE .CIR files, it
supports the following file types: "HSPICE netlist (*.sp)", "Miscellaneous
commands (*.mis)", "Model files (*.mod)", "Library files (*.lib)", "Text files (*.txt)".
Close Closes the current edit window.
Save Saves changes to the current edit window file.
Save as Saves the current edit window file under a different name.
Print Prints the current edit window file.
Print preview Shows preview of the printed output.
Page setup Sets page formatting options.
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Printer setup Displays printer driver options menu.

Exit Saves all the open files and exits the program.
3.1.3.2 Edit Menu

Command Function
Undo Undoes the last edit operation.
Redo Restores the last “undo” operation.
Cut Cuts the current selection and saves it to the paste buffer.
Copy Copies the current selection to the paste buffer.
Paste Pastes the contents of the paste buffer.
Delete Deletes the current selection.
Select all Selects all the text.
Find Searches for a text string.
Find next Repeats last search forward.
Find previous Repeats last search backward.
Replace Replaces a text string for another.
Read only Toggles editor read-only mode (browsing only).
3.1.3.3 View Menu

Command Function
Toolbar If set, displays toolbar.
Status bar If set, displays status bar.
Bookmarks The Clear All bookmarks command clears all the numbered bookmarks. The
Bookmark 0 thru Bookmark 9 commands set or clear the corresponding
numbered bookmarks.
Go to bookmark Goes to the corresponding numbered bookmark if set.
More bookmarks The Toggle bookmark command sets or clears a bookmark. The Next bookmark
command jumps to the next bookmark. The Previous bookmark command jumps
to the previous bookmark. The Clear all bookmarks command clears all the
bookmarks except for numbered bookmarks.
3.1.3.4 Simulation Menu

Command Function
Run simulation Invokes the simulator and simulates the circuit file.
Simulator engine option Selects one of the following simulator programs to be used to
run simulations: TopSpice (default), XSPICE Option, LTspice
simulator, other simulator (user provided simulator). The
selected option is saved between sessions.
Plot data (post-processor) Opens the TopView post-processor and plots the simulation
results. You don’t need to rerun the simulation to plot the
previous simulation run data.
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SCHEMATIC EDITOR
Browse output file Allows you to browse the simulation output listing (.out) file.
Open misc. SPICE commands file Opens the miscellaneous user SPICE commands (.mis) file.
3.1.3.5 Tools Menu

Command Function
Model library database Invokes the TopSpice Model Database, which allows you to browse and
search all the models in the TopSpice model libraries, get detailed
information about a model, and extract a model SPICE code.
Model utilities Commands to support model file functions:
Encrypt model Encrypts a model file so others cannot read its

file contents. See User’s Guide Chapter 4.
Open model file Opens a model file. This offers a convenient way to
examine a model file. You can also copy and paste a
model definition from a model file to your SPICE circuit
file or the “users SPICE commands” file.
Search model Searches a model library file for a model.
library file
Restore original file Restores the file contents from the backup created at the start of the editing
session. Any changes saved during the editing session are discarded.
Write flat netlist Writes a "flat netlist" file for the open schematic circuit. This command
expands any subcircuit calls to produce a SPICE netlist without hierarchical
blocks. The flat netlist file has the extension ".FLAT.CIR".
Calculator Invokes the Windows calculator program.
3.1.3.6 Window Menu

Command Function
New window Opens a new window for the current file. This is useful when you need to view
different portions of the same file simultaneously. Any changes to the file are
applied to all the open windows for the file. When the file is closed all the
windows for the file are closed.
Cascade Cascades all the open edit windows so that all the title bars are visible.
Tile Displays all the open edit windows in a tile arrangement.
Arrange icons Arranges the open document windows as icons.
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3.1.3.7 Help Menu

Command Function
Editor help Displays Circuit File Editor help PDF document.
Simulator reference Displays Simulator Reference PDF manual.
User’s Guide Displays TopSpice User’s Guide PDF manual.
Support services Displays the product support policies and contact information.
Email support request Opens your system default email client program with a message containing
your TopSpice product details and addressed to Penzar Development
support, the user must add the request message and send it.
About Displays information about this program and product including serial number.
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SCHEMATIC EDITOR
3.1.4 Operation
The Circuit File Editor is automatically loaded when you select New Circuit or Open Last Project from
the TopSpice launch screen if the “Open As” “SPICE circuit (text) file” option is selected. It is also invoked
whenever you open a previously saved circuit netlist file using Open Saved SPICE (text) File button.
You can directly open the Circuit File Editor from the “TopSpice 8 Apps” window, which can be opened
using the Apps button on the TopSpice launch screen or Apps icon/tile on the Start menu.
You can also open a circuit netlist .CIR file with the Circuit File Editor from Windows Explorer.
For a new circuit a blank edit window is opened with the file name “untitled”. You should select the
File|Save as command and specify the desired file name before exiting, or performing any Analysis
menu commands. The Circuit File Editor text editing operations are similar to that of most other Windows
text editors such as Notepad.
When you are finished, select the File|Exit menu command. This command saves any changes to all the
open files and exits the program.
3.1.5 Multiple Open Files

You can open and display multiple edit windows, thereby editing multiple files. To open another edit
window, select the File|Open or File|New command.
If there are more than one circuit file open, all the Analysis commands apply only to the current circuit file
edit window or the last circuit file edit window that was active.
3.1.6 Simulation
To run a simulation, either click on the “Go” (green traffic light) toolbar icon, select the Simulation|Run
simulation menu command, or use the “F10” keyboard shortcut. To browse the simulation output file,
select the Simulation|Browse output file menu command.
Any changes to the circuit file are automatically saved every time the Run simulation command is
performed. The Tools|Restore original file menu command allows you to restore the circuit file to the
original state from the backup created when the file was opened the first time, regardless of any changes
saved during the session. This feature is useful when you want to try several changes to the circuit but
you decide to go back to the original circuit. Note: after the file is restored there is no way to recover the
changes you made during the session.
3.1.7 Syntax Highlighting

The Circuit File Editor syntax color highlighting feature applies different text colors to different SPICE
syntax elements. The following highlight colors are used:
Color Syntax Element

Blue Commands (starts with ".")
Cyan Post-processor directive statements (lines starting with "#")
Dark blue Keywords
Green Comments
Magenta Numbers
Red Expressions
The colors are not user selectable.
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3.1.8 Bookmarks
A bookmark allows you to mark a specific line in the file and then jump to the bookmarked line from
anywhere in the file using the "Go to bookmark" command. Two types of bookmarks are available: ten
numbered bookmarks (from 0 to 9) and generic bookmarks (unlimited). Bookmarks are not saved
between editing sessions.
Numbered bookmarks allow you to select or jump to a specific bookmark. To add a numbered bookmark,
use the View|Bookmarks menu command and select the desired numbered bookmark. To jump to a
numbered bookmark, use the View|Go to bookmark menu command and select the desired bookmark.
To remove a numbered bookmark, use the View|Bookmarks menu command and select the desired
numbered bookmark. The command View|Bookmarks|Clear all bookmarks removes all numbered
bookmarks – it does not clear generic bookmarks.
With generic bookmarks you can only jump to the next or previous bookmark from the current caret
position. Generic bookmark functions can be accessed either using menu commands or toolbar icons. To
add a bookmark, use the View|More bookmarks|Toggle bookmark menu command. This command
can also be used to remove individual bookmarks. The View|More bookmarks|Next bookmark
command jumps to the next bookmark. The View|More bookmarks|Previous bookmark command
jumps to the previous bookmark. The View|More bookmarks|Clear all bookmarks command removes
all the generic bookmarks but not the numbered bookmarks.
3-10
SCHEMATIC EDITOR
Figure 2.10 TopSpice File Browser window
3.2 Output File Browser

The TopSpice File Browser program allows the user to browse the simulation output listing file (filename
extension “.out”). It is automatically invoked by the Simulation|Browse output file menu command and
simulator to open the output file. The File Browser is actually a text editor and it can be used to edit the
output file if you need to. It operates much like any other Windows text editor with the following additional
features:
• Unlimited file size support (limited by available system resources).

• Automatic simulation error message display.
• Simulation warning and error message search.
• E-mail file.
• Insert OLE objects.
3.2.1 User Interface

The TopSpice File Browser uses the Microsoft Windows graphical user interface. All commands are
invoked through pull-down and pop-up (dialog box) menus, or the toolbar icons. If you are not familiar
with the Windows interface, we recommend that you review the Windows documentation.
3.2.1.1 Function and Shortcut Keys

Many of the menu functions have matching keyboard “shortcut keys”, that when pressed is equivalent to
selecting the menu item. The following is a list of the available keys:
Key Menu Item/Command

F1 Help
F3 Edit|Find Next
F9 Tool|Find next error message
F10 Tool|Find Next warning message
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Backspace+ Alt Edit|Undo

Delete Edit|Clear
Delete+Shift Edit|Cut
End+Ctrl Go to end of file
End+Shift Select text to end of line
Home+Ctrl Go to start of file
Home+Shift Select text to start of line
Insert+Ctrl Edit|Copy
Insert+ Shift Edit|Paste
PageDown+Shift Select text next page
PageUp+Shift Select text previous page
←+Ctrl Go to word left
→+Ctrl Go to word right
←+Shift Select text left
→+Shift Select text right
↑+Shift Select text previous line
↓+Shift Select text next line
A+Ctrl Edit|Select All
B+Ctrl Bold font
C+Ctrl Edit|Copy
E+Ctrl Center paragraph
F+Ctrl Edit|Find
H+Ctrl Edit|Replace
I+Ctrl Italic font
L+Ctrl Left justify paragraph
N+Ctrl File|New
O+Ctrl File|Open
P+Ctrl File|Print
R+Ctrl Right justify paragraph
S+Ctrl File|Save
U+Ctrl Underline font
V+Ctrl Edit|Paste
X+Alt File|Exit
X+Ctrl Edit|Cut
Y+Ctrl Edit|Redo
Z+Ctrl Edit|Undo
The following is a list of shortcut keys sorted by commands:
Command Key
Help F1
Bold font B+Ctrl
Center paragraph E+Ctrl
Italic font I+Ctrl
Left justify paragraph L+Ctrl
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SCHEMATIC EDITOR
Right justify paragraph R+Ctrl

Underline font U+Ctrl
Go to word left ←+Ctrl
Go to word right →+Ctrl
Go to end of file End+Ctrl
Go to start of file Home+Ctrl
Select text left ←+Shift
Select text right →+Shift
Select text previous line ↑+Shift
Select text next line ↓+Shift
Select text to end of line End+Shift
Select text to start of line Home+Shift
Select text next page PageDown+Shift
Select text previous page PageUp+Shift
File|Exit X+Alt
File|New N+Ctrl
File|Open O+Ctrl
File|Print P+Ctrl
File|Save S+Ctrl
Edit|Copy C+Ctrl
Edit|Copy Insert+Ctrl
Edit|Cut X+Ctrl
Edit|Cut Delete+Shift
Edit|Clear Delete
Edit|Find F+Ctrl
Edit|Find Next F3
Edit|Paste Insert+Shift
Edit|Paste V+Ctrl
Edit|Redo Y+Ctrl
Edit|Replace H+Ctrl
Edit|Select All A+Ctrl
Edit|Undo Backspace+Alt
Edit|Undo Z+Ctrl
Tool|Find Next Error Message F9
Tool|Find Next Warning Message F10
3.2.2 Menu Commands
3.2.2.1 File Menu

Command Function
New Opens a new empty edit window.
Open Opens an existing file.
Save Saves changes to the current open file.
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Save as Allows you to save the current open file under a different name.
Print Prints the current open file.
Print preview Allows you to preview the printed output.
Page setup Sets page formatting options.
Send Invokes the system e-mail client program to e-mail the file.
Exit Saves changes and exits the program.
3.2.2.2 Edit Menu

Command Function
Undo Undoes the last edit operation.
Cut Cuts the current selection and saves it to the paste buffer.
Copy Copies the current selection to the paste buffer.
Paste Pastes the contents of the paste buffer.
Paste special Pastes other Windows clipboard objects to file.
Clear Deletes the current selection.
Select all Selects everything.
Find Allows you to search for a text string.
Find next Repeats last search forward.
Find previous Repeats last search backward.
Replace Replaces a text string for another.
Links Allows you to edit OLE object links.
Object Allows you to edit object.
3.2.2.3 View Menu

Command Function
Toolbar If set, displays toolbar.
Format bar If set, displays format bar.
Ruler If set, displays ruler.
Status bar If set, displays status bar.
Options Displays the view options dialog menu.
3.2.2.4 Insert Menu

Command Function
Date and time Inserts date and time text.
Object Inserts OLE object.
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SCHEMATIC EDITOR
3.2.2.5 Format Menu

Command Function
Font Allows you to set the text font options.
Bullet style Sets bullet style.
Paragraph Allows you to set the paragraph formatting options.
Tabs Allows you to set tabs.
3.2.2.6 Tools Menu

Command Function
Find next error message Finds and displays the next simulation error message.
Find next warning message Finds and displays the next simulation warning message.
3.2.2.7 Help Menu

Command Function
Contents Displays File Browser help topics.
About Displays information about this program.
3.2.3 Operation
The TopSpice File Browser is automatically loaded when you select the Simulation|Browse output file
menu command from the Schematic Editor or Circuit File Editor, or the TopView View|Browse output
file command, to open the simulation output file. It is also invoked by the simulator program if the
simulation terminates with errors.
If the simulation output file contains simulation error messages, the TopSpice File Browser automatically
displays the line with the first error message in the file. To display the next message, select the
Tools|Show next error message menu command. The Tools|Show next warning message menu
command can be used to find and display simulation warning messages.
The File Browser text editing operations are similar to that of most other Windows text editors such as
Notepad.
When you are finished browsing, select the File|Exit menu command. This command also saves any
changes to the file and exits the program.
3.2.4 E-mail Output File

The File Browser File|Send menu command opens the system default e-mail client program send
message window with the current open output file as an attachment. If you need to contact Penzar
Development Technical Support (e-mail address: support@penzar.com) regarding simulation problems or
errors, this is a convenient way to e-mail the output file.
If possible you should always e-mail the simulation output file when requesting support for simulation
problems or errors. In most cases, the output file contains all the information, including the SPICE netlist,
needed to resolve problems.
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3-16
SPICE DEVICES AND MODELS
CHAPTER
4 SPICE DEVICES AND MODELS
4.1 Simulator Circuit Elements

The electrical components that make up a circuit are described using element statements. Each
component is specified by an element statement that contains the element name, the circuit nodes to
which the component terminals are connected, component value or model name, and any other
parameters that determine the electrical characteristics of the element. For passive components such as
resistors it is usually sufficient to specify a component value. For active components such as
semiconductor devices a device model definition is also needed.
In addition to passive and active devices, TopSpice includes many different types of controlled sources,
which can be used to implement behavioral block (black box) models of subsystems and components. All
the components may also be grouped into subcircuits to model complex devices or develop hierarchical
circuit descriptions. To power and drive the circuits, independent (ideal) sources are available for
specifying power supplies and signal sources. Many different types of sources are implemented in
TopSpice. By using one or more of these sources, almost any desired waveform function can be
generated.
The following table lists all the TopSpice simulator circuit elements:
Element Description
A XSPICE special function
B GaAs FET (same as J) / SPICE3 arbitrary dependent source
C capacitor
D diode
E voltage-controlled / behavioral modeling voltage source
F current-controlled current source
G voltage-controlled / behavioral modeling current source
H current-controlled voltage source
I independent current source
J JFET, GASFET or MESFET
K inductive coupling and magnetic core
L inductor
M MOSFET
O digital/analog interface
Q bipolar transistor (BJT)
R resistor
S switch (voltage-controlled)
T transmission line (ideal and lossy)
U digital device
V independent voltage source
X subcircuit (macromodel)
Z MESFET (same as J)
4-1
4.1.1 Passive Devices

The following passive devices are available:
Device Element Models/Options
Resistor (linear, behavioral) R R, RES

Capacitor (linear, nonlinear) C C, CAP, POLY, PWL, Q, TABLE
Ferroelectric capacitor C FECAP
Inductor (linear, nonlinear) L IND, POLY, PWL
Coupled inductor K
Magnetic core K CORE
Transmission line (ideal, lossy) T LTRA, TRN
Voltage-controlled switch S VSWITCH, SW
4.1.2 Independent Sources

The following independent (ideal) sources are available:
Source Element
Independent voltage source V
Independent current source I
4.1.3 Signal Sources

The following transient signal sources are available:
Function Description Elements
AM Amplitude modulated waveform V, I

EXP Damped exponential pulse V, I
FILE User data file V, I
NOISE Noise generator for .NOISE analysis I
PULSE Periodic or single pulsed waveform V, I
PWL Piece-wise linear (arbitrary) waveform V, I
RANDOM Random waveform V, I
SFAM Single frequency AM V, I
SFFM Single frequency FM V, I
SIN Damped sine wave V, I
4.1.4 Dependent Sources

The following dependent (controlled) sources are available:
Source Type Element

Voltage-controlled voltage source (linear, nonlinear) E
Current-controlled current source (linear, nonlinear) F
Voltage-controlled current source (linear, nonlinear) G
Current-controlled voltage source (linear, nonlinear) H
4-2
4.1.5 Special Function Sources

The following special function sources are available:
ADD add two voltages E

COMPFUN comparator function E
COMPINV Inverting comparator function E
DIVIDE divide two voltages E
LIMTER voltage limiter function E
MULTIPLY multiply two voltages E
OPAMP op amp function E
OTA operational transconductance amplifier G
POLY polynomial function E, F, G, H
POWER power (V x I) sum function E, G
SCHMITT Schmitt trigger function E
SCHMITTINV inverting Schmitt trigger function E
4.1.6 Analog Behavioral Modeling Sources

The following analog behavioral modeling sources are available:
FREQ frequency response table E, G

LAPLACE Laplace transform E, G
RESISTOR resistance expression G
TABLE look-up table E, G
VALUE expression transfer function E, G
4.1.7 Semiconductor Devices

The following semiconductor elements and device models are available:
Device Element Models
Diode D D
Junction FET (JFET) J NJF, PJF
GaAs FET J, B, Z GASFET
MESFET J, B, Z NMF, PMF
MOSFET M NMOS, PMOS, VDMOS
Bipolar junction transistor (BJT) Q NPN, PNP, HNPN, HPNP
4-3
4.1.8 Digital Devices

The digital element U implements the following digital primitive functions for logic simulation:
Function Description Model

ADD N-bit full adder UALU
AND AND gate with two or more inputs UGATE
BUF Buffer gate UGATE
BUF3 Tri-state buffer gate U3GATE
CLOCK Periodic stimulus source USTIM
COMP N-bit magnitude comparator UALU
COUNT N-bit universal counter UCOUNT
DATA Arbitrary waveform stimulus source USTIM
DEC N bits-to-N line decoder USEL
DFF Edge-triggered D flip-flop UEFF
DIVN Divide-by-N counter UCOUNT
DLATCH Gated D flip-flop (latch) UGFF
INV Inverter UGATE
JKFF Edge-triggered JK flip-flop UEFF
MUX One of n-bit multiplexer USEL
NAND NAND gate with two or more inputs UGATE
NOR NOR gate with two or more inputs UGATE
OR OR gate with two or more inputs UGATE
PARITY Parity generator/checker UALU
PENC N-line priority encoder USEL
PSREG N-bit universal shift register USREG
PULSE Pulse generator/multivibrator UPULSE
RAM Static random-access memory URAM
ROM Read-only memory UROM
RSFF Gated RS flip-flop UGFF
SREG N-bit shift register (serial in/parallel out) USREG
SRFF Gated SR flip-flop UGFF
SRLATCH Gated SR AND-OR flip-flop latch UGFF
SREGP N-bit parallel in/serial out shift register USREG
XOR Exclusive OR with two or more inputs UGATE
XNOR Exclusive NOR with two or more inputs UGATE
The following digital stimulus generators are available to provide digital input:
Function Description
CLOCK Generates periodic digital data
DATA Generates arbitrary digital data
4.1.9 Analog/Digital Interfaces

The analog/digital interface element O is implemented in TopSpice to perform the conversion between
analog and digital signals during mixed-mode simulations. This element is automatically inserted by
TopSpice at any circuit node with both analog and digital connections.
The following analog/digital interface functions are available:
4-4
ATOD Converts analog voltages to digital states
DTOA Converts digital states to analog voltages
4.2 Device Models

Device models allow the user to define devices with unique characteristics by specifying a set of model
parameter values once. Then these devices can be used throughout the circuit description by only
referencing the appropriate device model names. The .MODEL statement is used for this purpose.
By using the library search feature in TopSpice, predefined device models can be placed in library files.
Then TopSpice will automatically search the library files and insert the model definitions into the circuit
description file. TopSpice default library contains the models for many common off-the-self analog
discrete elements. TopSpice is also compatible with other vendor's SPICE libraries which adhere to the
U.C. Berkeley SPICE syntax.
To determine the exact effect of a device model parameter, you may need to refer to its device model
equations. Accurate device modeling, especially for transient and high frequency analyses, requires
specialized skills and detailed device characteristics data.
4.2.1 TopSpice Built-in Models

Model Description
ATOD analog/digital interface
C capacitor model
CAP capacitor model
CORE nonlinear magnetic core
D diode (levels 1 and 3)
DTOA digital/analog interface
FECAP ferroelectric capacitor
GASFET GaAs FET (levels 1, 2, 3 and 6)
HNPN HBT npn
HPNP HBT pnp
IND inductor model
LTRA lossy transmission line
NJF n-channel JFET
NMF n-channel MESFET
NMOS n-channel MOSFET (levels 1, 2, 3, 7, 8, 44, 49, 53, 55)
NPN npn BJT (levels 1 and 4)
PJF p-channel JFET
PMF p-channel MESFET
PMOS p-channel MOSFET (levels 1, 2, 3, 7, 8, 44, 49, 53, 55)
PNP pnp BJT (levels 1 and 4)
R resistor model
RES resistor model
SW voltage-controlled switch
U3GATE tri-state gate
UALU ALU function
UCOUNT counter
UEFF edge-triggered flip-flop
UGATE digital gate
UGFF gated flip-flop
UIO analog/digital interface
UMUX digital multiplexer (obsolete)
4-5
UPULSE digital pulse generator

URAM RAM memory
UROM ROM memory
USEL digital selector
USREG shift register
USTIM digital stimulus generator
VDMOS vertical double diffused MOSFET (LTspice compatible)
VSWITCH voltage-controlled switch
4.3 Subcircuits
Subcircuits allow the creation of reusable circuit cells (functional blocks) and hierarchical circuit
descriptions. SPICE subcircuits are equivalent to subroutines in computer programming languages. They
are often referred to as "macro models". Subcircuits offer several advantages. By placing a block of the
circuit used more than once into a subcircuit definition, it can be added to the circuit many times by simply
referencing the subcircuit. This saves labor and makes the circuit netlist (or schematic) more compact and
easier to read. Subcircuits also allow the user to describe the circuit using a structured and hierarchical
approach by dividing the circuit into functional blocks. Another very powerful use for subcircuits is for
creating library files of common macro models, standard parts and reusable cells.
For large circuit descriptions, you can divide the circuit into several subcircuits and save them in separate
files. Then you can use the .INC or .LIB statement in TopSpice to include these files into your main circuit
file. Frequently used circuit functions can be defined in subcircuits and added to library files. TopSpice will
automatically add the library definitions prior to the simulation. TopSpice also offers the capability to pass
parameters to subcircuits to customize each instance of a subcircuit.
Subcircuit definitions are started by using the .SUBCKT statement, where the subcircuit name, terminal
nodes and optional parameters are listed, and ending with the .ENDS statement. The subcircuit definition
netlist in between can only contain device element, .MODEL and .PARAM statements. No other
command statements are allowed. Nested subcircuit definitions are allowed. However, a subcircuit
defined inside another subcircuit definition is accessible only in the subcircuit definition containing it.
For example,
.SUBCKT OUTPUT 1 2 3
Q1 2 10 0 NOUT
Q2 2 11 3 POUT
X1 1 3 10 11 DRIVER
.
.
.SUBCKT DRIVER 1 2 3 4
.
.
.ENDS DRIVER
.
.MODEL NOUT NPN (BF=50)
.ENDS
In the above example, the subcircuit definition DRIVER and the device model NOUT are local to the
subcircuit OUTPUT and they are not accessible outside of it. Note that any .ENDS statement terminating
a nested subcircuit definition should contain the name of the subcircuit or the entire subcircuit definition
will be terminated.
To add a subcircuit, use the subcircuit instance call element, X, statement. For example,
X1 21 40 2 OUTPUT
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The above line creates an instance (calls) the subcircuit defined in the previous example. The nodes are
mapped into the external nodes defined in the subcircuit definition by their order. The node "2" in the
above subcircuit call will map to node "3" in the subcircuit definition.
The relative position of the subcircuit definitions and calls are irrelevant. Subcircuit calls can precede their
definitions and vice versa. All node, element and model names inside a subcircuit block are local to the
subcircuit and do not conflict with identical names in other sections of the circuit.
Subcircuits can also be customized for each instance by defining and passing argument parameters. For
example,
X1 2 1 5 AMPLIFIER PARAMS: GAIN=50 RINPUT=15K

.SUBCKT AMPLIFIER 1 2 3 PARAMS: GAIN=10 RINPUT=1K
Subcircuits are meaningful in the context of the input file. Before actually performing the simulation,
SPICE creates a flat netlist by expanding all subcircuit calls into the actual subcircuit definitions. Hence,
the amount of memory required to simulate the same circuit with or without using subcircuits about the
same (subcircuits increases memory usage slightly).
4.4 Simulation Models

In addition to the circuit netlist, a complete SPICE circuit file must include any necessary simulation
models. A schematic project can include the following types of simulation models:
Built-in device models Device models directly implemented in the simulator program code. They
include semiconductor devices such as diodes and transistors, several other
basic analog devices and digital primitives. They can be customized to fit
specific devices by specifying the model parameters values on a .MODEL
statement. See the Simulator Reference manual for complete list and details.
Macromodels Models for more complex devices, such as op amps, specified using SPICE
subcircuit definitions.
TopSpice library models TopSpice includes an extensive set of device models organized in libraries.
They include standard commercial parts, component vendor supplied models
and other devices. These libraries are encoded in a binary format. To
examine a model netlist, perform searches of the model libraries or browse
the libraries, use the Tools|Model Library Database command. If the
Schematic Editor Insert|Part|TopSpice Library Model command is used to
place the library part, all the necessary model link commands are added by
the program.
User parts A user part encapsulates a SPICE model and its matching schematic symbol
into a single file. The Schematic Editor Insert|Part|User Part command is
used to place a user part. Users can create, import or edit user parts using
the Tools|User Part command utility functions.
Built-in device models and macro models can be included to a schematic circuit project using one of the
following methods:
1. The user can directly enter or "copy and paste" a model definition using the Simulation|Open User
SPICE Commands File command. Simple .MODEL statements can even be placed directly on the
schematic drawing using a text object.
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Figure 4.1 Project model links definition menu
2. “Links” to model files or library files may be added using the Project|Add/Edit Model Links
command – see next section for more information on using model libraries and files.
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4.5 Model Libraries and Files

A model library is a file that contains the SPICE code, or statements, for one or more device models. If a
file contains only one model it is usually called a model file. Model libraries and files are supplied by many
part vendors, IC foundries and other third parties, or they can be created by the user. TopSpice also
includes an extensive set of model libraries. The simulator automatically searches the library files if the
circuit file contains any undefined subcircuits or device models.
TopSpice supports the following types of model libraries and files:
SPICE libraries The standard SPICE model library is a text file that includes the SPICE code for
one or more device models. The industry convention is to use the filename
extension ".LIB" for SPICE model library files. The user can open or create a library
file using any text editor.
Model files A SPICE model file is a text file that contains the SPICE code for one device
model. There is no standard filename extension for model files but some of the
commonly used ones are: .MOD, .SUB, .TXT, .CIR and .SPI. The .INC command is
normally used to include model files in a SPICE netlist..
Vendor libraries Most component vendors provide SPICE models for their parts either as standard
library files or model files. Many of these models are also included in the TopSpice
model libraries.
HSPICE libraries The HSPICE simulator uses a special library format. Many IC foundries provide
their process model libraries in this format. For more information on working with
HSPICE libraries see Sec. 4.8.
TopSpice libraries TopSpice includes an extensive set of device models organized in libraries. They
include standard commercial parts, component vendor supplied models and other
devices. These are not standard SPICE library files. Instead, they are encoded in a
binary format. To examine a model netlist, perform searches of the model libraries
or browse the libraries, use the Tools|Model Library Database command. If the
Insert|Part command Model Library Part function is used to place the library part,
all the necessary model link commands are added by the program – see Sec. 4.7.
All model libraries and files can contain the following types of models:
Built-in device models Device models directly implemented in the simulator program code. They
include semiconductor devices such as diodes and transistors, several other
basic analog devices and digital primitives. They can be customized to fit
specific devices by specifying the model parameters values on a .MODEL
statement. See the Simulator Reference manual for complete list and details.
Macromodels Models for more complex devices, such as an op amp, specified using SPICE
subcircuit definitions (macros). A subcircuit model code consists of multiple
SPICE statements which are bracketed by the following statements:
.SUBCKT name <node list>

.
.ENDS [name]
When a circuit simulation uses device models that are not defined in the circuit file, the simulator
automatically performs a library search in the following sequence:
1. User specified libraries if any.
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2. TopSpice Model Libraries Database.
3. The default library file DEFAULT.LIB.
The default model library file DEFAULT.LIB contains "default" model definitions for all the TopSpice
primitive device models to match the Schematic Editor default symbols. This is a standard SPICE library
file that can be open using any text editor program. However, the user should not modify it because it
could be overwritten if a program update is installed.
In general, model libraries do not include any schematic symbol information. However, schematic
symbols are provided for all the parts in the TopSpice libraries. For other libraries, you must select one of
the available generic symbols, create a new symbol or modify an existing symbol to match the library
model. Most device models supplied by component vendors will match one of the generic symbols.
4.5.1 SPICE Model Libraries

The standard SPICE model library is a text file that includes the SPICE code for one or more device
models. The industry convention is to use the filename extension ".LIB" for SPICE model library files. The
user can open or create a library file using any text editor. Besides .MODEL statements and .SUBCKT
definitions, library files can contain .PARAM statements and comment lines. No other command
statements are allowed.
Model library files can also contain .LIB statements. By using nested library calls, one can include all the
necessary library files by simply calling one master library file. However, the search time increases
considerably for large library files and it may become unacceptably slow. To avoid this problem, only call
the libraries needed. One can easily remove and add libraries by "commenting" out the .LIB statements
from the master library file.
When performing a library search, the simulator accepts the first model with matching model name and
model type. If a library file contains multiple definitions for the same model name and type, only the first
definition is used. This also applies when multiple definitions for the same model are found in more than
one library file.
If the library file name specified does not include a directory path, TopSpice looks for library files at the
following locations and in the following sequence:
1. Current working folder (where the circuit file is located).
2. "LibraryPath" folder, if defined.
3. TopSpice program installation folder.
LibraryPath is a parameter in the TopSpice configuration file TOPSPICE.INI, under the section
[TopSpice], which allows you to specify a directory path where model library files are located. The default
is the "\Lib" subfolder in the TopSpice folder. This allows you to keep your own or modified library files in
a separate folder from the TopSpice files or circuit files.
The library files are searched in the order listed in the input file. For example,
.LIB MYLIB.LIB
.LIB “\Program Files\TopSpice\Lib\XYZ.LIB”
.LIB E:\MODELS\XYZ.LIB
The default TopSpice library file DEFAULT.LIB is searched last. To force the default library to be
searched before, insert the .LIB statement:
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.LIB DEFAULT.LIB
To use a part in a model library, one must determine the model name and the model type (“.MODEL” or
“.SUBCKT”). If it is a .SUBCKT model, one also needs to determine the number and purpose of the
model interface nodes (pins). For most models, use the following procedure to determine this information:
1. The first step in using an unfamiliar model is to examine the model documentation, if any, and SPICE
code. This is necessary to determine the model type, .MODEL statement or subcircuit, and model
name. To examine the model code, use the Tools|Model Libraries|Open Model File command to
open the library file. It can also be open using any text editor.
2. Browse for the desired model or search for it using the Edit|Find command. Make a note of the exact
model name, which immediately follows either .MODEL or .SUBCKT on the first model statement.
Model names are case insensitive. Model names could be different from the device part numbers.
3. For built-in device (.MODEL) models, the device type follows the model name, such as PNP for a BJT
model or D for a diode. Symbols for all the built-in model device types are available in the default
symbol library. The node connections for a built-in model are determined by its matching SPICE
element syntax.
4. For subcircuit models, the model code needs to be examined to determine the number of model pins,
their functions and their order to be able to select the appropriate schematic symbol. The pin
information should be documented on most models. The pin node names are listed after the model
name on the .SUBCKT statement.
Once this model information is determined, see the next section for specific instructions for using model
library parts with the Schematic Editor. To use library models in a SPICE netlist file, follow this general
procedure:
1. If the model is a device .MODEL definition, one can use the standard device SPICE syntax in the
circuit file. For example, the SPICE device for a 2N3904 transistor model is the “Q” element. Hence,
add a BJT device statement such as
Q1 12 4 0 2N3904
2. If the model is a .SUBCKT definition (“X” type), then, you would need to look up the model code in the
library file. First open the file using the Tools|Model Utilities|Open Model File menu command, or a
text editor. For example, for the TTL 7400 2-input NAND gate model, the following model code is
found:
.SUBCKT 7400 1 2 3 ;node numbers

* 2-input NAND in in out ;pin names
U1 NAND 3 1 2 TTL TTLDA
.ENDS 7400
The first line is the .SUBCKT definition statement. The second line is a comment line documenting
the model and the pin functions. First, note that only one of the four gates in the 7400 chip is modeled
since for simulation purposes it is irrelevant which gate is used. Also, there is no supply or ground
nodes because this is a digital device model, and only logic simulation is performed with it.
To use the model, one needs to note the number of pins, the function of each pin and their order.
The “node numbers” of the pins are irrelevant – they are the internal subcircuit nodes and they don’t
usually have any significance. Then, add a subcircuit call statement such as
X22 a b q 7400
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3. A .LIB library command statement must be added to tell the simulator where to search for the model
as follows:
.LIB filename
filename must include the full path name if the library file is not located in the TopSpice directory or
“\Lib” subdirectory. For example, if you use the LM318 part model in the TI.LIB (Texas Instruments)
library, add the following statement:
.LIB TI.LIB
An alternate method is to manually "copy and paste" a model definition from the library file to the
circuit file. This avoids the library search time overhead.
4.5.2 Using Models as Schematic Parts

To use a SPICE simulation model in a model library or model file as a schematic part requires the
following model information:
1. The exact model name which could be different from the device part number. The model name is
required to produce the correct model use SPICE netlist statement.
2. The SPICE model type which can be either a built-in model (.MODEL) or a subcircuit model
(.SUBCKT). For built-in models, you must also determine the SPICE device type.
3. A matching schematic symbol for the model. SPICE model libraries and files do not include any
schematic symbol data. Instead, you must determine the required symbol from the model such as the
number of pins, their order and/or functions.
For most models, use the following procedure to determine the above information:
1. The first step in using an unfamiliar model is to examine the model documentation, if any, and its
SPICE code. This is necessary to determine the model type, .MODEL statement or subcircuit, and
model name. Model libraries and files are standard text files and they can be opened with any text
editor such as Windows Notepad. To examine the model code in a model library file, you can also
use the Tools|Model Utilities|Open Model File command.
2. Browse for the desired model or search for it using the text editor Edit|Find command. Make a note
of the exact model name, which immediately follows either .MODEL or .SUBCKT on the first model
netlist statement. SPICE model names are not case sensitive.
3. For simulator built-in device (.MODEL) models, the device type and schematic required symbol can
be determined by the model type, which follows the model name, such as PNP for a BJT model or D
for a diode. See sec. 4.2.1 or the Simulator Reference manual for the complete list of model types.
Symbols for all the built-in model device types are available in the default symbol library.
4. For subcircuit models, the model code needs to be examined to determine the number of model pins,
their functions and their order to be able to select the appropriate schematic symbol. The pin
information should be documented on most models. The pin node names are listed after the model
name on the .SUBCKT statement. You must be familiar with SPICE .SUBCKT syntax to be able to
perform this step. The syntax is documented in the Simulator Reference manual.
After the required model information has been determined, there are two methods for using a model as a
schematic part: create a user part or use a symbol with a model link. The preferred method is to create a
user part file. The user part encapsulates a model and its symbol information into a single object which is
saved to user part .TSP file. The user parts can be used in more than one schematic project and they can
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be easily organized by the user. For more information on creating and using user parts, see Chapter 3
sec. 3.21 “User Parts” and the next section “Import Model”.
However, if you only need to use a model in one schematic file, it could be more convenient to simply
place a symbol and add a model link for it as follows:
1. Select one of the generic symbols provided, or create a new symbol, that matches the model. Most
models will match one of the supplied generic symbols. For example, for most op amp models you
can use the XOPAMP symbol.
If there is no generic symbol that fits the model, one can modify an existing symbol or create a new
symbol either using the Tools|Symbol Utilities command or by manually editing a symbol definition
using a text editor. See sections 3.22 for more information on creating symbols.
2. Place the selected matching symbol using the Insert|Part command Part Symbol function.
3. Specify the model name as the part “Value/name" attribute instead of the actual part number (if they
are different).
4. The last step is to add a "model link" to tell the simulator either to include a model file or search a
specific library file for the model using one of the following methods: add a “global” model link; specify
the model link as a part attribute; manually add a SPICE link statement.
To add a “global” model link, follow this procedure:
a. Select the Project|Add/edit Model Links command.

b. Click the Browse button, and select the library or model file. Click Open.
c. Make sure the appropriate link option is selected: ".LIB" for library files; “.INC” for model files;
“.INC/MDB” for model database. The default option selection is based on the filename extension.
If the model file contains only one model, select the ".INC" option regardless of the filename
extension.
d. Click the Add button.
To specify the model link as a part attribute, follow this procedure:
a. Double click on the part symbol.

b. In the Model/Hierarchy File Link box, either enter the model filename or click the Open button to
select the library or model file.
c. Make sure the appropriate link option is selected: ".LIB" for library files; “.INC” for model files;
“MDB” for model database; “.HSC” for hierarchical blocks. The default option selection is based
on the filename extension. If the model file contains only one model, select the ".INC" option
regardless of the filename extension.
d. Click Ok.
To manually add the model link SPICE command statement, follow this procedure:
a. Select the Simulation|Open User SPICE Commands File command.

b. For a library file, add the following line to the miscellaneous SPICE commands file:
.LIB filename
For a model file, add the following line to the miscellaneous SPICE commands file:
.INC filename
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filename must include the full directory path name if the file is not located in the same folder as
the schematic or the TopSpice “\Lib” subfolder.
For all three methods, if the model is a HSPICE™ formatted library model, it requires the HSPICE™
style .LIB specification with the section name. If the library filename contains spaces or its filename
extension is not .LIB, it must be enclosed between single or double quotes. Section names cannot
contain spaces. Examples,
FETMODELS.LIB NFET1
"\my libraries\cmos1u.lib" nmostyp
'bicmos process.lib' pnpmin
4.5.3 Importing Models

The Schematic Editor Tools|User Part|Import Model menu command allows you to conveniently import
a SPICE model in a model file as a TopSpice user part. This command supports importing of models
defined using .MODEL and .SUBCKT (subcircuits) in a standard SPICE netlist format text file.
When the user opens a model file, the program reads the file and compiles a list of the SPICE models
found in the file. If there is more than one model, the user must select the desired model from the list.
Typically, a library file (with the filename extension .LIB) includes model definitions for multiple devices. A
model file includes the model definition for one device (regardless of the filename extension used).
However, the model for a single device, especially complex parts, could consist of multiple model
definitions, or “submodels”, in the same model file. The user must determine and select the correct “top
level” model definition for the device.
After selecting the desired model, if more than one, the user can specify the following import options:
Copy and save netlist in part file: copies the model netlist and saves it in the part file. The advantage of
this option is the model is no longer required to be distributed or kept with the user part file.
Link to model file: the appropriate model file link command (.LIB or .INC) is added. The advantage of this
option is that changes made to the models in the model file do not require changes to the user part file.
Include entire model file contents: copies the entire model file or adds the .INC link command. If the
model file contains one model, this option is the default. If the model file contains multiple model
definitions and this option is not selected, only the model netlist is copied or the .LIB link command is
added. Note: if the model for a single device consists of multiple model definitions, this option should be
selected.
Assign default symbol: assigns a matching schematic symbol to the model. For .MODEL definitions, the
matching SPICE device symbol is used. For subcircuits, a generic rectangular symbol with the matching
number of pins is used.
Use as pin names the subcircuit I/O nodes: for subcircuit models, the listed I/O nodes are used as the
symbol pin names.
Part name: the user can specify a part name different than the model name.
Click “Import” to create the user part for the imported model. The “Edit User Part” dialog is shown for the
newly created part. The user can make any necessary changes, such as changing the symbol, before
saving it.
S-parameters data files can also be imported as user parts. See sec. 7.5.1 for more details.
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Figure 4.4 TopSpice model libraries schematic part selection screen
4.6 TopSpice Model Libraries and Database

TopSpice includes an extensive set of simulation models organized in libraries. They include standard
commercial analog and digital parts, component vendor supplied models, and other devices and
functions. These libraries are not standard SPICE library files. Instead, they are indexed and encoded in a
binary format for quick search and extraction.
The Model Database tool is provided to examine model codes, perform searches or browse the libraries
contents. To run the Database, select the Tools|Model Library Database command from either the
Schematic Editor or Circuit File Editor, or open the "Model Libraries Database" icon in the TopSpice
program folder.
In general, to use a TopSpice model library part in a circuit, simply specify the model name as listed in the
library for the part on the appropriate schematic symbol or SPICE element statement. The simulator
automatically searches the libraries and retrieves the models used.
A schematic symbol library is included for the TopSpice libraries, which contains matching symbols for all
the parts in the libraries. To add a model library part on a schematic, use the Insert|Part command and
click the Model Library Part button. The last model selected by the user, if any, in the Model Database
is automatically selected at the start so it can be conveniently inserted by simply hitting the "Enter" key.
If the desired model part number is known, the most convenient way to find it is to enter the part number
in the "model" search box. You can also browse the libraries by selecting a category and a library within
the category (if more than one). The "ALL MODELS" category lists all the available models in all the
libraries.
The models available under each general category do not include the parts in the "Vendors" libraries. If
you cannot find a part or model under a specific category, you should always perform a search of all the
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libraries. For example, if you cannot find an op amp part, it most likely is found in one of the vendor
libraries.
The model code for a specific library part can also be inserted by adding a .INC/MDB command
statement either to a SPICE netlist or the "other SPICE commands" file. See Sec. 4.6.4 ".INC/MDB
Command" for more details.
Figure 4.5 TopSpice Model Libraries Database screen
4.6.1 Model Database Commands

File Menu
Command Function
Save Saves the selected model SPICE code to a model text file.
Save as Saves the selected model SPICE code to a model text file using a user specified
file name.
Export As User Part Creates a schematic user part for the selected model. The user part
encapsulates the model SPICE code and its schematic symbol in a single .TSP
file.
Print Prints the selected model SPICE code.
Printer setup Displays printer driver options menu.
Close If not saved, offers the option to save the model SPICE code for the selected
library part, and exits the program.
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Edit Menu
Command Function
Cut Cuts the model code text selection and saves it to the Windows clipboard paste buffer.
Copy Copies the model code text selection to the Windows clipboard paste buffer.
Paste Pastes the text in the Windows clipboard paste buffer to the model code window at the
current caret position.
View Menu
Command Function
Toolbar Hides or displays the toolbar.
Status bar Hides or displays the status bar.
Tools Menu
Command Function
Find model Searches for a name or text string matching model names or part numbers, device
type or description text. Exact match or partial match option.
Find next model Repeats the last search for the next instance.
4.6.2 Model Database Operation

To invoke the Model Database, select the Tools|Model Librariy Database command from either the
Schematic Editor or Circuit File Editor, or open the "Model Libraries Database" icon in the TopSpice
program folder. The Database screen is divided into three windows: libraries tree, model list and model
code.
The "libraries tree" window displays the available libraries and allows the user to select the desired library.
The models are categorized into libraries by device types, analog functions, logic families and vendor
supplied libraries. Note that models for a part might be found under multiple libraries. For example,
2N2222 transistor models are found under the BJT library and the Zetex vendor library. When the user
clicks on a library name, the library is selected, and the list of models available in the library is shown in
the "model list" window.
In addition to the list of models, the "model list" window displays for each model the following information:
part number, SPICE device type, schematic symbol, device type class and brief description. This
information allows the user to quickly pinpoint models that matches the desired part. When the user clicks
on a model line, the corresponding model is selected, and the model code retrieved from the library file
and displayed in the "model code" window.
The "model code" window is a text editor window. Standard Windows text editing shortcut keys can be
used to select and edit the model code text such as Ctrl+C (copy) and Ctrl+V (paste). One can modify
the model code or add documentation comments before saving it, or do a "copy and paste" operation to
insert the model code into another file.
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The selected model can be saved to a model text file. The default filename is the model name with the
filename extension ".MOD". For example, if the model 2N3904 is selected the default filename is
"2N3904.MOD". The model can be saved to a different filename using the File|Save As command. Once
a user specified filename is used, the same filename remains the default even if a different model is
selected. The model code is appended if saved to an existing file. Hence, multiple models can be saved
to the same file.
The selected model can be saved as a schematic user part using the File|Export As User Part
command. The user part encapsulates the model SPICE code and its schematic symbol in a single .TSP
file. This makes more convenient when the user needs to edit or customize a library model.
Because of the large number of parts in the libraries, the easiest way to search for and locate a part is to
use the Tools|Find command. Since most model names are the same as or contain the part numbers,
the first search should be for the part number. In the "Search name or text" box, enter either the full or
partial part number (the search is case insensitive). It is best not to check the "Exact match" option since
a model name can differ slightly from the part number. Model names often add extra characters before or
after the part number. Check the "Part number" and "Model name" "Match" options. To start the search,
click one of the find buttons. The Find button starts a new search and displays the first matching
instance, if any. The Find Next button searches for and displays the next instance, if any, either in the
same library or remaining libraries. The Find All button searches for and displays all the matches.
The parts in the "Vendor libraries" are not included in the list of the general category libraries. You should
always perform a general search if you cannot find a part in a specific library. This is especially true of
discrete semiconductor parts and common IC functions such as op amps.
The last model selected by the user, if any, is also automatically selected at the start of the "Select Model
Library Part" dialog for the Schematic Editor Insert|Part command Model Library Part function. The
model part can be conveniently placed on the schematic by simply hitting the "Enter" key.
Note: the user cannot modify or add models to the Model Database.
4.6.3 TopSpice Model Libraries Search

The simulator will search the TopSpice model libraries for any undefined models in the following order:
1. A/D mixed-mode models
2. Analog IC functions
• Comparators (see Vendor libraries for more)
• Operational amplifiers (see Vendor libraries for more)
• Voltage regulators (see Vendor libraries for more)
• Timers
• Other analog ICs
3. Analog other models
4. Bipolar transistors
• General
• Power
5. Digital
• CMOS 4000 series
• CMOS 74AC series
• CMOS 74ACT series
• CMOS 74AHC series
• CMOS 74AHCT series
• CMOS 74HC series
• CMOS 74HCT series
• CMOS 74LVC series
• CMOS 74LVC1G series
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• TTL 7400 series

• TTL 74ALS series
• TTL 74AS series
• TTL 74F series
• TTL 74LS series
• TTL 74S series
• ECL 10K series
• ECL 10HK series
• Other digital IC models
6. Diodes
• Rectifier and general use
• Bridges
• Current regulator
• Double diodes
• Schottky diodes
• Varactor
• Zener
• Other diodes
7. Electro-magnetic
• Transformers and magnetic cores
• Other electromagnetic parts
• Ferrites
8. JFET
9. MOSFET
• General
• Power
• VDMOS models
10. Opto-electronics
• LED, laser & other parts
• Optoisolators & optocouplers
11. Passive devices
12. RF components
13. Semiconductors other
• IGBT
• SCR
• Triac
• Miscellaneous
14. SMPS
• PWM controllers
• PWM controllers average models
• Basso average models
• Basso switched models
• Basso other models
• Bello models
• UCOPEC models
15. System blocks
16. Transmission lines and cables
17. Vacuum tubes
• Rectifier valves and other tube models
• Triodes
• Tetrodes and pentodes
18. Vendor libraries (in alphabetical order)
The search order is relevant only when there are multiple instances of a model (same model name and
device type) in more than one library. The simulator will use the first matching model found.
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4.6.4 .INC/MDB Command

The .INC/MDB command tells the simulator to extract and insert the SPICE code for a specific model
from the specified TopSpice Model library. The standard .INC command cannot be used for this purpose
because the TopSpice model libraries are stored in an encoded binary format. The exact syntax rules and
options for the command are detailed in the Simulator Reference manual.
For example, to insert the 2N2222 model found in the Zetex vendor library, specify the following
statement:
.INC/MDB ZETEX 2N2222
Without this statement, the simulator would use the 2N2222 model found in the BJT library which is first in
the library search list. The library name and model information for a part can be obtained using the "Model
Database" tool as described in the previous section.
Note: The simulator automatically searches the Model Database for any undefined models. Hence,
normally there is no need for the user to manually specify .INC/MDB statements. Also, if the
Schematic Editor Insert|Part command Model Library Part function is used, .INC/MDB
statements are automatically added.
4.7 HSPICE Libraries

The standard .LIB command does not work with HSPICE library files because of their special
formatting. Instead, the following HSPICE specific library statement must be used:
.LIB filename entryname
filename is the library file name. If the name contains spaces it must be enclosed between double or
single quotes.
entryname is the library section entry name you want to insert. A library section can include any number
of SPICE statements and subcircuits (see next subsection).
Examples:
.LIB MYMODELS.LIB MOSFET1

.LIB “C:\Lib\CMOS process.lib” nominalModels
The HSPICE .LIB command works differently than the standard SPICE .LIB command. Instead of
searching for a specific model, it simply inserts the contents of the specified section into the circuit netlist.
Hence, a HSPICE library section (macro) can contain any valid SPICE statements. This command only
works with HSPICE library files.
If no entryname is specified, TopSpice assumes it is a standard .LIB statement, which must be used for
all other model library files.
HSPICE library files with MOSFET model "binning" is supported.
When using HSPICE libraries, you should always inspect the entire library file and read any
documentation in the file, usually found at the start of the file. Many HSPICE libraries require that
certain sections are included in a specific order to properly use the models in the library.
4-20
Figure 4.6 HSPICE library section browsing and selection
When working from the Schematic Editor, you can specify HSPICE library sections using the Project |
Add/edit Model Links menu command. After selecting or entering the library filename, check the
"HSPICE library" option. This enables the "HSPICE library section" options.
You can either manually enter the section name, or use the "Browse" button to browse through the list of
the available sections in the library file as shown.
4.7.1 HSPICE Library File Definition

HSPICE libraries are text files consisting of one or more sections (macros). A library section can include
any valid SPICE statements such as commonly use commands, device models and subcircuits. To build
HSPICE compatible library files, the following statements must be used to start and end a library
section:
.LIB entryname
.ENDL [entryname]
entryname is the library section (macro) entry name you want to add.
Example:
.LIB NFET0
* Nominal device
.PARAM TCHAN=200 XL=-0.05
.MODEL NFET0 NMOS (KP=5E-3 VTO=2.3V TOX=TCHAN XL=XL)
.ENDL NFET0
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4.8 Include Files

The .INC statement allows you to insert the contents of the specified file in the input file. The contents are
inserted at the .INC statement position. This feature is commonly used to include model files but it is also
useful for breaking up large input files into several different files or to save a frequently used section of a
circuit description in a separate file.
An include file may contain any valid SPICE statement except the title and .END statements. Include files
may contain additional nested .INC statements.
For example,
.
.INC OUTSTAGE.INC
.
In the above example the contents of the file OUTSTAGE.INC are inserted at the location of the .INC
statement.
There is no default filename extension for include files, although .CIR, .INC, .TXT or .MOD (for models) is
commonly used.
If the include file name specified does not include a directory path, TopSpice looks for include files at the
following locations and in the following sequence:
1. Current working folder (where the circuit file is located).

2. "LibraryPath" folder, if defined.
3. TopSpice program installation folder.
4.9 Encrypted Model Files

The Schematic Editor and Circuit File Editor Tools|Model Utitilies|Encrypt Model File command
encrypts a model file so its contents cannot be read by others. The encrypted file can be used only by the
TopSpice simulator.
Note: there is no decryption function. An encrypted model file cannot be converted back to its original
plain text version. You should always keep the original plain text version.
When encrypting a file, a different filename should always be specified for the encrypted version output
file. By default, the encryption function will change the encrypted output filename extension to “.ts.mod” or
“.ts.lib”. However, you can use whatever filename extension you prefer.
There is no difference in using TopSpice encrypted model files. They can be specified on .INC and .LIB
statements. However, they cannot be used with the “import as user part” function.
Third party encrypted model files cannot be used by TopSpice, such as those encrypted for PSpice,
HSPICE and LTspice programs. These files can be used only by the programs used to encrypt them. For
example, a PSpice encrypted file can be used only by the PSpice simulator.
For LTspice encrypted models, you can try using the Simulation|Simulator Engine Option|LTspice
Simulator command.
4-22
SIMULATION
CHAPTER
5 SIMULATION
5.1 Introduction
TopSpice supports three circuit simulation analysis modes: DC, AC (frequency response) and transient
(time response). Each analysis mode also provides for one or more options to obtain derived results. To
help determine sensitivity to temperature and component variations, and optimize the design, TopSpice
offers several options for automatically repeating the simulations using different conditions. These
analysis options are discussed in the following sections.
The desired analyses may be specified by including command statements in the circuit file or from the
Simulation|Setup menu in the schematic or netlist editor.
5.1.1 TopSpice Simulator Commands

Command Description
.AC AC analysis (frequency sweep)
.ALIASES ignored (PSpice netlist compatibility only)
.ALTER alter circuit
.DC DC sweep
.DISTO distortion
.END end of circuit
.ENDL end library entry section
.ENDM end macro (same as .ENDS)
.ENDPROTECT ends protected netlist
.ENDS end subcircuit
.FOUR Fourier analysis
.FRA frequency response analysis in time domain
.FUNC function definition
.GLOBAL global node
.HSPICE$ enable HSPICE syntax priority
.IC initial condition
.INCLUDE include file
.LIB library file
.LOADBIAS load initial condition data from bias data file
.MACRO start macro definition (same as .SUBCKT)
.MC Monte Carlo analysis
.MODEL device model definition
.NODESET set node initial guess
.NOISE noise analysis
.OP operating point information
.OPTIONS run time options
.PARAM define parameters
.PLOT “line printer” plots
.PRINT print data
.PROBE save data in binary format
.PROTECT protect (hide) input netlist
.SAVE save data in binary format (same as .PROBE)
.SAVEBIAS save bias data to text file
.SAVEOPB save dc operating point bias data to binary file for schematic back annotation
5-1
.SENS sensitivity analysis

.STAT device statistical distribution
.STEP step circuit parameter
.SUBCKT start subcircuit definition
.TEMP set temperature
.TF transfer function
.TRAN transient analysis
.WATCH ignored (PSpice netlist compatibility only). TopView plots the listed variables.
.WC worst case analysis
.WIDTH input and output file line width
5.1.2 Simulation Setup

To simulate a circuit, the user must setup the desired simulation. There is no "default" simulation the user
can perform on a circuit without a setup. Any simulation run requires the following minimum setup:
1. Select one or more of the following analyses:
DC operating point
DC sweep
AC frequency sweep
Transient response
2. Specify the selected analysis command parameter values and options. There are no default settings
for the analysis commands. All commands require the user to specify the necessary parameter
values except for the DC operating point analysis command.
3. Specify at least one data output command. When simulating from the Schematic Editor, the .PROBE
command is enabled by default on the Simulation|Setup menu. The DC operating point analysis
does not require an output command.
Besides the above minimum setup, the user can specify these additional analyses: noise, distortion,
Fourier harmonics, sensitivity and transfer function.
The simulator can also be setup to repeat a simulation multiple times under different conditions using one
of the following advanced analysis options: temperature, parametric stepping, Monte Carlo, worst case
and alter circuit.
5.2 DC Analysis
The DC analysis determines the static operating point and the DC response of the circuit with inductors
shorted and capacitors opened. A DC operating point analysis is automatically performed prior to
transient analysis to determine the transient analysis initial conditions, and prior to an AC small-signal
analysis to determine the linearized, small-signal models for nonlinear devices.
The DC analysis can be used to generate DC transfer curves by sweeping an independent source, tem-
perature or resistor component value over a user specified range. The values of output variables are
stored for each sequential DC value and can be plotted or printed. If requested, the DC small-signal value
of transfer function (ratio of output variable to input source), the input resistance, and the output
resistance are computed as part of the DC solution. TopSpice can also determine the DC small-signal
sensitivities of specified output variables with respect to circuit parameters.
The following DC analysis command options are available:
.OP bias point calculation

.DC dc sweep
5-2
SIMULATION
.TF transfer function calculation

.SENS small-signal sensitivity calculation
The .OP statement must be used when the user wishes to see comprehensive operating point information
and the small-signal models for non-linear devices.
Examples:
.OP
.DC VIN -2 3 0.1
.DC VCC 0 5 0.2 IB 10uA 100uA 10uA
.DC RLOAD 1K 10K 500
.TF V(OUT) VIN
.SENS V(4) V(3,1) I(VBIAS)
5.3 AC Small-Signal Analysis

The AC analysis calculates the frequency response of a linear circuit under sinusoidal steady-state
conditions. This is a frequency domain analysis using the “phasor” concept. The circuit voltage and
current values are complex numbers (i.e.: they have real and imaginary parts, or magnitude and phase in
polar format).
The simulator first computes the DC operating point of the circuit and determines the linearized, small-
signal equivalent models for all of the non-linear devices in the circuit. The resultant linear circuit is then
analyzed through the user selected range of frequencies. Hence, the AC analysis results must not
necessarily be interpreted as being the same as using small amplitude sine waves in the time domain.
At least one AC input source must be specified for AC analysis. AC input sources are independent
sources, voltage or current, with the AC option value. Otherwise, the results of the AC analysis are
meaningless. A transfer function (voltage gain, transimpedance, etc.) is usually the desired output of an
AC analysis. Hence, it is convenient to set the AC input source values to unity and zero phase. Then, the
output variables have the same value as the transfer function values (output divided by input). Because
the results are complex numbers, to plot the results the data must be converted to a real component
(such as magnitude) or use a complex plane graph (such as a Smith or polar chart).
The following AC analysis options are available:
.AC frequency sweep

.NOISE noise analysis
.DISTO distortion analysis
Examples:
VIN IN 0 AC 1
.AC DEC 10 10KHz 10MEGHz
.AC OCT 10 2K 16K
.NOISE V(OUT) VIN 10
.DISTO RLOAD
Note: because the results of the .AC analysis are in complex number format, to plot or print the results,
the user must specify a real number format option. Examples,
.PRINT AC VDB(OUT) VP(OUT)

.PROBE
#AUTOPLOT AC VDB(OUT) VP(OUT)
5-3
5.3.1 Noise Analysis

The generation of noise by resistors and semiconductor devices is simulated using the .NOISE option in
AC analysis. Equivalent noise source values are determined by the program itself from the small-signal
operating point of circuit, and the contribution of each noise source is added at a given summing point.
The total output noise level and equivalent input noise level are determined at each frequency. The input
and output noise levels, which are measured in Volts/√Hz or Amps/√Hz, are normalized with respect to
the square root of the noise bandwidth.
To perform the noise analysis, the user must specify the noise output node (summing point) and the input
source for the equivalent input noise. The noise analysis data are available under the "noise" category as
real number data and as complex number data under the "ac" category. Input and output noise may be
printed or plotted as a function of frequency.
The SPICE noise analysis supports the following noise generator models: thermal (white), flicker (1/f) and
shot. The thermal noise is from the thermal motion in resistances. The flicker and shot noises model the
noise in PN junctions. Flicker noise sources are simulated in the noise analysis if the appropriate values
for the parameters KF and AF are included in the semiconductor device model cards.
The following devices have noise generator models:
Element Device Noise Type
D diode thermal, flicker, shot

J JFET, GASFET, MESFET thermal, flicker, shot
M MOSFET thermal, flicker, shot
Q bipolar transistor thermal, flicker, shot
R resistor thermal
S switch thermal
TopSpice allows the user to add custom noise generators to the noise analysis using the I current source
NOISE option.
The amount and type, if applicable, of noise contributed by the devices can be controlled by specifying
the device model noise parameters.
The noise output of the devices can be scaled or even suppressed using the following methods:
1. NOISE model parameter. For example, a group of resistors can be made noiseless by using the
resistor model option and setting the parameter NOISE to zero.
2. Global .OPTION NOISE option. This determines the default noise output scaling for all the devices in
the circuit. This value overrides the model NOISE parameter value. It does not affect the noise output
of I current sources with the NOISE option.
3. Subcircuit .OPTION NOISE option. This determines the default noise output scaling for all the devices
in the subcircuit definition. This option overrides the global .OPTION NOISE value. It does not affect
the noise output of I current sources with the NOISE option.
4. Device instance NOISE parameter. This parameter overrides the .OPTION NOISE value (global or
subcircuit).
For example,
5-4
SIMULATION
.OPTION NOISE=0
R5 3 9 150K NOISE=1
For the above example, the noise output is set to zero for all the devices in the circuit except R5.
The following example specifies a subcircuit model that does not generate any noise:
.SUBCKT QUIETAMP in1 in2 vp vn out

.OPTION NOISE=0
.
.ENDS QUIETAMP
The following example models a typical real life noise generator using the I current source NOISE option
injected at a circuit node
INSRC1 5 0 NOISE PINK 2.8E-8 100 1 1E-9
This example generates a 1/f noise with a cutoff frequency of 100Hz and a white noise floor of 1nV/√Hz.
5.3.2 Distortion Analysis

When the .DISTO option is specified the distortion characteristics, such as the harmonic content, of a
circuit in the small-signal mode are simulated as part of the AC analysis. The analysis proceeds assuming
that one or two signal frequencies are imposed at the input. The .DISTO analysis only includes the
distortion effects of diodes and BJTs.
To perform a more comprehensive distortion analysis, a Fourier analysis of the transient analysis output
waveform should be used.
5.3.3 Open Loop Gain Measurement

The TopSpice model library includes the OPENLOOPGAIN macromodel to perform "open loop gain"
measurement of a closed-loop system when running an .AC analysis.
To make a measurement, follow this procedure:
1. Insert the XOPENLOOPGAIN symbol or the OPENLOOPGAIN part from the model library at the
desired point in the feedback loop.
2. Add the following include command either as a text object on the schematic or using
Simulation|Open other SPICE commands file menu command:
.INC MEASUREOPENLOOPGAIN.TXT
3. If there are any existing autoplot commands setup, they should be disabled.
4. Setup and run an .AC analysis.
The OPENLOOPGAIN macromodel and MEASUREOPENLOOPGAIN.TXT include file implement the

open loop gain measurement technique described in [1]. They allow you to perform the measurement
without the need of a duplicate circuit. See the example circuit "Examples\General\Open Loop Gain
Measurement.sch" for a sample application.
Example netlist usage:
5-5
*CLOSED LOOP SYSTEM OPEN LOOP GAIN MEASUREMENT

V+ V+ 0 15V
V- V- 0 -15V
X1 0 1 V+ V- 2 LT1001
R1 1 0 1K
R2 1 OUT 1K
C1 1 OUT 3pF
R3 OUT 0 100
X2 2 OUT vmolgain imolgain OPENLOOPGAIN ;measurement macro
.INC MEASUREOPENLOOPGAIN.TXT ;measurement commands file
.AC DEC 30 0.1 100MEG
.PROBE
.END
[1] M. Tian, V. Visvanathan, J. Hantgan and K. Kundert, Striving for Small-Signal Stability, IEEE Circuits
and Devices Magazine, vol. 17, no. 1, pp. 31-41, January 2001.
5.4 Transient Analysis

The transient analysis computes the large-signal nonlinear response of a circuit as a function of time over
a user specified time interval. Unless the user provides the initial conditions for a circuit network, they are
determined by a DC analysis prior to the start of transient analysis. All sources with no time dependence
(for example, independent sources) are set to their DC value.
The transient analysis differs somewhat from the other analysis in that the time step used during the
analysis is not fixed by the user. Instead, SPICE uses a time step control algorithm to determine the
optimum time step for the present simulation conditions. However, the user can specify the maximum
time step limit. Also, the logic simulation algorithm defines a minimum discrete time step which can be set
by the user in the .OPTION statement. TopSpice will save all the simulated time points to the binary
output file if requested. The .PRINT TRAN command outputs data only at the user specified time steps
unless the TRAN/ALL option is used.
5.4.1 Fourier Harmonic Analysis

A Fourier harmonic analysis of an output waveform can be specified using the .FOUR statement to obtain
the Fourier harmonic coefficients and total harmonic distortion (THD) value with a transient analysis. The
output is in the form of a ".PRINT" table which can be plotted by the TopView post-processor.
A Fast Fourier transform (FFT) on any waveform can also be obtained using the TopView post-processor
FFT or #CALC FFT command after the simulation is completed.
Examples:
VIN IN 0 SIN(0 2.5 10MEGHz 0.1us -90)

.TRAN 5ns 500ns
.FOUR 1MEG V(out)
5-6
SIMULATION
5.4.2 Frequency Response Analysis

The Frequency Response Analysis (FRA) uses injected test signals and Fourier analysis to measure the
frequency response of a closed loop system in the time domain. This technique is based on the voltage
gain part of the Middlebrook method for linear systems. This analysis can be used to determine the
average small signal frequency response of nonlinear circuits and switched-mode circuits such as the
feedback loop of a SMPS circuit.
To apply the .FRA analysis to your simulation, you must follow these steps:
1. You must have a working transient simulation setup for your circuit.
2. You need to fully understand how the feedback loop you want to analyze works.
3. Identify a point in the feedback loop where a low impedance is driving a high impedance. Under this
condition the current gain can be assumed to be zero at this point. For most SMPS circuits, two places
are useful for this, either in series with the feedback pin of the SMPS controller or between the output to
the top of the resistor divider going to the feedback pin.
4. Insert a transient SINE voltage source here. This source will provide the sine wave signal that perturbs
the feedback loop. The choice of the sine wave amplitude will impact accuracy and the signal to noise of
the method. The smaller the amplitude, the lower the signal to noise ratio. But if the amplitude is too
large, the system is not operating linearly resulting in harmonic distortion of the test signal. A default
starting value of 10mV is recommended unless circuit operating characteristics indicate otherwise. The
direction of feedback should be from the source positive to negative nodes. For example for a SMPS
circuit, if the voltage source is connected directly to the feedback pin, the negative node is the feedback
pin. For example,
VFRA A B SIN 0 10mV 1KHz
The frequency of the source is irrelevant since it is set by the simulator for each FRA frequency run.
5. Specify the .FRA command for the desired frequency sweep and conditions.
Figure 5.1 Example FRA simulation circuit and setup.
5-7
Figure 5.2 FRA simulation plot and comparison to AC analysis results for
linear circuit for Figure 5.1.
The results are printed as a table to the output .OUT listing file. The table data is available in TopView as
the plot variables GAINDB_FRA and PHASE_FRA under the "Fourier/FRA" data category.
After the .FRA analysis is completed, the frequency response results are automatically plotted by default
regardless of any other "autoplot" commands was specified.
Figure 5.1 shows the FRA simulation setup for a linear op amp circuit. The simulation results are plotted
in Figure 5.2. The plot also compares the loop gain results using the FRA command and the AC analysis
Middlebrook method. As can be seen both simulation results match exactly as expected.
The example in Figure 5.3 illustrates FRA simulation to get the frequency response of a SMPS converter
circuit feedback loop using a transient switched controller model. The sine wave source VFRA is inserted
in the feedback loop circuit at the input to the feedback pin, which is the point where a low impedance
source is driving a high impedance input. The source positive terminal is connected to the low impedance
side.
Figure 5.3 FRA simulation setup for a SMPS converter circuit.
5-8
SIMULATION
Figure 5.4 SMPS circuit nominal transient simulation run.
In the FRA setup, the log frequency sweep is selected from 100Hz to 50KHz with two points per decade.
The following optional parameters are specified on the FRA setup:
“Time steady-state” is set to the time when the circuit output becomes stable. As it can be seen in Figure
5.4, this value is around 200us.
“Number of periods” sets the maximum number of the test signal sine wave periods to simulate.
“Time run maximum” sets the maximum simulation run time for any FRA frequency. The simulation run
time for a test signal frequency will be either the maximum number of periods times its period or the one
period time if its longer than the maximum run time (less the steady-state time). For this setup, at 100Hz,
the simulation will run for 10.2ms. At 10KHz, it will run for 400us.
Figure 5.5 shows the FRA simulation results plot.
Figure 5.5 FRA plot for SMPS simulation using switched model.
5-9
5.5 Analysis at Different Temperatures

TopSpice allows the circuit simulation to be performed at any user specified temperature, range of
temperatures or non uniform device temperatures. The default simulation temperature is 27 °C. The
following commands are available to control the operating temperature:
.TEMP Sets the operating temperature. If more than one temperature is specified in the
.TEMP statement the analysis is repeated for each temperature and the results
appended to the output file.
.DC TEMP Performs DC analysis while sweeping the temperature over the specified range.
.STEP TEMP Steps or sweeps the temperature over the specified values or range.
.OPTION TNOM Resets the nominal temperature. Model parameter values are assumed to
correspond to this temperature (default 27 °C). The nominal temperature for a
specific model can also be specified on the .MODEL statement.
TopSpice includes temperature effects for the following devices:
Element Description
C capacitor
D diode
J, B, Z JFET, MESFET, GaAs FET
L inductor
M MOSFET
R resistor
Q bipolar transistor
In addition, users can create their own temperature dependent components using the temperature
variable in expressions.
All model data is assumed to have been measured at a nominal temperature of 27 °C, which can be
changed by use of the TNOM parameter on the .OPTION control line. This value can further be
overridden by specifying the TNOM parameter on the .MODEL statement. Any temperature dependent
model parameters are evaluated before the simulation and the temperature updated values are printed to
the output file.
The most significant temperature effects included in SPICE are related to the exponential temperature
dependence of semiconductor junction parameters. For instance, the temperature dependence of the
junction saturation current is determined by:
XTI
T   E g q(T1T0 ) 
I S (T1 ) = I S (T0 ) 1
N
 exp 

 T0   Nk (T1 − T0 ) 
where k is Boltzmann's constant, q is the electronic charge, Eg is the energy gap, and To is the nominal
temperature.
The default resistor and capacitor temperature coefficients are set to zero, so they do not change with
temperature, unless the user explicitly specifies non-zero temperature coefficient values either on the
device statement or on a .MODEL statement.
Non-uniform temperature simulation is supported. The device parameters TEMP and DTEMP allow
different operating temperatures to be assigned to specific device instances. The TEMP parameter
specifies the temperature for the device. The DTEMP parameter specifies the temperature difference
5-10
SIMULATION
between the device and circuit temperatures. An operating temperature can also be specified on a
.MODEL statement using the T_ABS absolute temperature parameter.
The operating temperature of a device in the circuit is determined as follows:
1. The circuit operating temperature.
2. The specified model absolute temperature parameter (T_ABS) value if applicable. This value
overrides the circuit operating temperature.
3. The specified device temperature parameter (TEMP or DTEMP) value. This value overrides the
circuit operating temperature and the T_ABS temperature.
Examples,
Q1 2 5 0 2N3956 TEMP=65
R2 3 6 1K TC1=0.015 DTEMP=37
5.6 Analysis for Different Component Values

An important task in circuit design is the process of optimizing the design for improved performance or
manufacturing yield after an initial design is completed. This involves an iterative step of making minor
changes to the circuit components, simulating, and analyzing the effects on the circuit performance.
TopSpice includes several commands to help automate this task.
The following commands are available for performing repeated simulations using different component
values:
Command Description
.STEP Performs parametric analysis. The simulation is rerun while stepping the value of a
component, source or global parameter.
.ALTER Allows repeating the simulation while altering one or more component values, source
options, .MODEL statements or subcircuits.
.MC Performs Monte Carlo statistical analysis. The simulation is rerun while randomly
changing the component values using user specified statistical distributions.
.WC Performs worst case analysis. The simulation is rerun for all the permutations of the
extremes of the user specified statistical distributions and nominal values.
The TopView graphical post-processor features several functions to facilitate the task of plotting and
performing statistical analysis on simulation data from multiple runs:
TABULATE Scans the output file for the specified variable and tabulates its value for
all the runs.
PERFORMANCE SPEC Extracts performance spec data from the simulation results for all the
runs.
HISTOGRAM PLOT Plots data as histogram.
See the “TopView” chapter for more information on these functions.
5-11
5.6.1 Parametric Analysis

The .STEP command sweeps or steps the value of a variable. The .STEP command currently supports
stepping of the following variables:
Independent voltage and current source DC values

Resistors
Linear capacitors
Linear inductors
Temperature
Global parameters (.PARAM parameters)
Linear or logarithmic sweeps, or lists of values may be specified as the stepping values. TopSpice also
offers tolerance value stepping and wildcard name options. The tolerance value option allows you to
specify values as percent deviations from their nominal values. The wildcard (*) option allows you to step
a group of devices by specifying a partial device name followed by a wildcard in the .STEP statement.
Used in combination with the tolerance value stepping option, you can use the wildcard feature to
change, for example, all resistors in a circuit by a certain percentage of their nominal values.
Only one .STEP statement is allowed. For each step value, the entire simulation is repeated including all
temperature values if a .TEMP command is present.
Examples,
.STEP R1 200 1K 100

.STEP LIN VCC 12V 8V 0.5V
.STEP DEC IBIAS -1uA -1mA 10
.STEP OCT L1 1uH 16uH 20
.STEP CF LIST 10pF 20pF 50pF 100pF 75pF
.STEP PARAM GAIN LIST 5 20 50 100
.STEP LIN PARAM F3DB 100KHz 200KHz 20KHz
.STEP R20 LIST% -28% -10% 0 5% 120%
.STEP LIN% C5 -0.5 0.75 0.25
.STEP R* LIST% -10% 0 5% 20%
.STEP LIN RX* 5K 7.5K 500
.STEP TEMP –15 0 25 50 75
A group of devices can be stepped by specifying a partial device name followed by a wildcard in the
.STEP statement. Used in combination with the tolerance value stepping option, you can use the wildcard
feature to change, for example, all resistors in a circuit by a certain percentage of their nominal values.
Examples:
.STEP R* LIST% -10% 0 5% 20%

.STEP LIN RX* 5K 7.5K 500
In the first example, all resistors are stepped. In the second example, only resistors with names that start
with "RX" are stepped.
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SIMULATION
5.6.1.1 Tolerance Stepping

Step values can also be specified as percent deviations from the nominal value. This option is supported
only for stepping device values - it cannot be used with global parameters. To specify tolerance values,
use the following .STEP statement syntax:
.STEP LIN% device start stop step

.STEP DEC% device start stop #points
.STEP OCT% device start stop #points
.STEP device LIST% <value list>
Examples:
.STEP R20 LIST% -28% -10% 0 5% 120%

.STEP LIN% C5 -0.5 0.75 0.25
5.6.1.2 Multidimensional Stepping

"Multidimensional" parametric stepping can be performed using the .STEP command and the TABLE
function. In another words, it allows you to change multiple independent components at each step. Use
the following procedure:
1. Define a dummy parameter, such as CASE, to select each step case.

2. For each parameter or component value you want to change, define its value using a TABLE function
look-up corresponding to each step case:
{TABLE(name,value1,value2,value3,…,valuen)}
For example,
.PARAM CASE=1
.PARAM GAIN={TABLE(CASE,1,60,2,15,3,20)}
VCC vcc 0 {TABLE(CASE,1,3.5V,2,5V,3,6.2V)}
R1 2 1 {TABLE(CASE,1,5K,2,10K,3,15K)}
.
.STEP PARAM CASE LIST 1,2,3
In the above example, the values of both VCC and R1 are stepped for each CASE step.
5-13
5.6.2 Alter Circuit

The .ALTER command allows you to alter the circuit and rerun the simulation. It is more flexible than the
.STEP command but not as easy to use. The .ALTER command allows any combination of devices,
sources, .MODEL statements or subcircuits to be changed between runs. Each ALTER run can include
changes to more than one statement. Also, different number of statements or different statements might
be changed between runs. However, circuit elements cannot be added or removed between ALTER runs
except by altering subcircuits.
The .ALTER statements must be placed just before the .END statement. The following statements can be
changed using .ALTER:
All devices
Subcircuit calls (X element, number of interface nodes must be same)
.INC
.LIB (HSPICE format only)
.MODEL statements
.PARAM statements (global only)
The syntax for the altered statements is identical to that of the original statements. No changes in node
names, number of nodes or order of nodes are allowed.
There is no limit on the number of .ALTER statements and the simulation will be rerun as many times as
the number of .ALTER statements. The circuit is restored to its nominal state between .ALTER iterations.
Hence, any .ALTER changes only apply to one .ALTER run and not to subsequent .ALTER runs (i.e.: the
changes are not cumulative).
Example:
.
VCC 1 0 SIN(0 10V 20KHz)
R1 2 0 5K
M1 OUT 2 0 NFET L=2U W=100U
.MODEL NFET NMOS(VTO=1V KP=200U RS=10 CGSO=1E-14)
*
* Repeat simulation with altered elements
.ALTER ;run #2
VCC 1 0 SIN(0 20V 30KHz)
R1 2 0 3.5K
M1 OUT 2 0 NFET L=2U W=150U
.ALTER ;run #3
.MODEL NFET NMOS(VTO=1V KP=400U RS=5 CGSO=1E-14)
VCC 1 0 PULSE(0 10V 0 0 10us 10us 100us 200us)
.ALTER ;run #4
R1 2 0 10K
.END
In this example three additional runs are made after the nominal case.
No topological change of the circuit is allowed – for instance, a new component cannot be added.
However, subcircuits may be substituted as long as the number of nodes for the subcircuit call (interface
nodes) remain the same. For example, one can try different op amp models using the .ALTER
statements:
.
X23 3 1 vcc vee out UA741
.
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SIMULATION
.ALTER
X23 3 1 vcc vee out LM107
.ALTER
X23 3 1 vcc vee out AD607
Global .PARAM parameters can be changed in .ALTER runs. The values of nominal circuit parameters
can be altered and new parameters can be added. For example,
.PARAM VNOM=5V
VCC 1 0 {VNOM}
R10 2 0 5K
*
* Repeat simulation with altered elements
.ALTER
.PARAM VNOM=4.5V RLOAD=10K
VCC 1 0 {VNOM}
R10 2 0 {RLOAD}
When working with HSPICE format model libraries, .ALTER statements can be used to repeat the
simulation for different process corner (nominal, slow, fast, etc.) models. For example,
.
M12 vcc out 0 0 NFET1
.LIB cmos02u.lib TT
.
.ALTER
.LIB cmos02u.lib SS
.ALTER
.LIB cmos02u.lib FF
When working with model files or even model libraries, .ALTER statements can be used to repeat the
simulation for using different model files by using .INC statements. However, the model names must
remain the same.
For example,
.
Q12 out 27 0 NPNMOD
.INC STD.MOD
.
.ALTER
.LIB FAST.MOD SS
.ALTER
.LIB SLOW.MOD FF
When running simulations from the Schematic Editor, .ALTER commands must be specified using the
Simulation|Setup command. Click on the .ALTER button on the Simulation Setup dialog. The easiest
way to specify the ALTER statements is to first create the circuit SPICE netlist using the Simulation|View
circuit file command, then using the text editor “copy and paste” function copy the appropriate
statements to the ALTER commands file.
5-15
5.6.3 Monte Carlo Analysis

A circuit design must take into account the effects of the component variations or tolerances if it is
expected to work within the design specifications when it is manufactured. This is commonly referred to
as statistical design centering and the objective is to maximize the manufacturing yield. Another purpose
of statistical analysis is to predict the design performance window (worst and best specs.). The .MC
command in TopSpice performs Monte Carlo statistical analysis. The Monte Carlo analysis simulates the
random variations in the component values and their effects on the performance of the circuit. For
example,
.MC 100 SEED=123
This command specifies that 100 runs be simulated which is equivalent to 100 samples of the circuit. The
first run is always the nominal case (without any random changes).
The optional SEED parameter specifies an initial seed for the random number generator. The advantage
of giving a seed is that the same sequence of random numbers can be reproduced, if needed in the
future, by repeating the Monte Carlo analysis on the same circuit. Otherwise, TopSpice uses a different
seed for every Monte Carlo analysis.
At least one .STAT statement must also be present to specify the device statistical tolerance parameters.
The file STATSDEFAULT.TXT in the TopSpice installation folder contains default .STATs statements for
resistors, capacitors and inductors. This file can be included using the .INC command or by checking the
“User default .STATs” option on the “Simulation Setup” Monte Carlo setup menu.
5.6.3.1 Device Tolerances

To perform a Monte Carlo analysis, TopSpice chooses component values generated by a random
number generator with the user specified probability distributions and tolerance ranges. The .STAT
command is used in TopSpice to specify the device tolerance statistical distributions. The device
tolerance represents variations between components for a given sample.
For example,
.STAT R* GAUSS 5% -2 +3
.STAT Q* 2N3906 BF ARECT 40 -1 +1
The first .STAT command specifies that all resistors have a Gaussian statistical distribution with a
standard deviation, σ, of 5% of the nominal value. The tolerance range parameters specify that the
distribution is "cut-off" at -2σ and +3σ. This limiting reflects the fact that measured distributions of
component values always exhibit cut-off points. If this information is not available a good rule of thumb is
to assume ±3σ cutoffs. In addition, the limiting is needed to remove the possibility that unrealistic values
are generated. For instance, a resistor can never have a negative value.
The second statement specifies that the BJT model 2N3906 parameter BF have a rectangular (uniform)
distribution extending ±40 from the nominal value. The distribution applies to all 2N3906 devices. Since
this is an absolute tolerance the standard deviation is given in units of BF. TopSpice allows both relative
and absolute tolerances. For relative tolerances, as in the first .STAT statement, the standard deviation is
specified as a percentage.
The .STAT command can be applied to a single device or subset of devices. For example,
.STAT RW* RECT 2% -2 +2

.STAT COUT AGAUSS 20pF -3 +3
The first .STAT statement applies only to resistors having reference names starting with "RW". The
second one applies only to capacitor COUT. The more specific .STAT command overrides a more
5-16
SIMULATION
general one. Hence, for the last example, if there were another .STAT command that applies to all the
capacitors, the one for COUT will be used for that device.
5.6.3.2 Lot Tolerances

The .STAT command allows an optional lot tolerance specification which represents the variations in the
mean values between different samples. If a lot tolerance distribution is given, the value of an affected
component is calculated for each run as follows:
VALUE = VNOM + ∆LOT + ∆DEV
where
VNOM is the nominal value.

∆LOT is the lot tolerance variation.
∆DEV is the device tolerance variation. For relative tolerances it is given by
∆DEV = (VNOM + ∆LOT) σ DEV
For example,
.STAT R* GAUSS 5% -4 4 LOTTOL RECT 10% -1 1
In this example, all the nominal values of all the resistors in the circuit are shifted by the same run lot
tolerance (up to ±10%). In addition, each resistor includes the device tolerance (different for each resistor)
which can range up to ±20%. Hence, in the worst case a resistor could be up to -28% or +32% off from
its nominal value.
The lot tolerance attempts to model the manufacturing lot to lot variations. For instance, if one were to
measure a sample of 100K resistor, it might yield a mean value of 98K. However, another sample from a
different lot might have a mean value of 105K due to minor variations in materials or processes during the
manufacturing of the different lots.
Another common application of lot tolerance is in modeling the variation of device parameters over a
wafer area when manufacturing integrated circuits. A silicon wafer is divided into small areas or dies
each containing a circuit. The device parameters within a die exhibit certain distribution and mean which
are modeled by the device tolerance. But different dies might exhibit slightly different mean values
depending on their location on the wafer. This effect is modeled using the lot tolerance.
5.6.3.3 Tolerance Tracking

Besides the device and lot tolerances, the user also has the option for specifying a correlation coefficient.
This allows modeling of tolerance tracking between devices. Tracking arises because the device-to-
device variation is not truly random but it is rather dependent on some common factor. This is often
observed in the design of integrated circuits. Because the devices are fabricated on the same die, the
variations between devices generally exhibit a correlation with their locations on the die. For example,
the transistor parameters inside a memory cell would show much less variation than the overall
distribution for the whole chip.
Example,
.STAT MCELL* NCELLFET VTO AGAUSS 0.1 -3 3 CC=0.8
This command specifies a linear correlation coefficient of 0.8. A coefficient of 1.0 means there is no
variation between devices. A value of zero means the variations are completely independent (random).
5-17
When a correlation coefficient is given, the position of the device statements in the netlist becomes
significant. Devices that track each other should be next to each other on the netlist. The more
separated the devices are the less they will track.
5.6.4 Worst Case Analysis

The .WC (or .WCASE) worst case analysis command runs the extremes of component statistical
distributions and nominal case permutations. The purpose of the worst case analysis is to predict the
design performance window (worst and best specs.). A circuit design must take into account the effects
of the component variations or tolerances if it is expected to work within the design specifications when it
is manufactured.
Examples,
.WC
.WC CORNER
.WC NOCORNER
The CORNER option only runs the permutations for the extremes of the distribution without the nominal
case. The NOCORNER option excludes runs for permutations that don't include the nominal case.
The number of runs in a worst case analysis is 3 to the power of .STAT statements applicable. With the
CORNER option, the number of runs needed is 2 to the power of .STAT statements. With the
NOCORNER option, the number of runs is the difference between the default and CORNER option runs.
Because the runs needed increases exponentially by the number of applicable .STAT statements, their
number should be minimized as much as possible. The .STAT options NOWC and WCONLY can be used
to selectively use the same set of .STAT statements for both Monte Carlo and worst case analyses.
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SIMULATION
5.7 Data Output and Post-Processing Commands

To request simulation result output you must specify one or more of the following commands depending
on the analyses being performed:
.OP Prints bias point information.

.PRINT DC Prints dc sweep tabulated data.
.PRINT AC Prints frequency sweep tabulated data.
.PRINT NOISE Prints noise analysis tabulated data.
.PRINT DISTO Prints distortion analysis tabulated data.
.PRINT TRAN Prints transient analysis data using user specified time step.
.PRINT TRAN/ALL This option allows all the calculated time points data to be printed.
.PROBE Saves all circuit voltages and currents, or user specified list, in a compact
proprietary binary format (valid for any analysis).
.SAVE Same as .PROBE
.TF Prints small-signal transfer function results.
#AUTOPLOT Post-processor directive to "auto plot" specified variables and expressions. The
SMITHCHART, HISTOGRAM and FFT options auto plots the specified graph
types.
#CALC Post-processor directive to calculate expression variables. This is useful to
calculate intermediate expression variables that must be used in other
expression variables.
#MEASURE Post-processor directive to measure performance spec data variables from
multiple runs simulations.
#TABULATE Post-processor directive to tabulate quantities found in the output file and save
them as variables.
The .PROBE, .PRINT, .OP, .SENS, .TF, .FOUR and #AUTOPLOT commands may be specified using the
Schematic Editor Simulation|Setup command menu. The other commands must be specified using the
Simulation|Open User SPICE Commands File menu command, or directly on the schematic or circuit
file.
Examples:
.PRINT DC V(2,3) V(1) V(OUT) I(VDD)

.PRINT AC VM(10) VP(10) VDB(OUT) IM(VIN)
.PRINT NOISE INOISE ONOISE(DB)
.PRINT DISTO HD2 HD3(R) SIM2(DB)
.PRINT TRAN V(2) V(OUT) I(VSRC)
.PRINT TRAN/ALL V(3) D(Q)
.PROBE
.PROBE V(1) V(OUT) I(RBIAS)
.PROBE VONLY NOSUBCKT
#AUTOPLOT V(1) {GAIN=V(OUT)/V(IN)}
5-19
5.8 Simulation Commands

SPICE simulation commands may be specified either by using menus or by typing the command
statements directly by the user. Most frequently used simulation commands can be conveniently specified
by selecting the appropriate Schematic Editor Simulation|Setup menu options.
The Setup menu settings are saved in the schematic file. When the Run simulation command is issued,
the menu settings are converted to SPICE statements and written to the circuit netlist .CIR file. For
detailed descriptions and usage of the Simulation|Seutp menu options see the next section.
In addition, the Schematic Editor allows the user to directly enter any other SPICE statements such as
device models, library commands, subcircuit definitions, simulator options and comments in the
miscellaneous command file (filename extension .MIS). To add or edit statements in the miscellaneous
command file, use the Simulation|Open User SPICE Commands File command. The contents of the
miscellaneous command file are inserted after the title line and before the circuit netlist information.
Note: .ALTER command statements should be added by selecting the Setup menu .ALTER setup
button, which opens a text editor window for the .ALTER commands file (filename extension .ALT).
An .INC statement for this file is automatically inserted in the SPICE circuit file before the .END
statement.
SPICE commands and comments can also be placed directly on the schematic drawing using text
objects. Any text object that starts with the character ".", "#" or "*" is considered a SPICE command or
comment and added to the netlist file when the netlist is written. They are added in the same order they
were placed on the drawing regardless of their position on the drawing.
Although, you could manually edit the circuit file using a text editor, this is not recommended since any
changes made would be lost whenever the program writes a new circuit file.
5.9 Simulation Setup Menu

The easiest way to specify the analysis and output commands for a schematic circuit project is by using
Figure 5.6 Simulation setup menu
5-20
SIMULATION
the “Simulation Setup” menu which can be invoked by selecting the Simulation|Setup command from
the Schematic Editor. To specify an analysis command, check the appropriate enable box and complete
the setup menu for it. To disable the command, simply uncheck the enable box. To change the setup
settings, click on the setup button for the analysis.
5.9.1 DC Bias Point Setup

If you want to obtain the DC operating point information check “Operating point detail” box. If you want to
perform a transfer function calculation, check the enable box for it, and enter a input source name (ex.:
VIN) and an output node voltage name in the format V(node) (ex.: V(5)). If you want to perform a
sensitivity analysis, check the enable box for it, and enter a list of node voltage names in the format
V(node) (ex.: V(1) V(OUT)).
5.9.2 DC Sweep Setup

In the “Sweep variable” box enter the name of the variable you want to sweep. Supported sweep DC
variables are independent voltage or current sources, resistors and temperature (TEMP). Next specify
the sweep start, stop and step values in the appropriate boxes.
If you want to perform the optional nested sweep, check the enable box for it and fill out the other boxes
as previously.
5.9.3 Transient Analysis Setup

Specify the step and stop times in seconds. “Time step” only serves as an initial value for the automatic
time step algorithm so any reasonable value is acceptable. It is also used as the .PRINT TRAN output
and .FOUR analysis data time increment value. A recommended value is one hundredth of the stop time
if there are no other simulation factors.
The other entries are optional. “Step ceiling” specifies the maximum time step allowed. This might be
necessary to improve the solution accuracy under some conditions. If you want the program to skip the
initial bias point calculation check the “Skip initial transient solution” box.
If you want to perform a Fourier harmonic analysis (.FOUR command), check the enable box for it and
enter the fundamental frequency in Hertz. By default 9 harmonics are calculated. Enter the number of
desired harmonics if different (up to 100). In the “Output variables” box enter the names of the node
voltages you want to observe in the format V(node) (ex.: V(OUT)).
5.9.3.1 Frequency Response Analysis Setup

To perform a frequency response analysis (.FRA command), check the enable box for it and click the
“Setup” button. Enter the test sine wave signal voltage source name in the format Vname.
Select the frequency stepping option: linear or logarithmic (DEC). Enter the start and stop frequencies in
Hertz. If linear stepping was selected, enter the frequency step increment. If logarithmic stepping was
selected, enter the number of frequency points per decade.
The optional setting “time steady-steady” must be specified if your circuit requires a certain time to reach
steady-state conditions or exhibits startup transients. The data for this initial time is ignored for FRA
calculations. Otherwise, the FRA results would not be correct. By default, the first data points near time
zero is always discarded.
5-21
The optional setting “time step ceiling” specifies the maximum time step for the transient analysis runs. It
overrides the step ceiling setting for the .TRAN statement. At least 100 time points per sine wave period
will always be simulated.
The optional parameters “number of periods” and “time run maximum” are useful for limiting the total
analysis time for long running simulations. The “number of periods” parameter specifies the number of
sine periods of the test signal to simulate for each frequency (default is five).
The “time run maximum” parameter specifies the maximum transient simulation time for any frequency
step run. When this parameter value is given, the transient simulation will run for the number of sine
periods if less than this value. Otherwise, the number of sine periods simulated is limited to be less than
this value. If this parameter value is less than one sine period, one period is simulated. This parameter
can be useful for limiting the transient run time at lower frequency steps while maintaining maximum
accuracy for higher frequencies.
The measurement circuit nodes can also be specified. The default nodes are the test signal source
terminals. The user can specify either the positive node only or the positive and negative nodes. To
specify a node, just enter its name only (not the format V(name) required by the .FRA statement).
See sec. 5.4.2 for more information about properly setting up a circuit for FRA.
5.9.4 AC Sweep Setup

Check the type of frequency sweep you want (decade, octave or linear). For decade and octave sweeps,
enter the number of points per decade or per octave. For linear sweeps, enter the total number of points
you want in the sweep. Enter the start and stop frequencies in Hertz.
To perform a noise or distortion analysis during the AC sweep, check the appropriate enable box. For the
noise analysis, specify the “input source name” which can be an independent voltage or current source
with the AC specification (ex.: VIN or I2), and the output node voltage name in the format V(node) (ex.:
V(5)). The “Summary print interval” specifies the number frequency sweep points interval at which a
detailed summary of the noise analysis is printed to the output file.
See the .DISTO distortion analysis command description in the Simulator Reference manual for detailed
explanations of the entries on the “Distortion Analysis Setup” menu.
5.9.5 Temperature Setup

To analyze your circuit at different temperature(s), enter the temperature values in degrees C. All the
requested analyses are repeated for each operating temperature.
5.9.6 Parametric Step Setup

To repeat the simulation for different component or global parameter values, enter the name of the
component (resistor, capacitor, inductor, or independent voltage or current source) or parameter. For
components, the name can be the full name or a partial name terminated by the wildcard (*).
Select the desired step mode: list of values, linear sweep, logarithmic decade sweep, logarithmic octave
sweep. For the list of values option, enter the desired step values. If you chose a sweep mode, enter the
sweep limits. For linear sweep, enter the step size. For logarithmic sweeps, enter the total number of
points for the sweep. You can specify absolute or tolerance (percent deviations from nominal) values by
selecting the appropriate choice.
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SIMULATION
5.9.7 Monte Carlo and Worst Case Setup

To perform a Monte Carlo analysis, select "Monte Carlo" and enter the number of runs you want. You
only need to specify a seed number if you want to repeat a Monte Carlo analysis using the exact same
sequence of random values.
To perform a worst case analysis, select "Worst Case". The "Corners and nominal" option runs all
possible permutations of the extreme corners of the distributions and the nominal case. The "Corners
only" option runs only the extreme corners of the distributions without the nominal case. The "No corners"
option excludes the permutations without the nominal case.
The file STATSDEFAULT.TXT in the TopSpice installation folder contains default .STATs statements for
resistors, capacitors and inductors. This file can be included using the .INC command or by checking the
“User default .STATs” option on the setup menu.
5.9.8 .ALTER Setup

To run .ALTER iterations, click the ".ALTER" enable box and button. The .ALTER statements must be
specified in a "ALTER commands" file which is a text file with the same file name as the schematic but
with extension ".ALT". Clicking on the ".ALTER" button opens the "ALTER commands" file with the
TopSpice text editor.
When writing the SPICE netlist for the schematic, an .INCLUDE statement for the ALTER commands file
is added at the end of the netlist before .END statement.
5.9.9 Post-Processor Directives Setup

To specify post-processor directive commands such as #MEASURE, click the “Post-processor Directives”
enable box and button. This opens the text editor window where you can enter the directive statements.
They are saved to a “post-processor directives” file with the same file name as the schematic but with the
.PPD file extension.
When writing the SPICE netlist for the schematic, an .INCLUDE statement for the post-processor
Figure 5.7 Save data setup menu
5-23
directives file is added.
5.9.10 Save Data Setup

This setup determines what simulation data are saved to the binary output file. The setup specifications
are converted to .PROBE command statements.
The “Save everything” option will save the simulation results for all the circuit variables (voltages, device
currents, magnetic core B and H values, and digital node states). When this option is selected, you can
choose to limit the output to voltages only or exclude subcircuit variables, by selecting the appropriate
options.
The “Save listed variables” option saves only the user specified data. You must enter the list of the
variables you want to save in the “Variables list” box. AC variable names with real format options such as
VDB(x) are not allowed.
When the “Save listed variables” option is selected, you can choose to save automatically the variables
listed in the “auto plot setup” menu by checking the “save autoplot variables” option. This also saves any
variables listed on #AUTOPLOT statements specified directly in text objects and any variables found on
#AUTOPLOT and #CALC expression variables.
If a simulation generates very large amounts of data, the “options to minimize data file size” can further
reduce the size of the output data file. The “minimum data interval time for transient analysis” option
specifies the minimum data save interval time for transient analysis simulations. For example, if 10us is
specified, data is saved only if the new time point is greater or equal than 10us from the previous time.
The “use single precision number format” option saves the data in single-precision floating-point number
format which has a precision of 8 decimal places. The default is double-precision number format which
has a precision of 16 decimal places. Selecting the single-precision option will reduce the data file size by
about half.
5.9.11 Print Data Setup

To print a tabular numerical output of the analysis results to the output file, choose the applicable analysis
option and enter the list of variables you want to print. The print function is available for DC sweep,
transient analysis, AC analysis, noise analysis and distortion analysis. For the transient analysis case,
you have the option to print all the calculated data points or only at the step time intervals.
In addition, the user has the option to specify the number of decimal digits and output file when printing
the data. The number of allowed digits is 4 to 15. If the "output to user file" option is set and a user
filename is specified, all the print data is written to the specified file.
5.9.12 Auto Plot Setup

The “auto plot” setup allows you to specify what the TopView post-processor program will plot
automatically after the simulation is completed. Each setup represents a graph with one or more plots. A
plot can represent a separate y axis plot, continuation of the same plot or a different plot. For each plot,
the user specifies a list of variables and/or expressions. The plots can be enabled or disabled separately.
You can specify any of the following graph options:
Type: TopView will automatically determine the X-Y plot type required for the data. However, if
you want to plot a FFT, histogram or Smith chart, you must check the appropriate option.
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SIMULATION
Figure 5.8 Auto plot graph setup menu
Analysis: the graph setup is applied to any analysis data available unless you select a specific
analysis option.
Axis scale: TopView automatically selects the appropriate axis scaling for the data. You can override
this by selecting one of the available axis scaling modes.
X variable: by default, the x variable is the analysis sweep variable. For example, for transient
analysis is time and for AC analysis is frequency. However, you can change the x
variable to any other output variable.
X axis: TopView automatically selects the appropriate X axis data range and tick spacing. You
can override this by unchecking (disabling) the Auto option and entering the X axis
minimum, maximum and tick values. You can also change the Label for the X axis (blank
means default label which is usually the X variable name).
To create additional graph setups, click the New button. You can select any of the existing graph setups
using the Next and Previous buttons, or delete a setup using the Delete button. You can also enable or
disable any of the graphs by checking the “Enable autoplot graph setup #” box.
Click OK after you are finished specifying the plots and options for all the graph setups.
There is no limit to the number of plots allowed per graph. However, up to 8 separate Y axes can be
actually plotted on the same graph. To add traces to a graph, click the Add Traces button. The traces
can be assigned to new or existing plots. You can select any of the existing plots by clicking on its
description in the plots list. Then, click the Edit button to edit the plot setup or the Delete button to delete
the plot.
To setup a plot, enter the names of the output variables you want to plot in the “Variable/expression list”
box separated by blank spaces. You can also specify any of the following plot options:
5-25
Figure 5.9 Plot setup menu
Description: Optional plot description text. If not given, the list of variables is used as the description.
Plot number: TopView can display up to 8 separate plots (with common X axis) in a single graph. By
default, the program will automatically determine the appropriate number of plots based
on the data. You can override this and select a specific plot using this option.
Y axis: TopView automatically selects the appropriate Y axis scaling and range for the data. You
can override this by specifying the Y axis options. If Log is checked, a log scale is used
which overrides the graph setup Axis scale option setting.
TopView automatically selects the appropriate Y axis data range and tick spacing. You
can override this by unchecking (disabling) the Auto option and entering the Y axis
minimum, maximum and tick values. You can also change the Label for the Y axis (blank
means default label which is usually the variable name or type).
Click OK after you are finished specifying the plot setup.
5.10 SPICE Netlist and Circuit File

A SPICE netlist and circuit file is generated whenever any of the following Schematic Editor commands is
selected: Simulation|Run Simulation, Simulation|View Circuit File, Simulation|View Netlist Cross
Ref Map, File|Netlist As and File|Exit. The File|Netlist As option allows you to save the netlist under a
different file name or the entire schematic as a subcircuit netlist. To inspect the netlist for the current
schematic, select the Simulation|View Circuit File option. Although you can edit the netlist using this
option any changes will be overwritten the next time the netlist is generated.
If a circuit file of the same name already exists, that file is converted to a backup file with extension .BAK
before creating the new circuit file.
Special considerations for generating correct SPICE circuit files:
Title: the program uses the schematic title block title as the SPICE circuit file title.
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SIMULATION
Parts: each part on a schematic corresponds to a SPICE circuit element statement. The schematic part is
converted to a SPICE statement either using the default netlist syntax rule for the part symbol or the user
specified part netlist attribute.
Power rails: the program generates a SPICE statement for a power rail symbol V+ or V- (POWER+ or
POWER-) only if a value is specified. If your schematic has more than one power rail symbol with the
same name, only one statement is created and the rest are ignored.
Optional parameters: you can include optional parameters for some SPICE elements such as the
MOSFET L and W parameters, or independent transient sources on the parameter fields of the part
attribute dialog box.
Text objects: schematic text objects starting with the following characters are added to the netlist as
SPICE command statements: period, asterisk (*), pound (#). Leading space characters are ignored when
checking for SPICE commands.
Digital global nodes: to connect digital part pins to the fixed digital logic high, low or NC (no connection)
nodes, place a label next to the pin with the corresponding node name: $D_HI, $D_LO or $D_NC.
SPICE library models: when using a SPICE library model, you must specify the library model name as
the part's value attribute instead of the actual part number (if they are different).
Reference names: the reference name identifies an instance of a certain part on the schematic or an
element in a SPICE netlist file. The program uses the first character of the symbol name to determine the
type of SPICE element for the symbol (this can be overridden by the “device type” attribute). When
generating the SPICE statement the program uses that character as the first letter of the SPICE reference
name for the symbol regardless of what the symbol reference name is. For example, if you give the
schematic reference name T10 for the BJT symbol Q, the corresponding SPICE statement created by the
program will use the reference name QT10 instead to obtain the correct SPICE statement.
SPICE syntax and topology rules: the Schematic Editor program does not perform any error checking
of the circuit netlist for violations of SPICE simulator syntax or circuit topology rules. This is done by the
simulator program when running the simulation. Any errors found are reported in the simulator output file
– this is a text file which the user can examine using the Simulation|Browse Output File command.
The SPICE circuit file written by the Schematic Editor has the following structure:
Title line
#revision: info
text objects
.INC filename.MIS (if used)
.INC filename.PPD (if used)
model file links
circuit netlist
.INC filename.CMD
.INC filename.ALT (if any)
.END
See the Simulator Reference manual for more detailed information regarding SPICE circuit files.
5-27
5.10.1 Map File

Whenever a netlist file is written, the program also writes a map file (filename extension .MAP). This file
contains cross reference information regarding the parts, pins, wires and nodes. It also includes any
netlisting error messages. The Schematic Editor menu command Simulation|View Netlist Cross Ref.
Map File allows you to browse the map file.
The information in the map file can be helpful in locating the source of the any netlist errors on the
schematic or to view a list of parts connected to a node.
5.10.2 Netlisting Error Messages

Open pins: this error indicates one or more part pins were left open (not connected to a wire or another
pin). Labeled pins are not considered open even if nothing is connected to them.
Conflicting label assignment: this error indicates that different label names were assigned to the same
wire, or connected wires and/or pins.
The Schematic Editor does not perform any SPICE netlist syntax checking.
5.11 Running Simulations

To run a simulation, either click on the “Go” (green traffic light) toolbar icon or select the Simulation|Run
Simulation menu command. If there are more than one simulator engine installed, you can use the
Simulation|Simulator Engine Option command to select the desired simulator before running the
simulation.
When the simulation run command is given, a SPICE netlist is extracted from the schematic drawing first.
The netlist along with the simulation command statements and any necessary simulation model links are
written to a SPICE circuit file (filename extension .CIR). This is the input file for the simulator.
To view the SPICE netlist circuit .CIR file extracted from the schematic drawing, use the Simulation|View
SPICE Circuit File command. This file should not be manually edited because any changes made will be
overwritten by the program.
After a simulation has been completed, you can perform one of these related functions:
Bias point voltages The View|OP Voltages and Currents command displays the simulated DC
and currents operating bias point node voltages and currents for voltage and dependent
sources on the schematic drawing.
View|OP Device Currents command displays the simulated DC operating bias

point currents for the following devices: all sources, resistors, diodes, BJTs
(collector), MOSFETs (drain), JFETs (drain), switches.
Plot data The Simulation|Plot Data command runs the TopView post-processor program
with the last simulation run output file as the command argument. This
command allows you to plot the previous simulation results data without the
need to rerun the simulation.
Browse output file The Simulation|Browse Output File command allows you to browse the
simulation output listing (.out) file. This file contains useful information about the
simulation such as detailed operating point information and simulation statistics.
You should also use this command to check for simulation error and warning
messages.
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SIMULATION
5.11.1 Multiple/Parallel Simulations

The Simulation|Run Multiple/Parallel Simulation command runs multiple simulations for the same
schematic. This command can be selected only after a normal Run Simulation is executed first. This
command allows the user to simulate the same circuit with different changes without waiting for each
simulation to finish. If your PC has a CPU with multiple cores, the simulations will run in parallel. This
command also makes it more convenient if you want to plot all the runs on the same plot.
The multiple simulation runs after the first normal run use the simulator "-batch" mode. No automatic
plotting is done after each multiple simulation run. Instead, the user must add the results from the multiple
runs using the TopView File|Open Multiple/Parallel Runs command to the first simulation run plot.
To combine the multiple simulation runs results for the same variable into a single trace, use the TopView
Traces|Merge Same Name Traces command.
For multiple simulations to run in parallel, the number of simulations running should not exceed the
number of CPU physical cores in your system. The actual assignment of which core runs a parallel
simulation is done by the Windows operating system, not the simulator application. Windows might not
always assign each parallel simulation run to a different core depending on other applications
concurrently running and other system conditions.
A multiple run uses filenames of format name.run#.* where name is the original file name. For example, if
the circuit filename is mydesign.sch, the second multiple run files would be mydesign.2.cir,
mydesign.2.out and mydesign.2.sav.
A Run Simulation command “resets” and starts a new multiple run sequence.
5.11.2 Pause-Plot-Resume Simulation

The "PAUSE-PLOT-RESUME" simulation feature allows you to pause a simulation, plot the simulated
results up to that point, and either resume or terminate the simulation.
To pause a simulation, select Pause from the simulator window menu. Then, click "Yes" to plot the partial
results. To resume or terminate the simulation, exit (or close) the TopView post-processor window. To
resume, click "Yes" on the prompt dialog.
Only .PROBE (or .SAVE) partial data can be plotted during a pause. .PRINT data is not available. Also,
the output file can be inspected while the simulation is paused. A combination of .PROBE and
#AUTOPLOT commands is recommended to do partial plots.
5.12 Bias Voltages and Currents Display

The Schematic Editor View|Bias Voltages and Source Currents command allows you to display the
circuit DC operating point bias node voltages and currents for voltage and dependent (E, F, G and H)
sources on the schematic drawing. Only the voltages and currents for "top level" nodes and sources are
shown - display of subcircuit values is not supported.
The View|Bias Device Currents command shows the DC operating point bias currents for the following
devices: sources (E, F, G, H and V), resistors, diodes, BJTs (collector), MOSFETs (drain), JFETs (drain),
switches.
Before selecting the command, an operating point bias simulation of the circuit must be performed with
the simulator SAVEOPB option to generate and save the bias point data. The simulator saves the bias
data to a file with the same file name as the schematic but with the file name extension ".OPB". The
5-29
Figure 5.10 Circuit DC bias voltages and currents display
transient (.TRAN) and ac (.AC) analyses commands perform an operating point bias calculation by
default. For other analyses, the user must manually specify the .OP command to perform the operating
point simulation.
Note: the .OPTION SAVEOPB statement is automatically specified by the Schematic Editor if the
Simulation|Setup command is used to specify simulation analysis commands.
5.13 Simulation Output Files

TopSpice generates two kinds of output files: text and binary. The “.OUT” output file is a text file which
contains simulation information plus any data requested using the .PRINT commands. The .PRINT
command generates a tabular printout of the specified simulation results (this data is also used by the
TopView graphics post-processor program).
The “.SAV” file is the binary output file containing all the circuit variables (voltages, device currents, digital
node states and magnetic core states) generated by the .PROBE command. You must use the TopView
"Probe" option or specify #AUTOPLOT commands in the input file to display data in the “.SAV” file.
The SPICE *.OUT output file typically includes the following information:
1. Header showing simulation time, date, SPICE program version, temperature, and the title of the
circuit.
2. The listing of the input file.
3. Summary of circuit elements used, some of their parameter values, and node connections cross
reference.
4. Circuit node table (if requested) and element cross reference.
5. Device models and parameter values (temperature updated if necessary).
6. Tabulated data for .PRINT statement output variables. If more than one analysis was performed they
are printed in the following order:
• DC transfer curves (if requested)
• AC analysis (if requested)
• Transient analysis (if requested)
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SIMULATION
7. The "line plotter" graph for .PLOT statements follow the .PRINT statement output for each analysis
type.
8. Initial bias point calculation node voltages are printed before the tabulated data for AC and transient
analyses.
9. Any Fourier analysis results are printed after the transient analysis .PRINT statement output.
10. Simulation statistics data summary if requested.
11. Simulation elapsed time.
If your input file included more than one circuit, or you requested several simulation temperatures for
instance, the above output format will be repeated for each circuit or run.
The sample output file, EXAMPLE.OUT, included in the TopSpice distribution disk shows the results for
all the analyses available in TopSpice.
5.14 Convergence
SPICE calculates the DC solution, and the transient analysis solution at each time point, using a Newton-
Raphson algorithm. This is a numerical iterative method which continues until the following accuracy
criteria are reached:
1. The non-linear branch currents converge to within a tolerance of 0.1 percent or 1 picoamp between
iterations, whichever is larger.
2. The node voltages converge to within a tolerance of 0.1 percent or 1 microvolt between iterations,
whichever is larger.
3. The number of iterations exceeds the preset limits.
These are the program defaults suitable for most applications but the accuracy criteria can be changed by
the user if required using the .OPTIONS statement.
Although the algorithm used in SPICE has been found to be very reliable, one of these problems could
arise in some cases:
1. The initial solution is not the desired or correct solution. This often happens when simulating circuits
with metastable states. For example, a ring oscillator or flip-flop can have multiple initial states which
are all valid. In such cases, to help SPICE obtain the desired initial solution, the user can provide
initial guesses for some of the circuit node voltages by using the .IC or .NODESET statements, or
specify the “OFF” option on some of the active devices.
2. It fails to converge to a solution. In DC analysis, convergence problems are usually due to incorrect
use of circuit connections, element values, or model parameters. Other common causes are circuits
with very large positive feedback loops or unrealistic circuit operation. Circuits with large number of
semiconductor devices, especially BJTs and MOSFETs, can also cause convergence problems
because of the exponential I-V characteristics of the PN junctions.
TopSpice includes several state-of-art powerful alternative solution algorithms to solve circuits with
difficult convergence problems without user intervention. When there is a convergence failure, TopSpice
automatically switches to a different algorithm until all the alternate algorithms are exhausted.
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In extreme cases when all the algorithms fail to converge, and inspection of the circuit cannot determine
the cause of the convergence problem, the user might need to manually adjust the error tolerance and
convergence limit parameters using the .OPTIONS statement until convergence is achieved.
Note: the TopSpice convergence algorithms work best with the default program convergence parameter
values. If you have convergence problems simulating SPICE netlists imported from another SPICE
program, or older TopSpice versions, we recommend that you retry the simulation without any
.OPTIONS statement convergence parameters that might have been specified. Also, remove any
.NODESET or .IC statements unless they are needed to specify the initial state of the circuit.
5.14.1 DC Convergence
When there is a convergence failure in the initial DC bias point solution attempt, the program performs the
following steps:
1. Prints to the output file a non-convergence warning message.
2. Prints to the output file the node voltages at the last iteration. The node voltages that are printed are
not necessarily correct or even close to the correct solution. However, this information may help in
determining the section of the circuit causing the problem since frequently the voltages at those
nodes may be well outside the range of expected values.
3. Prints to the output file the list of nodes and devices which did not converge. This can be helpful in
pinpointing the circuit problem area.
4. Selects one of the DC convergence aid algorithms and retries the bias point calculation. This is
repeated until all the available convergence aid algorithms are exhausted.
TopSpice implements several convergence aid algorithms to help in the convergence of initial bias point
calculation if there is no convergence using the standard SPICE Newton-Raphson iterative technique.
The algorithms are applied in the following sequence:
Newton-Raphson Initial Iteration (ITL1)

⇓
Predictive Source-Stepping (ITL12)
⇓
Charge-Controlled Algorithm with CSHUNT=0 (ITL11)
⇓
GMIN-Stepping (ITL10)
⇓
Charge-Controlled Algorithm with CSHUNT Stepping (ITL11)
Depending on the circuit characteristics, GMIN-stepping might precede the charge-controlled algorithm in
some cases. The parameter in parenthesis is the algorithm iteration limit .OPTION statement parameter.
The user can disable or bypass any of the algorithms by setting its limit parameter to zero.
The source-stepping algorithm starts by setting all supply and independent source output values to zero.
At this point convergence should be obtained since all voltages are known. Then, the supplies are
increased in small steps until the source outputs are restored to their nominal values. Theoretically, this
should always provide convergence since it starts with a known solution. Unfortunately, there are cases
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SIMULATION
where either the circuit equations matrix is too ill-conditioned or there is an abrupt transition point during
the stepping of the supplies which prevents convergence.
Two different source-stepping algorithms are available in TopSpice. The “predictive source-stepping”
algorithm uses the previous source value solutions to extrapolate the next source step value initial
solution. The standard source-stepping algorithm uses the last source value solution as only an initial
guess for the next source step solution (ITL6 is the iteration limit .OPTIONS statement parameter for this
algorithm). The predictive algorithm is much faster and it is the default source-stepping algorithm used
except during DC sweeps. To completely disable source-stepping, both the ITL12 and ITL6 parameters
must be set to zero.
The "charge-controlled" convergence aid algorithm can solve circuits with very difficult convergence
properties. This proprietary state-of-art algorithm uses charge to predict and control the DC solution
iterations. The following .OPTION statement parameters control the "charge-controlled" algorithm: ITL11,
QCOPCALC and CAPSHUNT.
The GMIN-stepping algorithm increases GMIN, the minimum allowed value for semiconductor junction
conductance, until convergence is obtained or the maximum limit is reached. Then GMIN is restored to
the nominal value, or within an acceptable range, in steps using the previous solution as an initial guess.
The user also has the option to manually change the convergence criteria conditions for DC analysis
using the following parameters in the .OPTIONS statement:
RELTOL relative tolerance

ABSTOL absolute current tolerance
VNTOL absolute voltage tolerance
PIVTOL matrix pivot tolerance (determines allowed dynamic range)
ITL1 DC iteration limit for initial bias point
ITL2 DC transfer curve iteration limit
When performing a DC sweep, regenerative switching circuits, or circuits with positive feedback and
hysteresis, will probably have difficulty converging unless the "OFF" option is used for some of the
devices in the feedback path, or the .NODESET statement is used to force the initial state of the circuit to
the desired state. Even a better approach is not to use DC sweep in these cases. Instead perform a
transient analysis using very slow ramp sources (compared to any time constants in the circuit).
If there is a convergence problem with the "pivot not found" warning message in the output file, we
recommend increasing the GMIN option. The pivot warning is usually the result of an "ill-behaved"
solution conductance matrix.
5.14.2 Transient Convergence

Non-convergence during transient analysis can occur if the time-step control algorithm determines that
the required time step to obtain convergence is less than the minimum time step allowed. When this
happens, the simulator prints a "time step too small" error message and aborts the simulation.
The minimum allowed time step, T∆min, is determined by the maximum allowed time step, T∆max, as
follows:
T∆min = 10 × T∆max
-9
and
T∆max = TSTOP/50
5-33
TSTOP is the transient simulation length. T∆max could be limited to a smaller value for circuits with no
energy storage elements, SIN sources and transmission lines. If the maximum step value option on the
transient analysis command is specified by the user, T∆max is limited to this value.
These are some common causes of transient convergence problems:
1. Unrealistic device parameter values. This is usually the result of a typo or use of incorrect units when
specifying a parameter.
2. Circuits with high feedback loop gain and very small time constants (too little capacitance).
3. Oscillation or ringing.
4. Transmission lines with very short delays.
5. Very large capacitors or semiconductor device capacitances.
6. Unrealistic circuit operation. For example, if you try to drive an ideal inductor with a fast current pulse
or step, extremely large and unrealistic inductor voltages might be required which would not be
possible with real inductors. To avoid this, the inductor losses present in a real inductor must be
included in the simulation.
7. Large ratio of fastest signal change to total simulation time, especially if it involves circuits with large
feedback gain loops. Specifying a smaller maximum time step size often solves the problem.
8. Inductive spikes. Ideal inductors with infinite bandwidth can cause very large and fast voltage spikes.
To minimize this, add a snubbing resistance in parallel to the inductor.
If you determine the convergence problem is not caused by any of the above conditions or the problem
persists, you can try to manipulate some of the convergence parameters.
The following parameters in the .OPTIONS statement control transient analysis convergence criteria:
CHGTOL absolute charge tolerance

TRTOL truncation error factor
METHOD integration method selector
MAXORD Gear integration order
MU trapezoidal integration control
ITL3 minimum transient iteration limit
ITL4 time point iteration limit
ITL5 transient analysis total iteration limit
We recommend you try increasing ITL4 to 200 first.
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DIGITAL SIMULATION
CHAPTER
6 DIGITAL SIMULATION
6.1 Introduction
In logic simulation, electrical behavior is modeled at the logic gate level and not at the transistor level.
Rather than dealing with voltages and currents at signal nodes, discrete logic states are defined, and
simple Boolean and integer operations are used to determine the new logic value at each node and
logical time step. Because Boolean and integer operations are generally the fastest operations available
on a digital computer, logic simulation is orders of magnitude faster than analog simulation.
The logic simulator implemented in TopSpice is fully event-driven. Timing models with separate
propagation delays for each logic level transition are assigned to all the logic elements. The digital section
of the circuit is only evaluated when a logic event takes place during the simulation. This technique is
typically more than 100 times faster than the most efficient forms of electrical (analog) analysis. Since
logic simulation is most efficiently handled in terms of discrete time steps, TopSpice uses independent
time steps for simulating the analog and digital portions. Logic simulation only provides a first-order timing
information. However, the use of discrete gate delays is needed for the detection of hazards, glitches, and
race conditions. Logic simulation also has the advantage of generating information regarding any illegal
states or conflicting conditions.
A true event-driven logic simulator with propagation delay modeling is essential to correctly represent and
simulate digital finite-state machines. Many other SPICE programs claiming mixed-mode simulation
capability actually use analog transfer functions to model digital gates and logic functions. Although this
approach is acceptable for simulating combinatorial logic circuits, it will not give the correct transient
response results for finite-state machines because it does not include any “memory” effects.
TopSpice implements the digital element U to describe logic circuits. Each logic element performs a
certain digital primitive function. The digital primitive functions can be combined in subcircuits to create
macro models for other digital components. Figure 6.1 is the schematic for a sample mixed-mode circuit
with analog and digital components. In this case we use both digital primitives and the library subcircuit
model for the SN7404 gate. The simulated results are displayed as both analog and digital waveforms in
Figure 6.2.
Figure 6.1 Sample analog/digital circuit
6-1
Figure 6.2 Simulated analog and digital waveforms for the circuit of Fig. 6.1
6.2 Digital Circuit Netlist

The general syntax rules for defining the digital portion of a circuit in TopSpice are essentially the same
as that for analog circuits. The only difference is that for the digital element U, you must specify a digital
primitive function after the element name, optional parameter/s, then node names, and the model name is
optional. For example,
U11 AND(3) Out In1 In2 In3
This logic element statement specifies a three input AND gate with default propagation delays.
The convention in TopSpice for the order of the node list is output nodes first, followed by mode (control)
nodes if any, and then input nodes. Node names for digital nodes follow the same rules as for analog
nodes. Any node on a U element node list is automatically defined to be a digital node. If the same node
name appears in both analog and digital elements, it becomes an analog/digital (A/D) interface node. The
simulator automatically inserts either an analog-to-digital or digital-to-analog interface element at every
A/D node unless one has been inserted by the user.
TopSpice implements several predefined digital global nodes. These nodes have fixed logic levels (i.e.:
they are not affected by any digital gate output connected to it). The following predefined global nodes are
available:
$D_LO Logic state 0 signal

$D_HI Logic state 1 signal
$D_X Logic state X signal
$D_NC Digital no-connection node (floating)
_D_LO Logic state 0 signal
_D_HI Logic state 1 signal
_D_X Logic state X signal
_D_NC Digital no-connection node (floating)
Figure 6.3 shows the complete netlist and circuit file for the mixed-mode circuit in Figure 6.1.
6-2
DIGITAL SIMULATION
MIXED-MODE RING OSCILLATOR

* Digital section
* Set initial states on inverters to avoid getting stuck in metastable
* state
U1 INV 2 1 IS=1
U2 INV 3 2 IS=0
X3 3 out SN7404 ;TTL inverter from library
* Analog section
* Feed back resistor and capacitor for oscillation frequency of about
* 250MHz
R1 1 2 330
C1 1 3 160pF
* Set analog initial conditions

.IC V(1)=0 V(3)=0
.tran 50ns 1US

.print tran/all V(1) V(2) D(out) ;print all calculated points
.END
Figure 6.3 Sample analog/digital circuit file
6.3 Logic States

Logic simulation analyzes the response of a digital circuit in terms of logic states instead of voltages or
currents as in the case of analog simulation. TopSpice is a nine-state logic simulator. That is a digital
node can be in any one combination of the following logic states:
State Logical Meaning

0 False (low, off)
1 True (high, on)
X Unknown
and driving strength (impedance) states:
State Driving strength

S Strongest (low impedance)
T Soft (transmission gates)
Z Weakest (high impedance)
TopSpice uses the "wire-AND" convention in determining the state of a node with two or more outputs
driving it. If all the outputs are at the same driving strength, the outcome is simply the Boolean AND
operation of all the outputs. If they are at different driving strengths, the signal with the strongest state
determines the node state.
The initial circuit logic states are determined by the simulator during the DC operating point calculation. If
the circuit contains multiple A/D interface "levels", the operating point calculation is iterated until all the
logic states are propagated. The iteration limit is set by ITL9. The default is 20. If your circuit longest logic
path has more than 20 A/D levels you might need to increase this value so the proper logic states are
fully propagated during the DC op calculation. Some oscillator type circuits containing A/D interfaces in
the feedback loop might require a setting of ITL9=0, which only sets the "top level" logic states, to start
oscillating.
The user can also manually set the initial state of any logic node by specifying the initial state parameter
(IS) value for any digital element output node or by labeling a digital node with one of the predefined fixed
logic state node names.
6-3
6.4 Logic Simulation Time Step

Unlike the analog simulator, the logic simulator uses discrete time steps. The minimum time step that the
logic simulator can take is the logic time step unit. All logic events happens at integer multiples of this unit
step.
DIGFREQ sets the logic simulator maximum frequency which is the reciprocal of the logic time step unit.
This value should be higher than the reciprocal of the minimum logic element delay.
The logic simulator uses 32-bit integer operations which limits the maximum number of logic steps to
about 3 billion. To avoid exceeding this limit, the simulator adjusts DIGFREQ to increase the logic time
step if required. If the user specified logic step (1/DIGFREQ) exceeds the minimum gate delay, a warning
is issued and gate delays less than 1/DIGFREQ are increased to 1/DIGFREQ. This allows the user to run
long transient analysis of circuits with digital elements by just specifying a lower DIGFREQ value instead
of specifying new gate delays for all the needed digital models. This does not apply to CLOCK and DATA
elements. For example, to simulate a circuit with digital elements to 10 seconds, add the following
statement
.OPTION DIGFREQ=100MEG
This increases all the digital model delays if necessary to at least 10ns.
6.5 Logic Simulation Errors and Glitches

Unlike the analog simulation, for the digital section of the circuit “floating nodes” are allowed. Hence, a
digital node can only have one connection to it. However, for floating input nodes the simulator will print a
warning message to the output file since these nodes are set to the “X” (unknown) state. Also, input
nodes would not normally be left floating and would most likely be a connection error. There is no
warning message for floating output nodes since their state is determined by the gate output connected to
it.
If the input of a logic gate changes faster than its propagation delay, the logic simulation will no longer
propagate the input to the output as with real gates. In another words, a gate cannot be operated faster
than its propagation delay. Under these conditions, a "glitch suppression" warning message is printed to
the output file. However, there is really nothing being "suppressed" here, and the logic simulation is
correct. The warning message is to help the user debug the circuit.
The solution when a logic glitch happens is either to use faster gates (reduce the gate model propagation
delays) or slow down your signal changes. It is also possible you might have a race condition in your
circuit. But again, in real life either you would not see anything or your circuit would operate erratically.
6.6 Digital Primitives

Digital logic elements are used to describe the digital portion of the circuit and they are used exclusively
by the logic simulator. A logic element can only be connected to "digital" nodes. If a digital element node
is connected to an analog node, TopSpice automatically inserts an analog/digital interface element at that
node. The digital elements do not have any analog supply terminals. Their analog output is determined by
the interface element supply voltage.
Digital primitive element general syntax:
Uname function[(opt1[,opt2])] <node list> [model [iomodel]] [IS=state ...] [parameters]
function Specifies a digital primitive function. For the Schematic Editor U symbols, the function
is determined by the symbol name.
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DIGITAL SIMULATION
opt1 and opt2 Options specific to each function type. For the Schematic Editor U symbols, the
options, if any, are specified on the symbol name.
<node list> Follows the convention output nodes first, followed by any mode set nodes and the
input nodes last. Note: the U element digital nodes cannot be connected directly to
the analog ground node 0.
model Optional model name. The model specifies the device propagation delay parameters
are defined. If not given the default model parameter values are used.
iomodel Optional DTOA interface model name to be used when TopSpice inserts a
digital/analog interface element to the output nodes of the digital element. If not given
the default DTOA model is used. If iomodel is specified you must also specify model
before it.
parameters Optional device parameters specific to each function type.
IS Optional device initial states specification for either the output node states or the
memory cell states (RAM and ROM devices).
The following built-in digital primitive functions are available:
Function Description Model

ADD N-bit full adder UALU
AND AND gate with two or more inputs UGATE
BUF Buffer gate UGATE
BUF3 Tri-state buffer gate U3GATE
CLOCK Periodic stimulus source USTIM
COMP N-bit magnitude comparator UALU
COUNT N-bit universal counter UCOUNT
DATA Arbitrary waveform stimulus source USTIM
DEC N bits-to-N line decoder USEL
DELAY Delays signal by user specified time UGATE
DFF Edge-triggered D flip-flop UEFF
DIVN Divide-by-N counter UCOUNT
DLATCH Gated D flip-flop (latch) UGFF
INV Inverter UGATE
JKFF Edge-triggered JK flip-flop UEFF
MUX One of n-bit multiplexer USEL
NAND NAND gate with two or more inputs UGATE
NOR NOR gate with two or more inputs UGATE
OR OR gate with two or more inputs UGATE
PARITY Parity generator/checker UALU
PENC N-line priority encoder USEL
PSREG N-bit universal shift register USREG
PULSE Pulse generator/multivibrator UPULSE
RAM Static random-access memory URAM
ROM Read-only memory UROM
RSFF Gated RS flip-flop UGFF
SREG N-bit shift register (serial in/parallel out) USREG
6-5
SREGP N-bit parallel in/serial out shift register USREG

SRFF Gated SR flip-flop UGFF
SRLATCH Gated SR AND-OR type flip-flop latch UGFF
XOR Exclusive OR with two or more inputs UGATE
XNOR Exclusive NOR with two or more inputs UGATE
Examples:
U1 CLOCK clk TPER=100ns 0 0 20ns 1 50ns 0 75ns 1

USET DATA ina DATA 0 0 20ns 1 50ns 0 100ns 1
U3 AND OUT 1 A
U4 NOR(3) 3 A B C FAST IS=1
U5 COUNT(10,3) Q2 Q1 Q0 co $D_LO cl ld $D_HI clk 4 3 2 IS=1 0 0
U6 JKFF A B 1 2 CLK DATA 10 TTLFF TTLFFDA
The first two examples are digital signal sources (stimulus generators). U3 is a 2-input AND gate. Next is
a 3-input NOR gate with an initial output state of logic 1. U5 is an edge-triggered JK flip-flop with timing
model TTLFF and digital-to-analog model TTLFFDA.
Note: Although the TopSpice U element syntax looks similar to that used by PSpice, they are
incompatible for the following differences:
1. PSpice™ requires analog power supply nodes on every U device.

2. The ordering of nodes is different.
3. The device and I/O model specifications are not optional in PSpice™.
The following subsections describe all the available digital primitive functions. For detailed descriptions of
the specific syntax rules, see the TopSpice Simulator Reference.
6.6.1 Digital Primitive Models

A digital model statement defines the switching characteristics (propagation delays) for a class of logic
devices. The following digital models are available:
Model Description
UALU adders, comparators
UCOUNT counters
UEFF edge-triggered flip-flops
UGATE Boolean gates
U3GATE tri-state gates
UGFF gated flip-flops (latches)
UPULSE pulse generators/multivibrators
URAM random-access memories (static RAM)
UROM read-only memories (ROM)
USEL multiplexers/decodes/encoders
USREG shift registers
USTIM digital stimulus sources
Examples:
.MODEL FASTGATE UGATE (TPLH=2ns TPHL=1.5ns)

.MODEL FFTYPE1 UEFF (TPCLKLH=20ns)
6-6
DIGITAL SIMULATION
6.6.2 Stimulus Generators

Two types of stimulus generators are provided: CLOCK and DATA.
The CLOCK stimulus generator digital primitive is used to provide a periodic digital waveform input.
Examples:
UCLKA CLOCK A CLOCK TPER=150ns 0 0 40ns 1 100ns 0

USIG CLOCK(2) 11 7 TPER=1us (0,1) (500ns,0)
In the second example above, the two outputs are identical. Also, as shown, you may use parenthesis
and commas to make the waveform specification easier to read.
The DATA stimulus generator digital primitive is used to provide an arbitrary digital waveform input.
Examples:
URESET DATA RST DATA 0 1 50ns 0 100ns 1 120ns 0

U1 DATA(2) A1 B1 (0,0) (1us,1) (3us,0) (5us,1)
In the second example above, the two outputs are identical. Also, as shown, you may use parenthesis
and commas to make the waveform specification easier to read.
6.6.3 Boolean Gates

All the standard Boolean gates are available as built-in logic functions. In addition, arbitrary number of
inputs may be specified for each gate.
The following Boolean gates are available:
Function Option Default Description

AND #inputs 2 AND gate
BUF #gates 1 Buffer array
INV #gates 1 Inverter array
NAND #inputs 2 NAND gate
NOR #inputs 2 NOR gate
OR #inputs 2 OR gate
XOR #inputs 2 Exclusive OR gate
XNOR #inputs 2 Exclusive NOR gate
The gate timing model (propagation and switching delay parameters) can be specified on a .MODEL
statement with the UGATE model type.
Examples:
U1 AND 3 a b
U2 BUF(2) Q1 Q2 3 4 IS=0 1
U3 XOR(3) Q A1 A2 A3 ECLGATE
.MODEL ECLGATE UGATE (TPLH=100ps TPHL=200ps)
6-7
6.6.4 Tri-State Gates

Tri-state gates have output control inputs. When the output is disabled, the tri-state gate output goes to a
high-impedance (“Z”) state regardless of the input state.
The following tri-state gates are available:
Function Option Default Description

BUF3 #gates 1 Buffer array
The gate timing model (propagation and switching delay parameters) can be specified on a .MODEL
statement with the U3GATE model type.
Examples:
UOUT BUF3(2) out1 out2 enable in1 in2

U1 BUF3 21 sel in TRIGATE
.MODEL TRIGATE U3GATE (TPLH=1.5ns TPHL=5ns)
6.6.5 Delay Gate

This function implements a true delay. Unlike propagation delay, all input state changes are kept in
memory until output time even if the changes happen faster than the delay time. However, events
separated by less than the simulator logic step are ignored. Multiple identical gates can be specified as
an option.
The model type for this function is UGATE. However, the model parameters are ignored. The delay must
be always specified as a device parameter.
Example:
U1 DELAY q A1 TD=2.5us
U1 DELAY(3) Q1 Q2 Q3 D1 D2 D3 TD=5ns
6.6.6 Flip-flops
TopSpice supports both edge-triggered and gated flip-flops (a.k.a. latches). Edge-triggered flip-flops
change state when the clock input changes – either on the falling or rising clock edge. Gated flip-flops
follow the data input as long as the clock (gate) input is high (enabled). When the clock is low (disabled),
the output remains unchanged. The following flip-flop types are available:
Type Description
DFF D type, positive-edge triggered
JKFF JK type, negative-edge triggered
DLATCH D gated latch
RSFF R-S gated latch (NAND type)
SRFF S-R gated latch (NAND type)
SRLATCH S-R gated AND-OR type latch (no invalid states)
The state of the flip-flops must be properly initialized at the start of the simulation. By default, all flip-flops
are initialized to the unknown “X” state. Until they are initialized to a known state, their outputs remain in
the X state. There are two ways to initialize flip-flops: apply the proper logic signal to the “preset” (or
“set”) or the “clear” (or “reset”) control input; set the initial state device parameter IS value.
The flip-flop timing model (propagation and switching delay parameters) can be specified on a .MODEL
statement with the UEFF (edge-triggered) or UGFF (gated) model type.
6-8
DIGITAL SIMULATION
Examples:
U1 DFF Q1 Q2 SETB CLRB CLK IN IS=0

U2 JKFF A B 1 2 CLK DATA 10 TTLFF
.MODEL TTLFF UEFF (TPCLKLH=3ns TPCLKHL=2.3ns)
U3 DLATCH Q1 Q2 SETB CLRB CLK IN IS=0
U4 RSFF A B 1 2 CLK DATA 10 CMOSFF
.MODEL CMOSFF UGFF (TPCLKLH=9ns TPCLKHL=11ns)
6.6.7 RAM Static Random-Access Memory

TopSpice offers a built-in random-access memory (RAM) function. It supports arbitrary memory sizes and
word widths. The total number of memory cells is
#outputs X 2#address
(e.g.: for 2 outputs and 4 address lines it is 32). Because the RAM is modeled using logical expressions
and integer arrays, there is no significant computational penalty related to increasing memory size.
By default, RAM memory cells are initialized to unknown states at the start of the simulation. To initial the
RAM with the desired data, the initial state device parameter IS must be specified with the states for all
the memory cells in the proper word format.
The RAM timing model (access time and propagation delay parameters) can be specified on a .MODEL
statement with the URAM model type.
Example:
U1 RAM(2,3) out1 out2 ce 15 a2 a1 a0 1 2 SRAM

+ IS = 0 0 ;addr. 0
+ 1 1 ;addr. 1
+ 0 1 ;addr. 2
+ 1 0 ;addr. 3
+ 0 0 ;addr. 4
+ 0 0 ;addr. 5
+ 0 1 ;addr. 6
+ 1 1 ;addr. 7
.MODEL SRAM URAM (TPADLH=2.5ns TPADHL=1.8ns)
6.6.8 ROM Read-Only Memory

TopSpice offers a built-in read-only memory (ROM) function. It supports arbitrary memory sizes and word
widths. The total number of memory cells is
#outputs X 2#address
(e.g.: for 3 outputs and 2 address lines it is 12). Because the ROM is modeled using logical expressions
and integer arrays, there is no significant computational penalty related to increasing memory size.
By default, ROM memory cells are initialized to unknown states at the start of the simulation. To initial the
ROM with the desired data, the initial state device parameter IS must be specified with the states for all
the memory cells in the proper word format.
6-9
The ROM timing model (access time and propagation delay parameters) can be specified on a .MODEL
statement with the UROM model type.
Example:
U1 ROM(3,2) out1 out2 out3 25 a1 a0 ROM12

+ IS = 0 0 0 ;addr. 0
+ 0 0 1 ;addr. 1
+ 1 0 1 ;addr. 2
+ 0 1 1 ;addr. 3
.MODEL ROM12 UROM (TPADLH=25ns TPADHL=18ns)
One important application of ROMs is the implementation of logic truth tables. For example, the following
ROM implements a BCD-to-decimal decoder:
U1 ROM(10,4) 1 2 3 4 5 6 7 9 10 11 $D_HI 12 13 14 15
* output states address
* 0 1 2 3 4 5 6 7 8 9 DCBA
+ IS= 0 1 1 1 1 1 1 1 1 1 ;0000
+ 1 0 1 1 1 1 1 1 1 1 ;0001
+ 1 1 0 1 1 1 1 1 1 1 ;0010
+ 1 1 1 0 1 1 1 1 1 1 ;0011
+ 1 1 1 1 0 1 1 1 1 1 ;0100
+ 1 1 1 1 1 0 1 1 1 1 ;0101
+ 1 1 1 1 1 1 0 1 1 1 ;0110
+ 1 1 1 1 1 1 1 0 1 1 ;0111
+ 1 1 1 1 1 1 1 1 0 1 ;1000
+ 1 1 1 1 1 1 1 1 1 0 ;1001
+ 1 1 1 1 1 1 1 1 1 1 ;1010
+ 1 1 1 1 1 1 1 1 1 1 ;1011
+ 1 1 1 1 1 1 1 1 1 1 ;1100
+ 1 1 1 1 1 1 1 1 1 1 ;1101
+ 1 1 1 1 1 1 1 1 1 1 ;1110
+ 1 1 1 1 1 1 1 1 1 1 ;1111
6.6.9 N-Bit Shift Registers

TopSpice offers built-in shift register logic functions. The user can specify shift registers with an arbitrary
number of bits (stages). Because the shift registers are modeled using logical expressions and integer
arrays, there is no significant computational penalty related to increasing number of bits.
The following shift registers types are available:
Type Option Default Description

PSREG #bits 4 Parallel load universal. This is a universal shift register offering
complete flexibility in data input (parallel or serial load), shifting (left or
right) and output mode (parallel or serial). It allows the implementation
of any arbitrary shift register. For both types, a shift is done on the
positive edge of the clock.
SREG #bits 4 Serial in/parallel out. This is a simple serial in with parallel out shift
register. It performs a right shift at every clock pulse.
SREGP #bits 4 Parallel in/serial out. This is a simple parallel in with serial out only shift
6-10
DIGITAL SIMULATION
register. It performs a right shift at every clock pulse.
By default, the shift register stages (bits) are initialized to unknown states at the start of the simulation.
To initial them with the desired states, the initial state device parameter IS must be specified with the
states for all the stages. For the PSREG, this can also be done using the parallel data load function.
The shift register timing model (propagation and switching delay parameters) can be specified on a
.MODEL statement with the USREG model type.
Examples:
U1 SREG(4) q3 q2 q1 q0 $D_HI clk din IS=1 0 1 0

U2 PSREG(3) q2 q1 q0 $D_HI s1 s0 clk din $D_LO d2 d1 d0 IS=1 1 0
U3 SREGP(3) q clr load clk sin $D_HI $D_LO $D_HI IS=0 1 1
.MODEL CMOSREG USREG (TPLH=5ns TPHL=12ns)
The first example defines a 4-bit shift register with initial state value of 8. The last two examples are 3-bit
parallel load shift registers with initial state value of 6.
6.6.10 N-Bit Counters

TopSpice offers a built-in counter logic function. The user can specify counters with an arbitrary number
of bits (stages). Because the counter is modeled using logical expressions and integer arrays, there is no
significant computational penalty related to increasing number of bits.
The following counter types are available:
Type Options Default Description

COUNT count mode, 2, 4 Universal counter. This is a universal counter function with
an arbitrary number of bits (stages), binary or decade
#bits
count mode, up/down control, parallel data load, ripple
carry output and parallel output.
DIVN N 2 Divide-by-N counter. This is a simple divide-by-N counter
with serial input and output only. This function is
convenient when specifying large N divide values.
By default, the counter stages (bits) are initialized to unknown states at the start of the simulation. To
initial them with the desired states (count), the initial state device parameter IS must be specified with the
states for all the stages. This can also be done using the parallel data load function.
The counter timing model (propagation and switching delay parameters) can be specified on a .MODEL
statement with the UCOUNT model type.
Examples,
U1 COUNT(10,3) out2 out1 out0 co $D_LO cl ld $D_HI clk 4 3 2 IS=1 0 0

U4 DIVN(4) q clr hold clk
.MODEL COUNTER UCOUNT (TPCQLH=25ns TPCQHL=18ns)
The first example defines a 3-bit decade up counter and sets its initial count value to 4. The second
defines a divide-by-4 counter.
6-11
6.6.11 Decoders, Encoders and Multiplexers

TopSpice offers built-in decoder, encoder and multiplexer (selector) logic functions. The user can specify
these functions with an arbitrary number of bits or lines. Because they are modeled using logical
expressions, there is no significant computational penalty related to increasing number of bits or lines.
The following multiplexer types are available:

DEC #lines 2 N-bit to N-line decoder. This is a N-bit to N-line decoder for selecting
the output line specified by the binary value at the select inputs. The
number of select inputs must be equal to the smallest exponent of
power of 2 which evaluates to the number of output lines or more.
For example, for 8 lines 3 select inputs are needed, and for 3 lines 2
select inputs. The output mode control allows for high or low
selected line output.
MUX #lines 4 N-line multiplexer. This is a N-line multiplexer for selecting the data
input line specified by the binary value at the N-bit select inputs. The
number of select inputs must be equal to the smallest exponent of
power of 2 which evaluates to the number of input lines or more. For
example, for 8 lines 3 select inputs are needed, and for 3 lines 2
select inputs.
PENC #lines 2 N-line priority encoder. This is a N-line to N-bit priority encoder to
binary encode the selected the input line value. The number of
output bits must be equal to the smallest exponent of power of 2
which evaluates to the number of input lines or more. For example,
for 8 lines 3 output bits are needed, and for 3 lines 2 output bits. The
priority mode control allows for high or low selected line input.
The timing model (propagation and switching delay parameters) can be specified on a .MODEL statement
with the USEL model type.
Examples:
U4 DEC(4) Q0 Q1 Q2 Q3 $D_HI E hold s1 s0

U1 MUX(4) out str s2 s1 d3 d2 d1 d0
U9 PENC(8) Q2 Q1 Q0 EO $D_HI D0 D1 D2 D3 D4 D5 D6 D7
.MODEL MUX USEL (TPLH=35ns TPHL=28ns)
6.6.12 Arithmetic Logic Units

TopSpice offers built-in arithmetic logic unit (ALU) functions. The user can specify ALU functions with an
arbitrary number of bits. Because the ALU functions are modeled using logical expressions, there is no
significant computational penalty related to increasing number of bits.
The following ALU types are available:

ADD #bits 4 Full adder. This is a full adder that adds a N-bit number A to
another N-bit number B, generating a N-bit sum plus a carry bit.
Adders can be “cascaded” using the carry-in input to accept the
carry-out from the previous adder.
6-12
DIGITAL SIMULATION
COMP #bits 4 Magnitude comparator. This is a magnitude comparator that

compares a N-bit number A with another N-bit number B and
determines their relative binary values. The outputs for A<B, A=B
and A>B provide the result of the comparison.
PARITY #bits 4 Parity generator/checker. This is a N-bit parity generator and
checker. The even output goes high if the number of high inputs is
even. The odd output goes high if the number of high inputs is odd.
The ALU timing model (propagation and switching delay parameters) can be specified on a .MODEL
statement with the UALU model type.
Examples:
U1 ADD(2) s1 s0 co a1 a0 b1 b0 ci
U1 COMP(3) c2 c1 c0 a2 a1 a0 b2 b1 b0 ALUMOD
U5 PARITY(4) even odd d0 d1 d2 d3
.MODEL ALUMOD UALU (TPLH=45ns TPHL=28ns)
The first example defines a 2-bit adder, the second defines a 3-bit magnitude comparator and the third a
4-bit parity checker.
6.6.13 PULSE Pulse Generator and Multivibrator

TopSpice offers a built-in pulse generator (PULSE) function. The PULSE function is most useful for
modeling monostable multivibrators. It offers options for retriggerable mode operation, internal/external
pulse timing, and positive or negative edge trigger inputs.
The PULSE timing model (access time and propagation delay parameters) can be specified on a
.MODEL statement with the UPULSE model type.
The following example implements a model for the 74HC123 retriggerable monostable multivibrator:
.SUBCKT 74HC123 REXT CEXT CLR A B Q QB

*
U1 AND BC B CLR HC74I HC74UIO
* Retriggerable mode operation

U2 PULSE Q QB DIS EXT EDIS $D_HI CLR A BC HC74PULSE HC74UIO IS=0 1 0
S1 REXT CEXT DIS 0 SW1

E1 VEXT 0 REXT CEXT 1
O1 ATOD VEXT 0 $G_DPWR EDIS HC74UIOEDIS
O2 ATOD VEXT 0 $G_DPWR EXT HC74UIOPULSE
.MODEL SW1 VSWITCH (RON=10 ROFF=10MEG VOFF=0.2 VON=1)
.MODEL HC74UIOEDIS ATOD (VLMAX%=0.1 VHMIN%=0.2 RIN=10MEG RSRC=10MEG)
.MODEL HC74UIOPULSE ATOD (VLMAX%=0.1 VHMIN%=0.6 RIN=10MEG RSRC=10MEG)
.ENDS 74HC123
6.7 Digital Macro Models

By combining the simulator built-in digital primitives in a subcircuit, the user can create custom macro
models of more complex digital devices. The following example implements the 4-bit binary counter
74LS193 chip:
6-13
.SUBCKT 74LS193 1 2 3 4 5 6 7 9 10 11 12 13 14 15
* B QB QA DN UP QC QD D C LOAD CO BO CLR A
U1 INV CLRB 14
U2 AND CLK 4 5
U3 XOR UD1 4 5
U4 AND SET 5 UD1
U5 AND RST 4 UD1
U6 RSFF UD UDB $D_HI CLRB $D_HI RST SET IS=0
U7 COUNT(2) 7 6 2 3 RCO UD CLRB 11 11 CLK 9 10 1 15 LS74CNT LS74DA
* BO
U8 OR(5) 13 7 6 2 3 4
* CO
U9 INV UPB 5
U10 NAND(5) 12 7 6 2 3 UPB
.ENDS 74LS193
A digital macro model can also include analog elements besides digital primitives such as the following
CD4016 bilateral switch model with analog control input and supply pins:
.SUBCKT CD4016A 1 2 13 14
* in/out out/in ctrl VDD
O1 ATOD 13 0 14 18 AD4016
.MODEL AD4016 ATOD (VLMAX=0.7 VHMIN%=0.7 RIN=1E12 RSRC=1E12)
U1 BUF 15 18 CMOSBUF
O1 DTOA 16 0 17 15 CMOSUIO
V1 17 0 5V
S1 1 2 16 0 SW4016
.MODEL SW4016 VSWITCH (VOFF=0.7 VON=3.5 RON=200 ROFF=100G)
.ENDS CD4016A
The TopSpice model library includes many macromodels for several standard logic families including
TTL, CMOS and ECL.
6.8 Analog/Digital Interface

In mixed-mode circuits, nodes may be connected to analog elements only, digital elements only, or to
both analog and digital elements. For the latter case, TopSpice automatically inserts an analog/digital
(A/D) or digital/analog (D/A) interface element, O, to perform the function of translating analog voltage
and impedance values to logic states and driving impedance levels, or vice versa. In addition, a global
digital supply voltage source and node are added to power the analog side of the interface element. The
value of this voltage source (default is TTL 5V) determines the analog input/output range. This process
effectively breaks the circuit into purely analog and digital sections. The following rules are used to
determine if the interface node is A/D or D/A:
1. If only digital input terminals are connected to the digital node, an A/D interface is added.
2. If there is one or more digital output terminals connected to the digital node, a D/A interface is added.
These rules are based on the assumption that a digital input is a high impedance path and the output
impedance of a digital element is low compared to the analog element impedances connected to it. If
these assumptions are not valid, one should manually insert the appropriate interface elements.
The characteristics of the interface are determined by the interface element model parameter values and
the digital supply voltage value. The interface element default values are listed at the end of this section.
The DTOA element is not a voltage source. Instead, the output is a resistive divider network connected
between the analog high (digital supply) and low reference (ground) voltage nodes. Hence, the output
6-14
DIGITAL SIMULATION
Figure 6.4 Analog/digital interface element equivalent circuits
levels and current drive capability are determined by the logic high and low resistances specified on the
DTOA model.
The following naming rules are used to name the added interface elements, nodes and global supply
voltage:
A/D interface element O<node name>

Analog side of A/D node same node name
Digital side of A/D node "$AD" or "$DA" is appended to node name
Global digital supply node $G_DPWR
Default model name ATOD or DTOA
Global digital supply V$G_DPWR
One can override the default interface model parameter values by one of these methods:
1. Specify an interface model name on the digital U element statement and the corresponding .MODEL
statement. This can be an ATOD, DTOA or UIO model type.
2. Add a model definition statement for ATOD and/or DTOA in the input file with the new model
parameter values.
3. Insert interface elements manually with different models.
To change the global supply voltage value, add the following statement
.OPTION DIGVPWR=value
value is the supply voltage value. If the output of a user specified voltage source is already connected to
the node $G_DPWR, the digital supply V$G_DPWR is not added.
By default, A/D interface (both ATOD and DTOA) device global low side nodes are connected to the
analog ground node 0. To specify a nonzero voltage for the low side, add the following statement
.OPTION DIGVGND=value
6-15
If value is nonzero, a source named V$G_DGND is added by the program and its output connected to the
global node $G_DGND.
CMOS 4000 series interface definition example:
.MODEL CMOSAD ATOD (VLMAX%=0.16 VHMIN%=0.6 RIN=1E12 RSRC=1E12)

.MODEL CMOSDA DTOA (RLO0=200 RHI0=10MEG RLO1=10MEG RHI1=200
+ RLOX=1K RHIX=1.5K RLOZ=10MEG RHIZ=10MEG
+ TSW0=10NS TSW1=10NS TSWX=10NS TSWZ=10NS)
.MODEL CMOSUIO UIO (VLMAX%=0.16 VHMIN%=0.6 RIN=1E12 RSRC=1E12

+ RLO0=200 RHI0=10MEG RLO1=10MEG RHI1=200
+ RLOX=1K RHIX=1.5K RLOZ=10MEG RHIZ=10MEG
.MODEL CMOS UGATE (TPLH=50NS TPHL=40NS)
Both analog reference nodes, lnode and hnode, must be connected to either the analog ground or the
output of a V independent voltage source.
If the hnode digital supply voltage is less than lnode analog ground, the logic voltage closest to the hnode
voltage is assumed to be logic low (0) and voltage closest to lnode to be logic high (1) values. In another
workds, the logic values are inverted with respect lnode.
The following example shows the A/D interface specification for ECL logic which takes advantage of this
feature:
VEE VEE 0 –2
U1 DATA D1 0 0 10ns 1 20ns 0 30ns 1
U3 INV OUT D1
R1 OUT VEE 50
O1 DTOA OUT 0 VEE QA ECLDA
O2 DTOA OUT 0 VEE QB ECLDA
.MODEL ECL10KDA DTOA (RLO0=280 RHI0=1K RLO1=30 RHI1=100K
+ RLOX=50 RHIX=100 RLOZ=1MEG RHIZ=1MEG
Note: this element is a simulation artifact to interface the analog and logic simulators. It should only be
used for the stated purpose, and not as a “real” circuit element to perform any other function. For
example, you cannot control the analog reference node voltages during the operation of the circuit
to change the output levels.
6-16
ANALOG BEHAVIORAL MODELING
CHAPTER
7 ANALOG BEHAVIORAL MODELING
7.1 Introduction
Analog behavioral modeling (ABM) is the method of modeling components or system blocks in terms of
the observed output responses to applied inputs. It is equivalent to defining a system in terms of its
transfer function. ABM is a powerful modeling technique offering several advantages:
• Implementation of new device models without modifying the simulator.

• Functional block (black-box) modeling of complex systems and high-level functions.
• Description of a system or circuit at several different levels of abstraction during the design process.
• Faster simulation of non-critical sections of a circuit.
With TopSpice analog behavioral modeling capabilities, transfer functions may be described in any of the
following methods:
Method Description
CAPACITOR Capacitance and charge expressions of voltages, currents, time, etc.
FREQ Frequency response table and s-parameters table.
LAPLACE Laplace transform. It supports arbitrary expressions of the complex frequency s.
POLY Polynomial equations of voltages and currents. This is a standard SPICE feature. It is
also computationally the fastest.
RESISTOR Resistance expressions of voltages, currents, time, etc.
TABLE Look-up table.
VALUE Arbitrary expressions of voltages, currents, time, etc.
TopSpice implements the ABM features as extensions to the dependent voltage source E element and
the dependent current sources G element. The ABM options are accessed by specifying one of the above
method keywords in the E or G element statement (POLY is also available for F and H sources).
TopSpice supports all the analysis modes (DC, AC and transient) for all the ABM methods. ABM
expressions can also be specified directly for resistor and capacitor values.
In addition, the E voltage source offers the following special function options:
Option Description
ADD Adds two voltages: (Va + Vb) x gain
COMPFUN Comparator with hysteresis
COMPINV Inverting comparator with hysteresis
DIVIDE Divides two voltages: (Va / Vb) x gain
LIMITER Voltage limiter
MULTIPLY Multiplies two voltages: (Va x Vb) x gain
OPAMP Op amp with output voltage limiting
7-1
POWER Calculates sum of the products of voltage and current: V1 x I1 x c1 + .. + Vn x In x cn

SCHMITT Schmitt trigger
SCHMITTINV Inverting Schmitt trigger
POWER option is also available for the G current source. The analog behavioral feature may be
combined with the subcircuit parameter passing capability in TopSpice to develop general purpose
analog blocks.
See the Simulator Reference manual E source section for more details.
7.2 POLY Polynomial Source

Polynomial sources implement transfer functions given by polynomial functions of circuit voltages or
currents.
Statement syntax:
Ename +node -node POLY(dim) <nc list> <coeff list> [IC=value]
Fname +node -node POLY(dim) <Vc list> <coeff list> [IC=value]
Gname +node -node POLY(dim) <nc list> <coeff list> [IC=value]
Hname +node -node POLY(dim) <Vc list> <coeff list> [IC=value]
Current flow is from the positive node, through the source, to the negative node.
+node Positive output terminal.
-node Negative output terminal.
dim Number of dimensions (controlling voltages or currents), which must be positive.
<nc list> List of node pairs for the controlling voltages. One pair of nodes must be specified for
each dimension.
<Vc list> List of voltage source names for the

controlling currents such as V1, VIN.
<coeff list> Polynomial coefficients.
IC Optional initial condition parameter. If not

specified, SPICE assumes 0. The initial
condition for dependent sources is an
initial guess for the value of the controlling
variable. To reduce the computational
effort for the dc operating point (or if the
polynomial specifies a strong non-
linearity), a value fairly close to the actual
controlling variable should be specified for
the initial condition.
The POLY sources allow circuits to contain dependent

Figure 7.1 POLY source symbol
sources characterized by any of the four equations:
attributes setup example
7-2
v = f(vc) E sources
i = f(ic) F sources
i = f(vc) G sources
v = f(ic) H sources
f() must be polynomials, and the arguments may be multidimensional. The polynomial functions are
specified by a set of coefficients p0, p1, ..., pn. Both the number of dimensions and the number of
coefficients are arbitrary. The first coefficient is always the constant term. The meaning of the other
coefficients depend upon the dimension of the polynomial.
Suppose that the function is one-dimensional (that is, a function of one argument). Then the function
value, fv, is determined by the following expression in fa (the function argument):
2 3 4
fv = p0 + p1×fa + p2×fa + p3×fa + p4×fa + ...
Note: for the case of “fv = p1×fa” (only one coefficient with p0=0) the linear dependent source form should
be always used instead of the POLY(1) option.
Suppose now that the function is two-dimensional, with arguments fa and fb. Then the function value, fv,
is determined by the following expression:
fv = p0 + p1×fa + p2×fb + p3×fa + p4×fa×fb + p5×fb + p6×fa + p7×fa ×fb + p8×fa×fb + ...
2 2 3 2 2
Consider now the case of a three-dimensional polynomial function with arguments fa, fb, and fc. Then the
function value, fv, is determined by the following expression:
2
fv = p0 + p1×fa + p2×fb + p3×fc + p4×fa + p5×fa×fb
2 2
+ p6×fa×fc + p7×fb + p8×fb×fc + p9×fc +
+ p10×fa + p11×fa ×fb + p12×fa ×fc + p13×fa×fb
3 2 2 2
2 3
+ p14×fa×fb×fc + p15×fa×fc + p16×fb +
+ p17×fb ×fc + p18×fb×fc + p19×fc + p20×fa + ...
2 2 3 4
For all four of the dependent sources, the initial condition parameter is described as optional. If not
specified, SPICE assumes 0. The initial condition for dependent sources is an initial guess for the value of
the controlling variable. To reduce the computational effort for the dc operating point (or if the polynomial
specifies a strong nonlinearity), a value fairly close to the actual controlling variable should be specified
for the initial condition.
Examples,
EMULT 1 0 POLY(2) 2 0 3 4 0 0 0 0 1
ESQR 1 0 POLY(1) 2 0 1.5 2 5M
F1 2 5 POLY(2) V1 VIN 0 0.1 23.5u
G1 1 2 POLY(1) 38 11 2E-6 3m 1.2m
H1 1 0 POLY(3) V1 V2 V3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
The first example multiplies the two voltages V(2) and V(3,4). The second one implements the quadratic
-3 2
equation 1.5 + 2xV(2) + 5x10 xV(2) .
When using POLY controlled sources you must be careful to check that the connections and coefficients
used allow for a stable solution. For instance, when using voltage controlled sources in the following
configuration:
Ex(or Gx) n1 n2 POLY(1) n1 n2 A B
7-3
In this case if the constant coefficient A is not zero, in most cases the circuit will fail to converge or it will
converge to an arbitrary value during the DC operating point calculation. The following example using an
E source illustrates the problem more clearly:
E1 1 0 POLY(1) 1 0 (4 1)
Here, E1 always tries to set node 1 to whatever voltage is at it plus 4 volts.
7.3 VALUE Source

VALUE sources implement transfer functions
specified by arbitrary mathematical equations of
circuit variables and user parameters.
Statement syntax:
Ename +node -node VALUE = {expression}

[GZERO]
Gname +node -node VALUE = {expression}

[GZERO]
{expression} may contain constants, circuit variables

(V,I and time), parameters and math functions. See
Section 7.7 for more detailed description on
specifying of expressions and parameters.
Figure 7.2 VALUE source symbol
GZERO if this option is specified the output
derivatives are set to zero. This helps convergence
when the table has large discontinuities and the
source is not part of a feedback loop. If it is part of
loop, GZERO cannot be used because it produces wrong results and/or causes convergence problems.
For AC analysis, the output value is the product of the input signal times the equivalent linearized gain
value at the DC operating point. For instance, for the expression {V(1)^2+V(3)} at V(1)=5.0V and
V(3)=3.5V, the AC expression value is
(2*5.0 + 3.5) * v(1) + (5.0^2 + 1.0) * v(3)
v(1) and v(3) are the AC frequency domain complex voltages.
The VALUE source is equivalent to the B element source in SPICE3/XSPICE.
Examples:
ERIN 8 0 VALUE = {2.0*V(3,2)/(I(VIN)+1P)+V(65)}

GPOWR 2 3 VALUE = {V(5)*I(VCC)}
EDB 10 11 VALUE = {20*LOG10(V(44)+1U)}
Note: expressions that include the source output voltage will likely cause a "feedback" effect without a
stable output value leading to solution convergence problems.
7-4
7.4 TABLE Source

TABLE sources implement transfer functions given
by look-up tables.
Statement syntax:
Ename +node -node TABLE {expression} =

<table data> [GZERO] [GSMOOTH=value]
Gname +node -node TABLE {expression} =

<table data> [GZERO] [GSMOOTH=value]
{expression} is the input signal expression. It is

evaluated first and used as the input value to the
look-up table.
<table data> is the list of table data points. Each data

point must be in the following format: Figure 7.3 TABLE source symbol
<input value> <output value> ...
Use of delimiter characters in the table data specification is optional. At least one data pair must be
specified.
For input values less than the first table input value, the output remains constant at the output
corresponding to the first table output value. For input values greater than the last table input value, the
output value remains constant at the last table output value. In between table values, linear interpolation
is used to determine the output values.
GZERO If this option is specified the output derivatives are set to zero. This helps convergence
when the table has large discontinuities and the source is not part of a feedback loop. If it
is part of loop, GZERO cannot be used because it produces wrong results and/or causes
convergence problems.
GSMOOTH This option is a convergence aid option that specifies the "smoothing" domain coefficient
value. Default is 0.1. Acceptable range is 0 (no smoothing) to 0.5. When nonzero, the
table corners are smoothed to minimize possible convergence problems with
discontinuities in the derivatives.
value at the DC operating point.
Examples:
ECOMP 3 0 TABLE {V(1,2)*1K-VBIAS} = (-1,-10) (1,10)

GSW 3 4 TABLE {V(3,4)*10} =
+ -5 1nA
+ 0 5uA
+ 3 1mA
7-5
7.5 FREQ Source

FREQ sources implement transfer functions given by
frequency response tables. The frequency response
table models linear devices in the frequency domain. It
can be used for both AC and transient analyses.
Statement syntax:
Ename +node -node FREQ {expression} = [format]

<table data>
Gname +node -node FREQ {expression} =

[format] <table data>
{expression} is the input signal expression. For AC

analysis, the equivalent linearized gain value,
evaluated at the dc operating point, is used.
format is an optional table data format keyword. The Figure 7.4 FREQ source symbol
default format is magnitude in dB and phase in attributes setup example
degrees. If the MAG format option is specified, table
magnitude values are assumed to be absolute
magnitudes instead of the default dB values. The RAD
option assumes the phase values are in radians instead of the default degree values. The R_I option
specifies that the table values are real and imaginary values. Note: only one option is allowed. The
SPARAM option specifies a s-parameters table.
<table data> is the list of table data points. Each data point must be in the following format:
<frequency> <gain value> <phase value> ...
Use of delimiter characters in the table data specification is optional. At least one data point must be
specified. <gain value> must be in dB and <phase value> in degrees. Linear interpolation is used for
values in between the frequency table data points. For frequencies outside the data range, the lowest and
highest frequency values are used.
times the frequency table response value. For DC and transient analyses, the output is the zero
frequency gain times the input expression value. For transient analysis the output is the convolution
integral of the transfer function expression value times the impulse response of the frequency response
table.
Examples:
EFILTER 4 3 FREQ {V(1,2)} = (0,0,0) (10K,50,-180) (20K,0,90)

GAMP 1 0 FREQ {V(IN)} =
+ 100Hz 90dB 180
+ 10KHz 85dB 160
+ 15KHz 60dB 90
+ 100KHz 20dB 50
7-6
7.5.1 S-Parameter Tables

A s-parameter frequency response table can be directly specified using the new E and G FREQ sources
SPARAM table option. This allows convenient linear modeling of high frequency devices for both AC and
transient simulation.
Statement syntax:
Ename +node -node FREQ {expression} SPARAM <table data>
Gname +node -node FREQ {expression} SPARAM <table data>
<table data> points must be specified as "freq magnitude phase" set of values. Magnitude is absolute
magnitude and phase is in degrees.
Example,
E12 9 3 FREQ {V(4,3)} SPARAM

+ 0.5G .023 76
+ 1G .05 71
+ 2G .086 51
+ 3G .12 35
+ 4G .149 18
+ 5G .172 3
To create a complete 2-port network model using s-parameters table would require a separate FREQ
source for each s-parameter. For instance, the following subcircuit SPARAM2P implements a general 2-
port s-parameter model:
.SUBCKT SPARAM2P p1a p1b p2a p2b

R1N p1a 5 -50
R1P 5 7 100
R2N p2a 4 -50
R2P 4 6 100
* S11
E11 7 9 FREQ {V(5,p1b)}= SPARAM
* Specify your S11 table here:
* FREQ MAG PHASE
+ 0.5G .97 -20
+ 1G .93 -41
...
* S21
E21 6 8 FREQ {V(5,p2b)}= SPARAM
* FREQ MAG PHASE
+ 0.5G 5.68 162
+ 1G 5.58 143
...
* S12
E12 9 p1b FREQ {V(4,p1b)}= SPARAM
* FREQ MAG PHASE
+ 0.5G .023 76
+ 1G .05 71
...
* S22
E22 8 p2b FREQ {V(4,p2b)}= SPARAM
7-7

* FREQ MAG PHASE
+ 0.5G .47 -11
+ 1G .45 -23
...
.ENDS
The subcircuit SPARAM2P, and also SPARAM3T, are available under the “RF components” category in
the model library database.
The Schematic Editor Tools|User Part|Import S-Parameters File command can import a s-parameters
data file as a user part. This utility function converts a s-parameters data file to a SPICE model and saves
it as a schematic user part with its matching symbol. The user part is saved as filename extension
*.S2P.TSP file. Only Touchstone 2-port s-parameters (.S2P) files are supported.
To use the SPARAM2P model with s-parameters data in other formats, follow this procedure:
1. Copy and paste the desired model subcircuit netlist to your circuit file or the “miscellaneous
commands” file.
2. Replace the s-parameter tables to match your device. Do not directly modify the models here.
3. Rename the model to match your device part number.
See the example circuit files "S-Parameters Table FET.sch" and "S-Parameters Table Transient.sch" for
sample applications.
7.6 LAPLACE Source

LAPLACE sources allow frequency domain modeling of linear systems using Laplace transforms. Any
arbitrary expression of the complex frequency variable "s" may be specified as a Laplace transform.
TopSpice can simulate both the frequency and transient responses of Laplace transfer functions.
Voltage source statement syntax:
Ename +node -node LAPLACE {expression} = {s expression}

+ [NMAX=value] [NFFT=value] [MU=value]
Figure 7.5 LAPLACE source symbol attributes

setup example
7-8
Current source statement syntax:
Gname +node -node LAPLACE {expression} = {s expression}

+ [NMAX=value] [NFFT=value] [MU=value]
expression is the input signal expression. For AC analysis, the equivalent linearized gain value, evaluated
at the dc operating point, is used.
{s expression} is the Laplace transform function specified as an expression of the complex frequency
variable "s". Laplace transform expressions can include numerical constants, user defined parameters
and the following variables:
S complex frequency
OMEGA radian frequency
HERTZ frequency in Hertz
Laplace transform expressions can include the following complex math operators:
() parenthesis
+ addition
- subtraction or negate
* multiplication
/ division
^ power operator (i.e.: x^y is power of x raised to y)
** power operator (i.e.: x**y) PSpice™ compatible syntax
Laplace transform expressions can include the following complex math functions:
ABS(x) absolute value

CMPLX(a,b) complex number a+jb
COS(x) cosine
EXP(x) exponential
JCMPLX(x) complex number 0+jx
LOG(x) logarithm
POW10(x) power of 10
PWR(x,y) power of x raised to y (same as x^y)
SIN(x) sine
SQR(x) square
SQRT(x) square root
NMAX specifies an optional maximum number of frequency points used to calculate the impulse
response (up to 8192).
NFFT is same as NMAX.
MU specifies an optional adjustment to the transient integration to minimize numerical oscillation

(acceptable range 0 to 0.5). Smaller value increases averaging and reduces oscillation.
times the Laplace transform value. For DC analysis the output is the transfer function expression value
times the transform value with s=0. For transient analysis the output is the convolution integral of the
input signal (output of expression) value times the impulse response of the transform.
Examples,
7-9
E1 3 0 LAPLACE {V(5)-V(2)*3} = {1/(1+0.001*s}

GLOSSY 2 0 LAPLACE {V(IN)} = {exp(-sqrt(C*s*(R+L+s)))}
7.6.1 Laplace Transform State Space Model

The LAPLACE source allows arbitrary transforms to be specified. But for transient analysis, it is very
computationally intensive, and it might require long simulation times, because it relies on full convolution
to get the time response. For linear Laplace transforms, it is far more efficient to evaluate the transient
response using the "state space" formulation.
The TopSpice model library includes several macromodels that implement linear Laplace transforms of
the form of ratio of polynomials using the "state space" formulation. These models support both AC and
transient analyses. They are much faster and more accurate for transient analysis than the LAPLACE
source. The following models are available:
Name Description
LAPLACE_N1 1st order linear Laplace transform
LAPLACE_N2 2nd order linear Laplace transform
LAPLACE_N3 3rd order linear Laplace transform
LAPLACE_N4 4th order linear Laplace transform
The transform must be a ratio of polynomials of the form
n i × s i + ... + n 2 × s 2 + n1 × s + n 0
H (s) =
d i × s i + ... + d 2 × s 2 + d 1 × s + d 0
The highest numerator order must be equal or less than the denominator order. The coefficients are
specified as subcircuit parameters:
Parameter Default Description

N0 1 numerator zero order (lowest) coefficient
N1 0 numerator 1st order coefficient
N2 0 numerator 2nd order coefficient
N3 0 numerator 3rd order coefficient
N4 0 numerator 4th order coefficient
D0 1 denominator zero order (lowest) coefficient
D1 1 denominator 1st order coefficient
D2 1 denominator 2nd order coefficient
D3 1 denominator 3rd order coefficient
D4 1 denominator 4th order coefficient
If a term is missing, a zero value must be specified for its coefficient. For example,
X1 in 0 out LAPLACE_N3 PARAMS: N0=0.715 N1=1 D0=1 D1=1.53 D2=2.05 D3=1
The above statement models the 3rd order Laplace transform
s + 0.715
H ( s) =
s + 2.05s 2 + 1.53s + 1
3
7-10
See example circuit file "Laplace State Space Model.cir" for sample application.
To implement an integrator, it is recommended that the INTEGRATOR macromodel be used instead of

the LAPLACE source transform {1/s}. Simulation using this model is faster and more accurate in most
cases.
7.7 RESISTOR Source

RESISTOR sources implement resistance transfer functions specified by arbitrary mathematical
equations of circuit variables and user parameters.
Statement syntax:
Gname +node -node RESISTOR {expression}
{expression} may contain constants, circuit variables (V,I and time), parameters and math functions. See
Section 7.7 for more detailed description on specifying of expressions and parameters.
Example:
G1 5 2 RESISTOR {RNOM*(1+0.2*V(5,2)+I(VX)/1.5M)}
For AC analysis, the resistance value is the DC operating point dI/dV value. If the source terminal voltage
is a variable in the resistance expression, the resistance value is given by
Rac = Rdc + Vdc dR/dV
Behavioral resistance expressions can also be specified on the resistor element statement. For instance,
the above G RESISTOR source example can be specified using the following resistor statement:
R1 5 2 {RNOM*(1+0.2*V(5,2)+I(VX)/1.5M)}
7.8 ABM Expressions

The expressions used in the ABM sources can be any arbitrary equation, which may contain constants,
circuit variables, arithmetic operators, predefined math functions and parameters. The expressions must
be enclosed between curly brackets {}, quotes or single quotes, to be recognized as expressions by
TopSpice.
Examples:
E1 1 0 VALUE={V(2,1)*2.0+V(OUT)/ROUT*I(VIN)}
G2 2 3 VALUE={LOG(V(3)/2.3M}
Although any arbitrary expression is allowed in TopSpice, the following considerations should be kept in
mind to avoid convergence problems or program crash during the solution phase:
• Functions should be well behaved and continuous. Very rapidly changing functions such as
exponentials and power functions represent very high gain blocks, which can lead to convergence
problems if it is part of a feedback loop.
• You should always add appropriate capacitances to account for delays at the input and output nodes
of analog behavioral blocks to avoid convergence problems during transient analysis.
• You must make sure the function is defined for all possible values of the circuit variable range (for
instance, if you have LOG(V(1)), and V(1) is zero, the program will halt).
7-11
For detailed descriptions of expressions and users parameters, see the Simulator Reference manual
“Parameters and Expressions” section.
7.8.1 Predefined Constants

The following predefined numeric constants may be used in expressions:
Name Value Description
BOLTZ 1.3806226E-23 Boltzmann's constant

CHARGE 1.6021918E-19 electron charge
EPS0 8.854214871E-12 permitivity constant
GMIN 1E-12 Minimum semiconductor junction conductance option value
(PSpice compatible)
PI 3.1415927.. pi value used internally by the simulator
7.8.2 Circuit State Variables

The following circuit state variables and constants may be included in ABM expressions:
V(n) or V(n1,n2) Node voltages
I(name) Device currents. name is the reference name for one of the following two terminal
devices: V (independent voltage source), C (capacitor), D (diode), E (voltage-
control dependent source), L (inductor), R (resistor).
TIME Time
HERTZ Frequency in Hertz (HSPICE compatible, Laplace transform expressions only)
OMEGA Radian frequency (Laplace transform expressions only)
TEMP Circuit operating temperature in degrees C (PSpice compatible)
TEMPC Circuit operating temperature in degrees C (obsolete, same as TEMP)
TEMPER Circuit operating temperature in degrees C (HSPICE compatible, same as TEMP)
TEMPK Circuit operating temperature in degrees K (absolute temperature)
Circuit voltage and current variables can take unexpected values while the simulator is trying to converge
to a valid solution point. Hence, one cannot assume their values will always be within the normal
operating range. For example, if you specify an expression such as {1/V(2)}, you cannot assume that
V(2) will never be zero even if during the normal operation of the circuit V(2) would never be zero. To
avoid a possible divide-by-zero error, you should modify the expression to something like {1/(V(2)+1u)}.
If an ABM expression inside a subcircuit uses current variables of form I(Vname) and the source Vname
is not found within the same subcircuit, it searches the top level circuit elements for Vname. Hence, top
level voltage source names are global for ABM expressions.
7-12
7.8.3 Math Functions

The following predefined math functions may be used in expressions:
ABS(x) absolute value

ACOS(x) arc cosine
ACOSH(x) arc hyperbolic cosine
ASIN(x) arc sine
ATAN(x) arc tangent
COS(x) cosine
EXP(x) exponential
IF(t,x,y) IF-THEN-ELSE logical evaluation. The argument t is normally a relational
expression. The output is x if t=TRUE or y if t=FALSE.
INT(x) integer part (same as TRUNC, HSPICE™ compatible)
LIMIT(x,y,z) if x<y returns y, if x>z returns z, else returns x
LN(x) logarithm base e (same as LOG, SPICE3 compatible syntax)
LOG(x) logarithm base e
LOG10(x) logarithm base 10
MAX(x,y) maximum of x and y
MIN(x,y) minimum of x and y
POW(x,y) power of x to the integer part of y, |x|^INT(y)
POW10(x) 10 to the power of x
PWR(x,y) power, |x|^y absolute value of x to power of y
PWRS(x,y) signed power, if x<0, -|x|^y; if x>0, |x|^y
RND returns a new random value between 0 and 1 for every new time point evaluated
during a transient analysis simulation. For DC and AC analyses, the starting random
value remains the same during the entire analysis run. The RND function does not
take any parameters.
NOTE: only one RND instance is allowed for the entire simulation because
there is one random generator available. Multiple RND instances will most likely
lead to simulation convergence problems because the RND function state for each
instance is not preserved.
ROUND(x) round off to nearest integer value (ex: 2.3 is 2, 11.7 is 12)
SGN(x) returns -1 if argument <0 or 1 otherwise (PSpice™ compatible syntax)
SIGN(x) returns -1 if argument <0 or 1 otherwise (same as SGN)
SIN(x) sine
SINH(x) hyperbolic sine
SQR(x) square
SQRT(x) square root
STP(x) step function. 1 if x > 0, otherwise 0
TABLE(x..) the TABLE(x,x1,y1,x2,y2,...,xn,yn) function result is the y value corresponding to
7-13
expression x value. Linear interpolation is used between the table data points. If x is
greater than xn, then the result is yn. If x is less than x1, then the result is y1. Table
values cannot be expressions and xi values must be in increasing order.
Note: nested TABLE functions are not allowed.

TANH(x) hyperbolic tangent
TAN(x) tangent
TRUNC(x) truncate to integer value
U(x) step function. 1 if x > 0, otherwise 0 (same as STP, SPICE3 compatible syntax)
URAMP(x) ramp function (SPICE3 compatible). x if x > 0, otherwise 0
When using these functions, the user must make certain that the arguments to the functions are within
the valid range. The simulator traps the following math errors:
- If LOG(x) or LOG10(x) and x <= 0, sets result to -100.

- If SQRT(x) and x < 0, uses x=ABS(x).
Other math errors in expressions may cause the program to halt (crash).
7.8.4 User Defined Functions

The .FUNC command statement defines allows the user to define new functions used in behavioral and
parametric expressions. It is useful for partitioning long expressions into subexpressions and where there
are several similar subexpressions used in a circuit file.
The user defined function can have up to 8 arguments. The number of arguments in the function call must
agree with the number in the definition. Both the function and argument names must start with a letter and
they can be up to 64 characters long.
The function definition expression can be any valid mathematical expression. It can include parameters,
constants, state variables and predefined functions. A .FUNC statement expression can include other
.FUNC defined functions. Up to 16 levels of nesting is allowed for .FUNC function calls.
A .FUNC statement does not have to precede the first use of the function name. Functions cannot be
redefined and the function name must not be the same as any of the predefined functions such as SIN
and SQRT. .FUNC statements defined in subcircuits only have local scope. .FUNC defined functions
cannot be used in LAPLACE transform expressions.
Examples,
.FUNC DECAY(K) {EXP(-TIME/K)}

.FUNC IALPHA(VX,RS) {VX/RS*DECAY(TAU)}
.FUNC MAX3(A,B,C) {MAX(A,MAX(B,C))}
.FUNC VTG(VG) {VG-VTH}
7-14
7.8.5 Logical Expressions

Logical expressions are supported by TopSpice. The result of logical expressions always have the value
of 0 or 1. Any values greater than 0 is considered a logic high value. The following logical operators are
supported:
~ unary NOT
| OR
^ XOR
& AND
Note: by default ^ is the power math operator. To use ^ as the XOR operator, the following option must be
specified before first use:
.OPTION EXPR^XOR
Logical expressions may be used anywhere ABM or parametric expressions are allowed. When
expressions include both math and logical operators, the precedence of the logical operators is the same
as multiplication and division except for the NOT operator.
Examples:
E1 2 0 VALUE={V(A)&V(B)&V(C))}
E1 1 2 TABLE={~(V(3)|V(10))&(I(VX)*R5))} (0,-2) (1,5)
G1 1 0 VALUE={V(3,5)|(V(A)+V(B))}
7.8.6 Relational Expressions

Relational expressions are supported by TopSpice. The result of relational expressions always have the
value of 0 (false) or 1 (true). Any values greater than 0 is considered true. The following relational
operators are supported:
== equal
!= not equal
> greater than
>= greater than or equal
< less than
<= less than or equal
Although, relational expressions may be used anywhere ABM or parametric expressions are allowed,
they should only be used as the first argument for the IF(t,x,y) function. When expressions include both
math and relational operators, the precedence of the relational operators is the same as addition.
Examples:
E1 1 0 VALUE={IF(V(2)<=VMAX,V(5),V(5)*V(5)/VMAX)*2}
G1 1 0 VALUE={IF((I(V1)*V(IN)!=(V(3)*V(3)/RL),1uA,I(V1)))
7-15
7-16
ABOUT SPICE
APPENDIX
8 ABOUT SPICE
8.1 SPICE Program

The SPICE (Simulation Program with IC Emphasis) program has become the de facto industry standard
for analog circuit simulation. It offers the advantages of a large user base, large number of existing device
models, modeling support by component manufacturers, and compatibility between CAD vendors.
There are now many versions of the SPICE program available (so called "alphabet SPICEs") for analog
circuit simulation. They are all derived from the SPICE general purpose circuit simulation program
developed and released in 1975 by the University of California at Berkeley. SPICE was originally
developed specifically for the simulation and design of integrated microcircuits. However, its ease of use,
excellent accuracy, robustness and wide availability has made SPICE the industry standard for the
analysis of all types of analog circuits.
An important advantage of SPICE simulators is the large number of device and component models
already available for them. Also, many component manufactures provide SPICE model libraries for their
parts free of charge or at nominal cost. These device models represent an investment of hundreds of
thousands of man-hours, which are available to the SPICE user at minimal cost.
SPICE programs from most vendors incorporate enhancements to the Berkeley version such as new
device models, bug fixes, and extended syntax for handling convenience features like library files,
parameter passing, etc. Many SPICE based CAE packages also include graphical post-processors for
viewing the output waveforms, and input front-ends to handle schematic capture and design analysis
options such as Monte Carlo, worst case and filter designs.
8.2 SPICE Reference Books

Christophe P. Basso, Designing Control Loops for Linear and Switching Power Supplies: A
Tutorial Guide, Artech House, 2012.
Christophe P. Basso, Switch-Mode Power Supplies Spice Simulations and Practical Designs,
McGraw-Hill Professional, 2008.
Steven M. Sandler, SPICE Circuit Handbook, McGraw-Hill Professional, 2006.
T. Ytterdal, Y. Cheng, T. A. Fjedly, Device Modeling for Analog and RF CMOS Circuit Design, Wiley,
2003.
L. Castaner, S. Silvestre, Modelling Photovoltaic Systems Using Pspice, John Wiley & Sons, 2002.
William Liu, Mosfet Models for Spice Simulation, Including BSIM3v3 and BSIM4, Wiley-Interscience,
2001.
Christophe P. Basso, Switch-Mode Power Supply SPICE Cookbook, McGraw-Hill, 2001.
Alfi Moscovici, High Speed A/D Converters – Understanding Data Converters Through SPICE, Kluwer
Academic Publishing, 2000.
Y. Cheng, C. Hu, MOSFET Modeling and BSIM3 User’s Guide, Kluwer Academic Publishers, September
1999.
8-1
Steven M. Sandler, SMPS Simulation with SPICE3, McGraw-Hill, 1997.
Daniel P. Foty, MOSFET Modeling With SPICE: Principles and Practice, Prentice Hall, 1996.
Ron M. Kielkowski, SPICE: Practical Device Modeling, McGraw Hill, 1995.
Bashir Al-Hashimi, The Art of Simulation Using PSpice, CRC Press Inc., Boca Raton, FL, 1995.
Kenneth S. Kundert, Designer’s Guide to SPICE and SPECTRE, Kluwer Academic, 1995.
James G. Gottling, Hands on PSpice, John Wiley & Sons, New York, NY, 1995.
David R. Cunningham and John A. Stuller, Circuit Analysis, 2nd Edition, John Wiley & Sons, New York,
NY, 1995.
Jan Ogrodzki, Circuit Simulation Methods and Algorithms, CRC Press Inc., Boca Raton, FL, 1994.
Ron Kielkowski, Inside SPICE, New York, NY, McGraw-Hill, 1994.
Andrei Vladimirescu, The SPICE Book, New York, NY, John Wiley & Sons, 1994.
K. Kit Sum, Switch Mode Power Conversion, New York, Marcel Dekker, 1994.
John Keown, PSpice and Circuit Analysis, New York, NY, Merrill, 1993.
Muhamid H. Rashid, SPICE for Power Electronics and Electric Power, Englewood Cliffs, NJ, Prentice
Hall, 1993.
Yim-Shu Lee, Computer-Aided Analysis and Design of Switch-Mode Power Supplies, New York, Marcel
Dekker, 1993.
C.D. Motchenbacher and J.A. Connelly, Low Noise Electronic System Design, New York, NY, John Wiley
& Sons, 1993.
Paul R. Gray and Robert G. Meyer, Analysis and Design of Analog Integrated Circuits, New York, NY,
John Wiley & Sons, 1992.
Franz Monseen, PSpice with Circuit Analysis, MacMillian Publishing, 1992.
J. Alvin Connelly and Pyung Choi, Macromodeling with SPICE, Englewood Cliffs, NJ, Prentice
Hall, 1992.
Muhamid H. Rashid, SPICE for Circuit and Electronics Using PSpice, Englewood Cliffs, NJ, Prentice Hall,
1990.
W. Banzhaf, Computer-Aided Circuit Analysis Using SPICE, Englewood Cliffs, NJ, Prentice Hall, 1989.
Paul W. Tuinenga, SPICE: A Guide to Circuit Simulation and Analysis Using PSpice, Englewood
Cliffs, NJ, Prentice Hall, 1988.
L. Meares and C. Hymowitz, Simulating with SPICE, San Pedro, CA, Intusoft, 1988.
Paolo Antognetti and Giuseppe Massobrio, Semiconductor Device Modeling with SPICE, New
York, McGraw-Hill, 1988.
8-2
ABOUT SPICE
Tom Thorpe, Computerized Circuit Analysis: Learning Spice and its Applications, John Wiley & Sons,
New York, NY.
A. Vladimirescu, Kaihe Zhang, A. R. Newton, D. O. Pederson, and A. Sangiovanni- Vincentelli, SPICE

Version 2G User's Guide, Department of Electrical Engineering and Computer Sciences, University of
California, Berkeley, August 1981.
A. Vladimirescu, S. Liu, The Simulation of MOS Integrated Circuits Using SPICE2, Memo No. ERL M80/7,
Electronics Research Laboratory, University of California, Berkeley, Oct. 1980.
Ellis Cohen, Program Reference for SPICE2, Memorandum No. M592, University of California, Berkeley,
June 1976.
L. W. Nagel, SPICE2: A Computer Program to Simulate Semiconductor Circuits, Memorandum No. M520,
University of California, Berkeley, May 1975.
8-3
8-4
INDEX
INDEX
print data, 5-24

. save data, 5-24
temperature, 5-22
.AC, 5-3 transient, 5-21
.ALTER, 5-11 AND gate, 6-7
.DC, 5-2 applications, 2-3
.DISTO, 5-3 approximation error, 1-13
.FOUR, 5-6 Apps, 2-3
.FRA setup, 5-21 Arithmetic Logic Units, 6-12
.FUNC, 7-14 ASIN, 7-13
.INC/MDB, 4-20 ATAN, 7-13
.MC, 5-11 attributes, 2-10
.NOISE, 5-3 autoplot, 2-12
.OP, 5-3 axis limits, 2-13
.PRINT TRAN, 5-6
.SAVE, 5-30 B
.SENS, 5-3
.STAT, 5-16, 5-23 Behavioral modeling, 1-4, 7-1
.STEP, 5-11, 5-12 bias point solution, 5-32
.TEMP, 5-10 bias voltage display, 5-29
.TF, 5-3 binary file, 5-30
bookmarks, 3-10
A BUF3, 6-8
Buffer array, 6-7, 6-8
A/D interface, 6-15
ABM, 7-1
ABM Expressions, 7-11
C
ABS, 7-9, 7-13 charge-controlled, 5-33
AC analysis, 5-3 circuit, 1-12
accuracy criteria, 5-31 circuit analysis, 5-1
ACOS, 7-13 Circuit Elements, 4-1
ACOSH, 7-13 circuit file, 2-16
ADD, 7-1 editor, 1-1
adder, 6-12 schematic, 5-26
algorithms CLOCK, 6-7
convergence, 5-32 command line
ALTER, 5-14 simulator operation, 2-13
ALU, 6-13 comparator, 6-13
analog behavioral modeling, 7-1 digital, 6-13
Analog/Digital Interface, 4-4, 6-14 complex frequency, 7-8
analysis, 2-19, 5-1 complex numbers, 5-3
setup menu, 5-20 Component Values, 5-11
analysis setup, 5-20 Configuration File, 1-7
.ALTER, 5-23 Controlled Sources, 4-2
AC sweep, 5-22 convergence, 5-31
auto plot, 5-24 transient analysis, 5-33
DC bias point, 5-21 convolution integral, 7-6, 7-9
DC sweep, 5-21 correlation, 5-17
FRA, 5-21 COS, 7-9, 7-13
Monte Carlo, 5-23 Counters, 6-11
parametric step, 5-22 cross reference, 5-28
I-1
current variable, 2-7

cursor measurements, 2-12
F
file
D circuit, 1-12
circuit netlist, 2-15
DATA, 6-7 encrypted, 4-22
Database tool, 4-15 input, 2-13
DC analysis, 5-2 output listing, 2-13
dc sweep, 5-2 schematic, 1-12
decoder, 6-12 File Browser, 1-3, 3-11
decryption, 4-22 files, 2-5
default temperature, 5-10 Flicker noise, 5-4
DEFAULT.LIB, 4-10 flip, 2-10
delay gate, 6-8 flip-flops
Design Project, 2-9 edge-triggered, 6-8
device models, 2-19, 4-5, 4-7, 4-9 floating point number, 2-7
Device Tolerances, 5-16 Fourier, 5-6
DIGFREQ, 6-4 Fourier harmonic analysis
digital, 6-1 setup, 5-21
arbitrary waveform, 6-7 FRA, 5-7
gates, 6-7 FREQ sources, 7-6
I/O model, 6-5 frequency domain, 5-3
periodic waveform, 6-7 frequency response, 7-6
primitive models, 6-6 frequency response analysis
Digital Circuit, 6-2 ac analysis, 5-3
Digital Devices, 4-4 AC setup, 5-22
Digital Macro Models, 6-13 transient, 5-7
Digital primitive, 6-1 transient setup, 5-21
Digital Primitives, 6-4 frequency sweep, 5-3
digital simulation, 6-1 function
distortion characteristics, 5-5 math, 7-13
distortion analysis, 5-3, 5-5 user defined, 7-14
distributed effects, 1-13
DIVIDE, 7-1
Divide-by-N counter, 6-11
G
documentation, 2-3 Gaussian, 5-16
DTEMP, 5-10 glitch suppression
digital simulation, 6-4
E Global Nodes, 2-6
GMIN, 5-33
editor GND, 2-11
text, 3-1 ground node, 2-11
Electrical Connection, 2-11
element
SPICE, 4-1 H
encoder, 6-12 harmonic analysis, 5-6
encrypt Help, 2-3
model file, 4-22 histogram, 5-11
encryption, 4-22 HSPICE Libraries, 4-20
equations, 7-4 HSPICE library file, 4-21
error checking, 5-27
error messages, 3-15
event-driven, 6-1 I
examples, 2-4
IF, 7-13
EXP, 7-9, 7-13
import
EXPR^XOR, 7-15
model, 4-14
expressions, 7-11
impulse response, 7-6, 7-9
Include Files, 4-22
independent sources, 4-2
I-2
INDEX
initial states, 6-5 model file

input file, 2-13 import, 4-14
Installation, 1-5 model library, 4-9, 4-10
activation, 1-6 modeling, 7-1
upgrade, 1-6 frequency domain, 7-8
INT, 7-13 Models
interface element, 6-14 built-in, 4-5
Inverter array, 6-7 Monte Carlo, 5-11
ITL11, 5-33 Monte Carlo analysis, 5-16
ITL12, 5-33 mouse
right button, 2-1
ITL6, 5-33
Multiple Open Files, 3-9
multiplexer, 6-12
J MULTIPLY, 7-1, 7-2
multivibrators, 6-13
junctions, 2-10 digital, 6-13
L N
LAPLACE sources, 7-8 Names, 2-6
Laplace transform, 7-8 NAND gate, 6-7
launch, 2-2 netlist, 1-12, 2-15
libraries, 4-9 error messages, 5-28
TopSPICE models, 4-15 rules, 2-8, 2-15
LibraryPath, 4-10 New Circuit, 2-2
LIMIT, 7-13 Newton-Raphson, 5-31
LN, 7-13 node label, 2-11
LOG, 7-9, 7-13 node names, 2-11
LOG10, 7-13 Node Names, 2-6
logic glitch, 6-4 node numbers, 2-11
logic simulation, 1-4, 6-1 node voltages
Logic States, 6-3 last iteration, 5-32
logic time step, 6-4 noise, 5-4
Logical expressions, 7-15 noise analysis, 5-3, 5-4
logical operators, 7-15 noise source, 5-4
Lot Tolerances, 5-17 nominal temperature, 5-10
LTspice non-convergence, 5-32
encrypted models, 2-15 non-electrical system, 1-13
simulator, 2-15 NOR gate, 6-7
Notation, 1-11
M number field, 2-7
number format, 2-7, 2-8
macromodels, 4-6
map file, 5-28
math errors, 7-14 O
math functions, 7-13 OMEGA, 7-9
MAX, 7-13 Open
MaxMem, 2-14 Last Project, 2-3
MIN, 7-13 Saved Schematic, 2-3
Mirror, 2-10 Saved SPICE File, 2-3
mixed-mode circuits, 6-14 Open as, 2-3
Mixed-Mode Simulation, 1-4 open loop gain, 5-5
model OPENLOOPGAIN, 5-5
database, 4-15 operating point, 5-2
encrypted, 4-22 operating temperature, 5-10
file, 4-9 optimizing, 5-11
libraries, 1-3 OR gate, 6-7
library, 4-9 output
links, 4-13 simulation, 5-19
I-3
output commands, 5-20

S
output file
browsing, 3-11 SAVEOPB, 5-30
e-mail, 3-15 scale factors, 2-7
output files, 2-13, 5-30 schematic
create, 2-9
Schematic Capture, 1-1
P seed, 5-16
parallel simulations, 5-29 Semiconductor Devices, 4-3
parameters, 7-11 sensitivity, 5-3
parametric analysis, 5-11, 5-12 shift registers
parasitic effects, 1-13 n-bit, 6-10
part attributes, 2-10 paralled load universal, 6-10
parts, 2-10 parallel in/serial out, 6-11
Passive Devices, 4-2 serial in/parallel out, 6-10
pause simulation, 5-29 shortcut keys, 2-1
performance spec, 5-11 text editor, 3-2, 3-11
plot partial run, 5-29 SIGN, 7-13
plotting, 2-12 Signal Sources, 4-2
POLY, 7-2 simulation, 1-12, 5-1
Polynomial sources, 7-2 multiple, 5-29
POW, 7-13 output, 5-30
POW10, 7-9, 7-13 pause-plot-resume, 5-29
power rails, 2-11 run, 2-20, 5-28
pre-processing, 1-12 schematic commands, 5-20
priority encoder, 6-12 Simulation, 2-12
probe, 2-12 Simulation Setup, 2-19, 5-21
project, 2-9 simulator, 2-13
propagation delay, 6-1 memory use, 2-14
PSREG, 6-10 other, 2-15
PULSE Simulator, 1-2
digital, 6-13 Simulator Commands, 5-1, 5-2
pulse generator, 6-13 simulator engine
digital, 6-13 option, 2-14
PWR, 7-9, 7-13 Simulator option, 3-6
PWRS, 7-13 SIN, 7-9, 7-13
SINH, 7-13
small-signal models, 5-3
R source stepping, 5-32
random SPARAM, 7-7
function, 7-13 s-parameter file
random number, 5-16 import, 7-8
random variations, 5-16 model, 7-7
Random-Access Memory, 6-9 S-Parameter Tables, 7-7
Read-Only Memory, 6-9 SPICE, 1-12, 2-13
register, 6-11 SPICE format, 2-13
registration, 2-4 SPICE model, 4-14
Relational expressions, 7-15 SPICE Model Libraries, 4-10
relational operators, 7-15 SPICE models, 4-7
RESISTOR, 7-11 SPICE syntax, 5-27
retriggerable, 6-13 SQR, 7-9, 7-13
PULSE, 6-13 SQRT, 7-9, 7-13
RND, 7-13 SREG, 6-10
ROM, 6-9 SREGP, 6-10
rotate, 2-10 SRFF, 6-8
ROUND, 7-13 standard deviation, 5-16
Run Simulation, 2-20 Standard Gates, 6-7
starting, 2-2
State Variables, 7-12
I-4
INDEX
statistical analysis, 5-11, 5-16 TRUNC, 7-14

statistical distribution, 5-16 TSEdit program, 3-11
statistical tolerance, 5-16, 5-23 tutorial session, 2-17
stepping, 5-12
stimulus generators, 6-7
STP, 7-13, 7-14
U
subcircuit, 4-6 UCOUNT, 6-11
support, 2-3 Uninstalling, 1-6
symbol Universal counter, 6-11
select, 2-10 update, 2-4
syntax URAMP, 7-14
color highlighting, 3-9 USEL, 6-12
user interface, 2-1
T user part
import, 4-14
TABLE, 7-13
TABLE sources, 7-5
tables, 7-5, 7-6
V
Tabulate, 5-11 VALUE sources, 7-4
TAN, 7-14 values
TANH, 7-14 component, 2-8
TEMP, 5-10 variables, 2-7
Temperature, 5-10 voltage variable, 2-7
terminology, 1-12 voltages schematic display, 5-29
text editor, 3-1, 3-11
time step, 5-33
TNOM, 5-10
W
tolerance, 5-16 warning messages, 3-15
Tolerance Tracking, 5-17 waveform analysis, 2-12
TOPSPICE.INI, 4-10 wildcard, 5-12
TopView, 1-3 wires, 2-10
TRAN/ALL, 5-6 worst case analysis, 5-18
transfer curves, 5-2
transfer functions, 7-1, 7-4, 7-8
dc, 5-3
X
transforms, 7-8 XNOR gate, 6-7
transient analysis, 5-6 XOR gate, 6-7
Transient Analysis Setup, 2-19 XSPICE, 2-14
Tri-State Buffer, 6-8
I-5

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TopSpice 8

For Windows XP/7/8/10

Mixed-Mode Circuit Simulator

Copyright  2019 by Penzar Development

TopSpice is a trademark of Penzar Development.

1 GETTING STARTED .......................................................................................................................... 1-1

2.8.1 Selecting Symbols .............................................................................................................. 2-10

4.4 Simulation Models ....................................................................................................................... 4-7

5.14.1 DC Convergence ................................................................................................................ 5-32

1.1.1 Schematic Capture

• Multiple schematic pages (up to 100).

1.1.2 Circuit File Editor

• Color highlighting for SPICE syntax.

See Chapter 3 for detailed information.

1.1.3 TopSpice Simulator

• Native mixed-mode, mixed-signal simulation with built-in event-driven logic simulator.

See the “Simulator Reference” manual for detailed information.

1.1.4 TopView Graphical Post-Processor

1.1.5 Output File Browser

See Chapter 3 for detailed information.

1.1.6 Model Libraries and Database

See Chapter 4 for detailed information.

1.2 Native Mixed-Mode Simulation

TopSpice features many advanced analog/digital mixed-mode capabilities:

• True event-driven state-machine representation of logic circuits.

See Chapter 6 for detailed information.

1.3 Analog Behavioral Modeling

See Chapter 7 for detailed information.

• Software CD with serial number.

1.4.1 System Requirements

• Windows XP, Vista, 7, 8 or 10 operating system (32 or 64 bits).

1.4.2 Installation Procedure

For the CD distribution, use the following procedure:

1. Insert CD in CD drive (must be built-in CD drive).

3. Follow the screen prompts.

[TopSpice]\Models contains all the simulation model library files.

Extension Open Command

1.4.3 Upgrade Installation

1.4.4 Uninstalling TopSpice

• From the Control Panel open the "Add/Remove Programs" icon.

1.5 Configuration File Setup

1.5.1 [TopSpice] Section

ProjectFolder Default folder (directory path) for user project files.

ExamplesPath Directory path where the example files are located.

SchematicCommand Command for schematic program.

EditFileCommand Command for text editor program.

BrowseFileCommand Command for output file browser program.

SetupSimulationCommand Command for simulator setup program.

SimulationCommand Command for simulator program.

XSpiceCommand Command for the XSPICE simulator engine option.

LTSpiceOption If set to 1, it enables the LTspice simulator option menu item.

PostProcessorCommand Command for post-processor program.

PDFViewCommand Command for displaying PDF help files.

1.5.2 [Schematic] Section

CursorWireOption Selects one of the following wiring cursors: 0=arrow, 1=pencil

1.5.3 [Simulator] Section

MemSize Maximum available memory space in Kbytes. If 0, auto detect amount of

1.5.4 [TopView] Section

1.5.5 [JobStatus] Section

ProjectPath Default directory path for your project files.

1.6 Documentation and Manuals

1.7 Documentation Notation Conventions

[IC=value] Items inside [ ] brackets, denote optional specifications.

1.8 Simulation Basics