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Rm0038 Reference Manual: Stm32L100Xx, Stm32L151Xx, Stm32L152Xx and Stm32L162Xx Advanced Arm-Based 32-Bit Mcus
Rm0038 Reference Manual: Stm32L100Xx, Stm32L151Xx, Stm32L152Xx and Stm32L162Xx Advanced Arm-Based 32-Bit Mcus
Reference manual
STM32L100xx, STM32L151xx, STM32L152xx and STM32L162xx
advanced ARM-based 32-bit MCUs
Introduction
This reference manual targets application developers. It provides complete information on
how to use the STM32L151xx, STM32L152xx and STM32L162xx and STM32L100xx
microcontroller memory and peripherals. The STM32L151xx, STM32L152xx and
STM32L162xx and STM32L100xx value line will be referred to as STM32L1xxxx throughout
the document, unless otherwise specified.
The STM32L1xxxx is a family of microcontrollers with different memory sizes, packages and
peripherals.
For ordering information, mechanical and electrical device characteristics please refer to the
corresponding datasheets.
For information on programming, erasing and protection of the internal Flash memory
please refer to the STM32L15xxx Flash programming manual.
For information on the ARM Cortex™-M3 core, please refer to the Cortex™-M3 Technical
Reference Manual.
Related documents
Available from www.arm.com:
• Cortex™-M3 Technical Reference Manual, available from:
• http://infocenter.arm.com/help/topic/com.arm.doc.ddi0337g/DDI0337G_cortex_m3_r2p0_t
rm.pdf
Available from www.st.com:
• STM32L151xx STM32L152xx datasheets
• STM32L162xx datasheet
• STM32L100xx datasheet
• STM32L15xxx Flash programming manual
• STM32F10xxx/20xxx/21xxx/L1xxxx Cortex-M3 programming manual
Contents
1 Documentation conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
1.1 List of abbreviations for registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
1.2 Peripheral availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
28.5.8 R6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793
28.6 SDIO I/O card-specific operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 794
28.6.1 SDIO I/O read wait operation by SDIO_D2 signalling . . . . . . . . . . . . . 794
28.6.2 SDIO read wait operation by stopping SDIO_CK . . . . . . . . . . . . . . . . 794
28.6.3 SDIO suspend/resume operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795
28.6.4 SDIO interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795
28.7 CE-ATA specific operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795
28.7.1 Command completion signal disable . . . . . . . . . . . . . . . . . . . . . . . . . . 795
28.7.2 Command completion signal enable . . . . . . . . . . . . . . . . . . . . . . . . . . 795
28.7.3 CE-ATA interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 796
28.7.4 Aborting CMD61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 796
28.8 HW flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 796
28.9 SDIO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 796
28.9.1 SDIO power control register (SDIO_POWER) . . . . . . . . . . . . . . . . . . . 796
28.9.2 SDI clock control register (SDIO_CLKCR) . . . . . . . . . . . . . . . . . . . . . 797
28.9.3 SDIO argument register (SDIO_ARG) . . . . . . . . . . . . . . . . . . . . . . . . . 798
28.9.4 SDIO command register (SDIO_CMD) . . . . . . . . . . . . . . . . . . . . . . . . 799
28.9.5 SDIO command response register (SDIO_RESPCMD) . . . . . . . . . . . 800
28.9.6 SDIO response 1..4 register (SDIO_RESPx) . . . . . . . . . . . . . . . . . . . 800
28.9.7 SDIO data timer register (SDIO_DTIMER) . . . . . . . . . . . . . . . . . . . . . 801
28.9.8 SDIO data length register (SDIO_DLEN) . . . . . . . . . . . . . . . . . . . . . . 801
28.9.9 SDIO data control register (SDIO_DCTRL) . . . . . . . . . . . . . . . . . . . . . 802
28.9.10 SDIO data counter register (SDIO_DCOUNT) . . . . . . . . . . . . . . . . . . . 803
28.9.11 SDIO status register (SDIO_STA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804
28.9.12 SDIO interrupt clear register (SDIO_ICR) . . . . . . . . . . . . . . . . . . . . . . 805
28.9.13 SDIO mask register (SDIO_MASK) . . . . . . . . . . . . . . . . . . . . . . . . . . . 807
28.9.14 SDIO FIFO counter register (SDIO_FIFOCNT) . . . . . . . . . . . . . . . . . . 809
28.9.15 SDIO data FIFO register (SDIO_FIFO) . . . . . . . . . . . . . . . . . . . . . . . . 810
28.9.16 SDIO register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810
List of tables
List of figures
Figure 100. Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . . . . . . . . . 351
Figure 101. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . . . . . . . . . 351
Figure 102. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 352
Figure 103. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
Figure 104. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
Figure 105. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
Figure 106. Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354
Figure 107. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 354
Figure 108. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
Figure 109. Output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 355
Figure 110. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
Figure 111. Output compare mode, toggle on OC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
Figure 112. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
Figure 113. Center-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
Figure 114. Example of one-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
Figure 115. Clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
Figure 116. Example of counter operation in encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . 365
Figure 117. Example of encoder interface mode with TI1FP1 polarity inverted . . . . . . . . . . . . . . . . . 366
Figure 118. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
Figure 119. Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
Figure 120. Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
Figure 121. Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . 369
Figure 122. Master/Slave timer example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
Figure 123. Gating TIM2 with OC1REF of TIM3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
Figure 124. Gating TIM2 with Enable of TIM3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
Figure 125. Triggering TIM2 with update of TIM3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
Figure 126. Triggering TIM2 with Enable of TIM3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
Figure 127. Triggering TIM3 and TIM2 with TIM3 TI1 input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
Figure 128. General-purpose timer block diagram (TIM9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
Figure 129. General-purpose timer block diagram (TIM10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
Figure 130. General-purpose timer block diagram (TIM11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
Figure 131. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 404
Figure 132. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 404
Figure 133. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
Figure 134. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
Figure 135. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
Figure 136. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
Figure 137. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
Figure 138. Counter timing diagram, update event when ARPE=1 (TIMx_ARR
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407
Figure 139. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 408
Figure 140. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408
Figure 141. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409
Figure 142. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 409
Figure 143. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
Figure 144. Output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 410
Figure 145. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412
Figure 146. Output compare mode, toggle on OC1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
Figure 147. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
Figure 148. Example of one pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
Figure 149. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
1 Documentation conventions
)#ODE &LASH
MEMORY
&,)4&
$#ODE %%02/-
#ORTEX
- DATA
3YS TEM
32!-
"US MATRIX
$-! $-!
'0)/#
'0)/$
'0)/(
'0)/"
'0)/%
'0)/!
#H
!("