Available online at www.sciencedirect.

com

ScienceDirect
Karbala International Journal of Modern Science 4 (2018) 228e236
http://www.journals.elsevier.com/karbala-international-journal-of-modern-science/

A low phase noise gm-boosted DTMOS VCO design in 180 nm

CMOS technology
Shasanka Sekhar Rout*, Satabdi Acharya, Kabiraj Sethi
Veer Surendra Sai University of Technology, Department of Electronics and Telecommunication Engineering, Burla, 768018, Odisha, India
Received 1 December 2017; revised 26 February 2018; accepted 1 March 2018
Available online 26 March 2018

Abstract

This paper presents the design of a low phase noise voltage controlled oscillator (VCO), which offers higher transconductance
(gm) by the use of parallel MOSFETs. Here, two NMOS transistors are connected in parallel with the cross-coupled NMOS
transistors of a conventional cross-coupled VCO. So, the total negative conductance offered to the circuit to cancel out the parasitic
resistance of the LC-tank is increased. This negative conductance is achieved without dealing with larger transistor size or any other
passive elements. Hence, power dissipation and silicon area are reduced. Further, dynamic threshold MOSFET (DTMOS) with a
capacitive division technique is implemented to increase the voltage swing, leading to a further decrease in phase noise. The
proposed VCO is designed and simulated in UMC 180 nm technology. It achieves a tuning range of 1.58e1.60 GHz about
200 MHz, with 6.09 mW power consumption at 1.1 V supply voltage. The phase noise is obtained
40.6 dBc/Hz at 1 kHz and

120.44 dBc/Hz at 1 MHz respectively. So, it should be used in transceiver and PLL blocks for low voltage and low phase noise
applications.
© 2018 The Authors. Production and hosting by Elsevier B.V. on behalf of University of Kerbala. This is an open access article
under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/).

Keywords: Cross-couple; DTMOS; Phase noise; Transconductance; VCO

1. Introduction devices show a larger flicker noise corner frequency,

Oscillators are broadly used in transceiver circuits
to generate a signal of particular frequencies. Oscilla-
tors are analyzed by considering all the parameters like
tuning range, phase noise, power, area, start-up, etc.
But among them, the most disturbing parameter is the
phase noise, which deviates the output a lot. Close-in
phase noise in CMOS LC oscillators is largely domi-
nated by flicker noise up-conversion. Sub-micrometer
* Corresponding author.
E-mail address: ssrout1988@gmail.com (S.S. Rout).
Peer review under responsibility of University of Kerbala.
leading to a larger phase noise. Therefore, under-
standing and minimization mechanisms of flicker noise
up-conversion are very important to get the lower
phase noise and adorable output.
Phase noise can be generated and affected by
various factors such as: quality factor (Q) of an oscil-
lator, noise of bias current sources, conversion of ad-
ditive noise to phase noise, cyclostationary noise,
current impulse injection, flicker noise up conversion
and noise around higher harmonics. Open loop Q
signifies how much an oscillator rejects the noise and
lower Q leads to higher phase noise [1]. Another factor
that contributes to phase noise is additive noise. The

https://doi.org/10.1016/j.kijoms.2018.03.001
2405-609X/© 2018 The Authors. Production and hosting by Elsevier B.V. on behalf of University of Kerbala. This is an open access article under
the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/).
 S.S. Rout et al. / Karbala International Journal of Modern Science 4 (2018) 228e236
additive noise around ±u0 (fundamental frequency)
having a two sided spectral density with a peak of ƞ,
results in a phase noise spectrum with a normalized
spectral density and a peak of 2ƞ/A2. More to it, as an
oscillator performs noise modulation periodically,
noise sources in transconductor are considered to be
cyclostationary, which appear as phase noise later [2].
Phase noise also depends on start-up conditions. If the
current impulse is injected at the peak of the output
voltage, it leads to amplitude variation, which does not
affect the phase of the signal [1,3,4]. But, if the current
impulse is injected at the zero crossing of the output
voltage, a voltage jump appears which leads to phase
change [1,3,5]. The most significant phenomenon
leading the close-in phase noise (noise near to the
fundamental frequency) is up-conversion of flicker
noise to 1/f3 noise [1,3,6]. Along with this, higher
harmonics of impulse sensitivity function and noise
current at even harmonics also get translated to phase
noise around fundamental frequency [4,6]. Low fre-
quency components also get up converted around ±u0
[6]. Noise at higher harmonics of bias current gets
converted to the phase noise around ±u0 [6e8].
The active device parasitic also plays a significant
role. Flicker noise of active device modulates output
common mode (CM) level and it produces amplitude
modulation (AM) at the output. This leads to phase
noise through AM-PM conversion in varactors due to
nonlinear parasitic capacitances [2,4,9e11].
The dominant contributors to phase noise are the
transconductor active devices, whose flicker noise is
up-converted via three mechanisms, such as: (i)
Amplitude to phase noise translation due to nonlinear
tank varactors [10,11]. (ii) Amplitude to phase noise
renovation due to nonlinear transconductor parasitic
capacitance [12]. (iii) Modulation of the harmonic
content of the output voltage waveform, (Groszkowski
effect) [7,13,14].
To get a useful oscillator output, phase noise should
be minimized. Many different approaches are imple-
mented in previous research works to decrease the 1/f
noise contribution to the phase noise. The techniques
include use of p-channel devices, which have a decade
lower 1/f noise than n-channel devices [1,2]. The
capacitive coupling is used to suppress the 1/f noise
up-conversion in the differential oscillator. Replace-
ment of the current source with a tank circuit to remove
the 1/f noise contribution of the tail current also works
effectively [7,13,15]. The symmetric VCO design
approach and the body bias control technique are also
valuable for the circuit operation [16].
229
Besides the methods meant for 1/f noise reduction,
other methods can be used as remedies for phase noise
reduction, which is described in the following section.
With the use of a bank of digital-switchable capacitors,
AM-PM conversion in varactors, can be minimized
[11,17]. This solution drastically reduces the tank
capacitance nonlinearity without impairing the overall
VCO tuning range. Small area transistors are helpful in
reducing AM-PM conversion due to parasitic capaci-
tances [10]. In Refs. [16,18] the voltage biased topol-
ogy which is intrinsically less prone to amplitude
modulation is used. Effective phase noise diminution
of the oscillator can be attained by increasing the tank
quality factor [1]. The solution given in Refs. [19e21]
diminishes harmonic generation and so the Grosz-
kowski effect, but at the expenses of overload gain and
the start-up margin.
The increment of output voltage swing and quality
factor of the oscillator can be achieved by decreasing
the threshold voltage (Vth) and increasing the effective
negative conductance (Gm) of the circuit. From another
point of view, the demand for low power and high
performance systems has also grown rapidly and the
main approach for reducing power has relied on power
supply scaling. Since power supply reduction below
3Vth will degrade the circuit speed significantly,
scaling of power supply should be accompanied by
threshold voltage reduction. However, the lower limit
for threshold voltage is set by the amount of off-state
leakage current that can be tolerated. To extend the
lower bound of power supply, DTMOS are used with
the highest Vth at zero bias and the lowest Vth at
maximum bias (V ¼ VDD) [8]. So, instead of normal
MOSFETs or static body-biased MOSFETs, use of
DTMOSs is useful for reduction of both phase noise
and power consumption [22].
The proposed VCO is designed with two tech-
niques. Firstly, the use of parallel MOSFETs with the
cross-coupled pair, which boost the effective trans-
conductance (gmeff) and secondly, replacing all con-
ventional MOSFETs with DTMOSs. Since DTMOS
has lower Vth, the output voltage swing increases. As a
result, there is a lower phase noise operation [16].
However, in DTMOS, a capacitive division circuit is
connected in between the drain and source. The body is
connected dynamically to the drain through the
capacitive division circuit. This arrangement over-
comes body-source pn-junction forward biasing prob-
lem, leading to lower leakage current and lower noise.
The design and analysis of the proposed circuit are
presented in section 2. The simulation results and
230 S.S. Rout et al. / Karbala International Journal of Modern Science 4 (2018) 228e236
comparison table are given in section 3, while section 4
concludes finally.
2. Circuit design and analysis
2.1. gm-boosted MOSFET VCO
One of the major contributing factors for phase
noise is the transconductance (gm) of a transistor. It
points to the negative conductance offered by the
active core of VCO, which cancel out the parasitic
resistance of the inductor. So a larger value of gm en-
hances quality factor (Q) of resonator [1]. This higher
Q value lowers the phase noise. In other words,
boosting of gm enhances Q, which results in lower
phase noise.
Here, two extra MOSFETs are connected in parallel
with the cross-coupled pair, to increase the effective
transconductance. Fig. 1 shows the VCO configuration
Fig. 1. gm-boosted MOSFET VCO design.
Fig. 2. Half circuit small signal equivalent circuit of Fig. 1.
consisting of two extra MOSFETs (M3 and M4), which
are connected parallel to the original cross-coupled
pairs (M1 and M2). The gates of M1 and M3 (M2 and
M4) are tied to the drain of the opposite cross coupled
transistor, M2 and M4 (M1 and M3). Fig. 2 shows the
half circuit small signal equivalent circuit of Fig. 1,
which is used to analysis the negative conductance and
the quality factor.
The negative conductance offered by the parallel
transistors reduces the total output conductance, which
enhances the output swing and quality factor. This
improves the phase noise performance of the VCO.
The voltage gain of the oscillator is given by Eq (1):
1
Av ¼ Gmeff  ð1Þ
GT
where Gmeff is the effective transconductance of the
amplifier, GT is the total conductance, which includes
GA (conductance at the drain of M1 and M3) and GL
(equivalent parallel conductance of the inductor. GL has
a dominant effect in total conductance. So, GT is given
by:
GT ¼ GL þ GA ð2Þ
Further, GL is represenred by:
1 Rs
GL ¼ z ð3Þ
Rs ðQ2 þ 1Þ ðuLÞ2
where Rs and Q are the series equivalent resistance and
the quality factor of the inductor respectively and
L ¼ LTANK/2. The loaded Q of the above connection is
written as:
rffiffiffiffiffiffi
1 CT
QL ¼ ð4Þ
GT L
where CT is the total capacitance at the drain of M1 and
M 3.
 S.S. Rout et al. / Karbala International Journal of Modern Science 4 (2018) 228e236 231

From Fig. 2, it is shown that the negative conduc-

tance generated is:
GA ¼
gm1
gm3 ¼
2gm ð5Þ

Here, parasitic capacitances are neglected for

negative conductance calculation. So, GT becomes
Rs
GT ¼ GL þ GA ¼ 2
2gm ð6Þ
ðuLÞ

From Eqs. (1), (4) and (6), it is observed that as GT

is reduced, Av and Q are increased. Thus the phase
noise is improved proportionally to the voltage
amplitude (gain) and quality factor [1]. Fig. 3 shows
the phase noise plot and Fig. 4(a) and (b) shows the
output power level and a power dissipation plot of the
VCO circuit described in Fig. 1 respectively. Fig. 5
represents the oscillation output of the above said
circuit.

2.2. DTMOS VCO with capacitive division technique

Conventional static body biasing technique de-

creases the threshold voltage of the MOSFETs, the
supply voltage and power consumption, as shown in
Fig. 6(a). But, the limitation with this configuration is
the pn-junction between the body and the source. It
gets forward biased at large body-bias voltage and
increases the leakage current resulting in more power
consumption. Further, the use of the static body biasing
technique in VCO circuits lowers the quality factor of
the resonator, which offers poor phase noise perfor-
mance. Thus, there are limitations for low voltage and
low power applications. To overcome these problems, Fig. 4. (a) Output power level plot of Fig. 1. (b) Power dissipation
DTMOS are used in place of conventional MOSFETs. plot of Fig. 1.
Fig. 6(b) shows a DTMOS in which the body is tied
to the gate [8,22]. This decreases the threshold voltage

Fig. 3. Phase noise plot of Fig. 1. Fig. 5. Oscillation output of Fig. 1.

232 S.S. Rout et al. / Karbala International Journal of Modern Science 4 (2018) 228e236

Fig. 6. (a) Static body biasing. (b) Dynamic body biasing with gate tied to body. (c) Proposed capacitive division body biasing.

statically and dynamically, such that the supply voltage where Vth0 is the native threshold voltage, g is the body
and power consumption are significantly reduced [2]. It effect coefficient, FF is the work function of the silicon
also offers faster start-up as it gives higher net trans- substrate, and VS and VG are the source and gate volt-
conductance (Gm ¼ gm þ gmb) than that of static body ages, respectively. For simplicity of analysis, the para-
biasing technique (Gm ¼ gm). Normal VCOs charac- sitic capacitance is neglected due to the large
terize a larger output swing, which introduces the capacitance of C1 and C2.
forward biased pn-junction and thus degrades the From small signal model, the net transconductance
phase noise performance. So, VCOs using this type of of the circuit (Fig. 6(c)) is expressed as:
DTMOS have to have a limited output swing. Thus, gm gmb C1
this technique can only be useful for low voltage ap- Gm ¼
þ ð8Þ
2 2ðC1 þ C2 Þ
plications. Other complicated dynamic body biasing
circuits [16,22e24] are used, in order to avoid forward where the channel-length modulation effect is neglec-
biasing of the body-source pn-junction, which losses ted. DTMOS VCO employing the proposed capacitive
the body transconductance (gmb) and the fast start-up division technique preserves the advantages of the
of the DTMOS VCO. conventional DTMOS VCO, like higher net trans-
This work proposes a simple capacitive division conductance, the fast start-up condition with low supply
technique to improve the issues of the DTMOS VCO: voltage and power consumption. VCO using DTMOS is
swing and phase noise, which is shown in Fig. 6(c). In described in Fig. 7.
addition, it maintains a high net transconductance (gm)
and fast start-up proportionally to the capacitive divi-
sion ratio, which are the merits of the DTMOS VCO.
The phase noise performance is proportional to the
amplitude of the output swing. However, the conven-
tional DTMOS VCO requires a low output swing, so
that the body-source pn-junction is not forward biased.
To address this issue, this work proposes a capacitive
division structure that drives the body to decrease the
threshold voltage statically and dynamically, even with
a high output swing as follows:
Vth ¼ Vth0
sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
   !
 C  pffiffiffiffiffiffi
þg 2FF þ Vs
1
VG 
2 FF
 C1 þ C2
ð7Þ Fig. 7. DTMOS VCO with capacitive division technique.
 S.S. Rout et al. / Karbala International Journal of Modern Science 4 (2018) 228e236
The capacitance ratio changes the threshold voltage
(Eq. (7)), the dc current and thus the swing amplitude
that is proportionally related to the dc current. In
Fig. 6(c), as the capacitance ratio increases, the output
swing increases in the current limited regime. Thus, the
phase noise performance improves as the phase noise
depends on the output swing and the Q-factor. But,
before the voltage limited regime, that output swing
Fig. 8. Phase noise plot of Fig. 7.
Fig. 9. (a) Output power level plot of Fig. 7. (b) Power dissipation
plot of Fig. 7.
233
decreases due to the forward biased pn-junction, which
degrades the phase noise.
The VCO phase noise is also affected by the AM to
PM conversion due to the varactors and parasitic
capacitance [19]. The static body biasing VCO has a
larger swing amplitude and thus better phase noise than
the DTMOS VCO. Compared to the static body biasing
VCO, the capacitive division DTMOS VCO has
similar swing amplitude, but reduced AM to PM
conversion due to the dividing capacitors, although it
somehow decreases a frequency tuning range. There-
fore, the phase noise performance is improved.
Fig. 8 shows a phase noise plot of VCO circuit
using DTMOS (as described in Fig. 7). Output power
level and power dissipation are shown in Fig. 9(a) and
9(b) respectively. The oscillation output DTMOS VCO
employing capacitive division technique is represented
in Fig. 10.
Fig. 10. Oscillation output plot of Fig. 7.
Fig. 11. Schematic of proposed VCO.
234 S.S. Rout et al. / Karbala International Journal of Modern Science 4 (2018) 228e236
2.3. Proposed gm-boosted DTMOS VCO with capac-
itive division technique
From Ref. [1], it can be studied that 1/f3 phase noise
corner frequency is directly proportional to gm of in-
dividual MOSFET. So increasing gm will lead to higher
phase noise. On the other hand, the phase noise
Fig. 12. Tuning range of the proposed VCO.
Fig. 13. (a) Frequency variation with supply voltage of proposed
VCO. (b) Oscillator output of proposed VCO.
spectrum is inversely dependent on Q-factor and higher
effective gm improves the Q-factor. Hence, increasing
effective gm will lead to lower phase noise. Therefore,
a moderate gm value will do the required task. Section
2.1 describes the technique for increasing the effective
gm to reduce phase noise. Section 2.2 describes how
DTMOS with capacitive body biasing technique
lowers gm by gmbC1/(C1þC2) and improves phase
noise and output voltage swing. So application of both
concepts to the standard MOSFET VCO optimizes the
phase noise. Fig. 11 shows the proposed VCO, with
both the techniques described above. Now from Eq. (5)
and Eq. (8), the effective gm will be calculated as:
 
3gm gmb C1
Gm ¼

ð9Þ
2 2ðC1 þ C2 Þ
3. Results and discussion
The proposed VCO is implemented with 0.18 mm
CMOS technology in cadence tool. The tank
Fig. 14. (a) Output power level of proposed VCO. (b) Power dissi-
pation of proposed VCO.
 S.S. Rout et al. / Karbala International Journal of Modern Science 4 (2018) 228e236 235

capacitor banks. This design consumes 6.09 mW

Fig. 15. Phase noise plot of the proposed VCO.
power at a supply voltage of 1.1 V.
Fig. 13(a) represents frequency variation with the
change in supply voltage (frequency pushing), whereas
Fig. 13(b) shows the VCO output waveform. From
Fig. 14(a), the output power level is found to be
27.86 mW and Fig. 14(b) shows the power dissipation
of the circuit to be 6.09 mW. As shown in Fig. 15, the
phase noise is found to be
120.44 dBc/Hz and
40.6
dBc/Hz at 1 MHz and 1 KHz offset frequency
respectively. The layout of the proposed design is
shown in Fig. 16.
Table 1 compares the performance of the VCOs
described in sections 2.1e2.3.
Table 2 represents the performance comparison of
the proposed VCO with VCOs those are available in
the literature [5,16,24].
The proposed work indicates a phase noise of

120.44 dBc/Hz, which is better, when compared to

110 dBc/Hz of [5] and
113.7 dBc/Hz of [24]. Here,
due to the use of DTMOS, lower value of Vth is ob-
tained, which results in higher voltage swing and
accordingly lower phase noise. This work also con-
sumes 6.09 mW power, which is achieved due to the
lowering of Vth value. In Table 2, all the previous
works are implemented with lower channel length and
lower supply voltage, so the power consumption of
those works is lower in comparison to the proposed
work, which is implemented in 180 nm technology.
The proposed VCO oscillates at maximum frequency
of 1.60 GHz.

4. Conclusion

The proposed VCO by using gm-boosting parallel

MOSFETs and dynamic threshold MOSFET
Fig. 16. Layout of the proposed VCO. (DTMOS) is designed and implemented with 0.18 mm
CMOS process. The gm-boosting method using parallel
cross-coupled pair increases effective trans-
parameters are selected to obtain a frequency of conductance of the circuit. So, Q-factor and output
2.4 GHz. But, the frequency range is obtained from voltage swing get enhanced leading to phase noise
1.58 to 1.60 GHz (about 200 MHz) with a control improvement. Use of DTMOS brings even higher
voltage variation from 0.7 V to 1.1 V (Fig. 12). The voltage swing with lower supply voltage. It also de-
frequency range can be increased by employing creases transconductance by gmbC1/(C1þC2), which
Table 1
Performance comparison of three proposed VCOs.
VCO circuit Frequency Supply Power Output power Phase noise in Phase noise in dBc/Hz
(GHz) voltage (v) Dissipation (mW) level (mW) dBc/Hz (1 KHz offset) (1 MHz offset)
gm boosted MOSFET 1.8 1.1 6.08 27.93
24
112
DTMOS with Capacitive 1.8 1.1 3.81 27
33.3
118.23
division technique
Both 1.6 1.1 6.09 27.86
40.6
120.44
236 S.S. Rout et al. / Karbala International Journal of Modern Science 4 (2018) 228e236
Table 2
Performance comparison of different VCOs.
Ref. Technology Frequency Supply Power
(GHz) Voltage (v) Dissipation (mW)
[5] 65 nm 3.3 1.2 0.72
[16] 0.13 mm 3.57 0.3 0.22
[24] 65 nm 5.71 0.6 0.42
This work 0.18 mm 1.60 1.1 6.09
reduces 1/f3 corner frequency resulting in lower close-
in phase noise. The proposed VCO design generates
the phase noise of
120.44 dBc/Hz and
40.6 dBc/Hz
at 1 MHz and 1 KHz offset frequency respectively. The
design operates on 1.1 V with a power consumption of
6.09 mW. This design optimizes the swing amplitude
and the Q value to get lower phase noise. It also pro-
tects from forward biasing of the body-source pn-
junction due to the use of DTMOS with the capacitive
division concept. Therefore the proposed VCO should
be used in transceiver front end design.
Acknowledgments
All the simulations and implementation are carried
out in the Laboratory of Department of Electronics &
Telecom., VSSUT, Odisha, India. This study did not
receive funding from any agencies.
References
[1] A. Hajimiri, T.H. Lee, A general theory of phase noise in
electrical oscillators, IEEE J. Solid-State Circuits 33 (2) (1998)
179e194.
[2] J. Phillips, K. Kundert, Noise in mixers, oscillators, samplers, and
logic an introduction to cyclostationary noise, in: Proc. IEEE
Custom Integr. Circuits Conf. (CICC), 2000, pp. 431e438.
[3] K. Hoshino, E. Hegazi, J.J. Rael, A.A. Abidi, A 1.5 V, 1.7 mA
700 MHz CMOS LC oscillator with no upconverted flicker
noise, in: Proc. IEEE Eur. Solid-State Circuits Conf. (ESS-
CIRC), 2001, pp. 337e340.
[4] B. Razavi, A study of phase noise in CMOS oscillators, IEEE J.
Solid-State Circuits 31 (1996) 331e343.
[5] F. Pepe, A. Bonfanti, S. Levantino, C. Samori, A.L. Lacaita,
Suppression of flicker noise up-conversion in a 65 nm CMOS
VCO in the 3.0-to-3.6 GHz band, IEEE J. Solid-State Circuits
48 (10) (2013) 2375e2389.
[6] A. Bonfanti, F. Pepe, C. Samori, A.L. Lacaita, Flicker noise up-
conversion due to harmonic distortion in Vander Pol CMOS
oscillators, IEEE Trans. Circuits Syst. I: Reg. Papers 59 (7)
(2012) 1418e1430.
[7] E.A. Vittoz, M.G.R. Degrawe, S. Bitz, High-performance
crystal oscillator circuits: theory and application, IEEE J. Solid-
State Circuits 23 (3) (1988) 774e783.
[8] S. Levantino, C. Samori, A. Zanchi, A.L. Lacaita, AM-to-PM
conversion in varactor-tuned oscillators, IEEE Trans. Circuits
Syst. II: Analog Digit. Signal Process 49 (7) (2002) 509e513.
Phase noise in Phase noise in dBc/Hz
dBc/Hz (1 KHz offset) (1 MHz offset)

47
110
e
116.88

43.3
113.7
¡40.6 ¡120.44
[9] A. Bonfanti, S. Levantino, C. Samori, A.L. Lacaita, A varactor
configuration minimizing the amplitude-to-phase noise con-
version in VCOs, IEEE Trans. Circuits Syst. I: Reg. Papers 53
(3) (2011) 481e488.
[10] J.H. Lee, S.Y. Kim, I. Cho, S. Hwang, J.H. Lee, 1/f noise
characteristics of sub-100 nm MOS transistors, J. Semicond.
Tech. Sci. 6 (1) (2006) 37e41.
[11] A. Hajimiri, T. Lee, Design issues in CMOS differential LC
oscillators, IEEE J. Solid-State Circuits 34 (5) (1999) 717e724.
[12] A. Bevilacqua, P. Andreani, On the bias noise to phase noise
conversion in harmonic oscillators using Groszkowski theory,
in: Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), 2011,
pp. 217e220.
[13] E. Hegazi, A.A. Abidi, Varactor characteristics, oscillator tun-
ing curves, and AM-FMconversion, IEEE J. Solid-State Circuits
38 (6) (2003) 1033e1039.
[14] N.N. Tchamov, N.T. Tchamov, Technique for flicker noise up-
conversion suppression in differential LC oscillators, IEEE
Trans. Circuits Syst. II: Expr. Briefs 54 (11) (2007) 481e488.
[15] E. Hegazi, H. Sjoland, A.A. Abidi, A filtering technique to
lower LC oscillator phase noise, IEEE J. Solid-State Circuits 36
(12) (2001) 1921e1930.
[16] S.L. Jang, C.J. Huang, C.W. Hsue, C.W. Chang, A 0.3 V cross-
coupled VCO using dynamic threshold MOSFET, IEEE
Microw. Wireless Compon. Lett. 20 (3) (2010) 166e168.
[17] S. Levantino, C. Samori, A. Bonfanti, S. Gierkink, A.L. Lacaita,
Frequency dependence on bias current in 5-GHz CMOS VCO's:
impact of tuning range and flicker noise up-conversion, IEEE J.
Solid-State Circuits 37 (8) (2002) 1003e1011.
[18] A. Koukab, Reactive power imbalances in LC VCOs and their
influence on phase-noise mechanisms, IEEE Trans. Microw.
Theory Tech. 59 (12) (2011) 3118e3128.
[19] F. Pepe, A. Bonfanti, S. Levantino, C. Samori, A.L. Lacaita,
Analysis and minimization of flicker noise up-conversion in
voltage-biased oscillators, IEEE Trans. Microw. Theory Tech.
61 (6) (2013) 2382e2394.
[20] S.J. Yun, C.Y. Cha, H.C. Choi, S.G. Lee, RF CMOS LC-
oscillator with source damping resistors, IEEE Microw. Wire-
less Compon. Lett. 16 (9) (2006) 511e513.
[21] B. van der Pol, The nonlinear theory of electric oscillations,
Proc. IRE 22 (1934) 1051e1086.
[22] F. Assaderaghi, S. Parke, D. Sinitsky, J. Bokor, P.K. Ko, C. Hu,
A dynamic threshold voltage MOSFET (DTMOS) for ultra-low
voltage operation, IEEE Electron. Device Lett. 15 (12) (1994)
510e512.
[23] S.L. Jang, C.F. Lee, A low voltage and power LC VCO
implemented with dynamic threshold voltage MOSFETS, IEEE
Microw. Wireless Compon. Lett. 17 (5) (2007) 376e378.
[24] J. Sun, C.C. Boon, X. Zhu, X. Yi, K. Devrishi, F. Meng, A low-
power low-phase-noise VCO with self-adjusted active resistor,
IEEE Microw. Wireless Compon. Lett. 26 (3) (2016) 201e203.