Int. j. inf. tecnol.
https://doi.org/10.1007/s41870-021-00687-x
ORIGINAL RESEARCH
Configurable memory designs in quantum-dot cellular automata
Mrinal Goswami1,2 • Rohit Tanwar2 • Prashant Rawat2 • Bibhash Sen1
Received: 2 July 2020 / Accepted: 19 April 2021
Ó Bharati Vidyapeeth’s Institute of Computer Applications and Management 2021
Abstract Quantum-dot cellular automata (QCA) has the
capability to scale down beyond the range of CMOS.
Besides wide acceptance of QCA, it suffers from different
challenges, regular structure and configurability is one of
them. The disparate design in QCA increases design
complexity as well as cost. The disparity of design needs
different clocking layout for the correct propagation of
signals. Moreover, the interconnection of these non-sym-
metric designs also increases the routing difficulty in a
specific, realistic clocking scheme. In this paper, config-
urable memory structures are investigated in QCA. First of
all, a configurable level triggered flip flop (ConFF) is
realized. The same ConFF is utilized to design configurable
dual edge triggered flip-flop (EConFF) with some minor
modification. Nine different logic functions can be pro-
duced using the same EConFF circuit which is not found in
any existing QCA circuit.The proposed configurable
structures are verified with QCADesigner 2.0.3.
This submitted manuscript is an extended version of ‘‘A Realistic
Configurable Level Triggered Flip-Flop in Quantum-Dot Cellular
Automata’’ which is published at VDAT 2019, CCIS 1066, pp. 455-
467, 2019, DOI: https://doi.org/10.1007/978-981-32-9767-8_38. To
the best of my knowledge, 60% new work has been included with the
existing version of the paper.
& Mrinal Goswami
mgoswami@ddn.upes.ac.in
1
Department of Computer Science and Engineering, National
Institute of Technology Durgapur, Durgapur, West Bengal,
India
2 clocking scheme. In this regard, the configurable realiza-
Department of Systemic, School of Computer Science,
University of Petroleum and Energy Studies, Bidholi,
Dehradun 248007, India
Keywords Clock pulse generator  Field coupled
nanotechnology  Flip-flop  Quantum-dot cellular
automata (QCA)  Configurable logic
1 Introduction
Current CMOS VLSI encounters several feature size
restrictions such as high leakage current, and high lithog-
raphy cost. Further, the down-scaling of CMOS does not
necessarily provide reductions in wire crossing. The
demand for alternative efficient computing paradigms
compels the removal of state-of-the-art digital computation
with emerging nanoelectronics. Quantum-dot cellular
automata (QCA) emerges as a promising nanoelectronic to
put back CMOS to give fast-paced devices at the nano-
electronics era [3, 18, 23].
Despite several favorable features, quantum-dot cellular
automata (QCA) encounters structural restrictions such as
highly sensitive to cell position/layout, reduced fault tol-
erance, limited field coupling strength and disparate
structure. The disparate design structure in QCA increases
design complexity as well as cost. The underlying clocking
arrangements have to be changed for a different circuit of
the same logic. It is better to have a similar structure so that
the logic propagation can be controlled by the same
clocking circuitry. Moreover, the interconnection of non-
symmetric designs increases the routing difficulty in any
realistic clocking scheme. So, to tackle these issues, a
consistent design methodology has to be explored. It is
always welcome symmetric modular design style so that it
can easily be mapped to any regular fabrication friendly
tion of QCA designs shows a ray of hope other than the
designs with different designs and areas.
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The flexibility of any reconfigurable circuit depends on
its building blocks. It is observed that flip-flop is the most
widely used building block in any reconfigurable circuit.
Hence, the configurable behavior of QCA flip-flops is
investigated here. QCA based flip-flops were studied
extensively [6, 14, 24, 25, 30, 37, 39, 40] due to its number
of applications. However, previous all these designs are
dis-similar and interested more to reduce area as well as
latency. No one provides any common methodology to
reduce the dis-similarity of these existing designs. Abu-
taleb et al. took account of this problem and introduced a
configurable flip-flop for the very first time in QCA [2].
However, it fails to generate an inverted output (Q), and
also, the output of the realistic version (USE clocking
version) of the proposed design is in a closed-loop. This
means, except multi-layering, it is not possible to connect
the output node. It is worth to mention here that multi-layer
cross-over in QCA has four times higher complexity than
the coplanar cross-over [20].
This paper takes account of all the factors discussed in
the last paragraph. The key points of this paper are listed
below:
– The design of the configurable level-triggered QCA
flip-flop (ConFF) is presented.
– The ConFF can produce three logic functions as and
when required.
– An efficient universal clock pulse generator (CPG) is
proposed, which can trigger all types of pulses.
– The configurable dual edge-triggered (EConFF) version
is also proposed with the help of CPG.
– An n-bit configurable counter, which can be configured
to shift register also, is proposed.
The whole manuscript is divided into the following sec-
tions: Sect. 2 introduced an overview of quantum-dot cel-
lular automata (QCA). Next Sect. 3, discuss some related
works based on configurable logic. Section 4 will introduce
ConFF. EConFF is investigated in Sect. 6. The complex
QCA configurable circuits are investigated in Sect. 7 fol-
lowed by a conclusion.
2 QCA background
QCA cell is considered as the most elementary unit of
QCA technology. It has four quantum-dots situated at each
corner of the square-shaped QCA cell (Fig. 1a). It can
occupy two free electrons, which can locomote within a
pair of quantum-dots in that same cell. Figure 1b shows an
orientation of a QCA cell and its possible two polarization.
A QCA cell can only reside in any of the two possible cell
polarization state i.e., either Pol = 1 (Binary 1) or Pol = 1
(Binary 0).
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Int. j. inf. tecnol.
(a) (b)
(c) (d)
Fig. 1 QCA fundamentals a quantum dots, b QCA cells, c majority
voter, d inverter
QCA is a majority logic-based technology where cir-
cuits are composed of two principal gates, majority voter
(Fig. 1c) and inverter (Fig. 1c). The majority voter has two
different configuration such as AND gate as well as OR
gate. AND realization is possible if any input is fixed at Pol
= 1. Alternatively, if any input is fixed at Pol = 1, the gate
will behave as OR gate.
There are two types of wires found in QCA, as shown in
Fig. 2. A 90° or coplanar wire can be formed with the help
of several ‘X’ shaped QCA cells (Fig. 2a), whereas a 45° or
rotating wire can be formed with the help of ‘?’ shaped
QCA cells (Fig. 2b). Further, coplanar wire-crossing can be
implemented using ‘?’ shaped and ‘X’ shaped QCA cells
in the same plane, as shown in Fig. 3
2.1 QCA clocking
The switching of QCA arrays is a big concern to design a
stable QCA system. The physical ground states provide an
advantage to QCA technology [13, 17]. But, it needs to
map with the logical solution of the problem for which the
device is designed to solve. Any QCA system can be in
some excited states (i.e., mixer of polarization Pol = 1 and
Pol = 1 in the same QCA system) if the input of the
system is switched abruptly. This leads to a
metastable state, and it could cause delay to arrive at its
stable ground state [29, 35]. Thus to avoid such problems,
adiabatic switching comes into the picture. According to
Refs. [17, 21, 41], a QCA clock required four phases
(switch, hold, release, and relax) for an adiabatic pipelining
cycle, as shown in Fig. 4. In the first phase, the inter-dot
barriers are upraised, which polarized the QCA cell. In the
IN OUT IN OUT
(a) Wire with ’X’ cells (b) Wire with rotating cells or ’+’ cells
Fig. 2 Two different types of QCA wire
Int. j. inf. tecnol.
Input 1
’X’ Cell
Input 2 Output 2
’+’ Cell
Output 1
Fig. 3 Wire-crossing in QCA
Fig. 4 QCA clocking
hold phase, the inter-dot barriers are so high that the
polarization of the QCA cells can not be changed from an
external source; hence it retains its polarization. In the
release phase, sinking inter-dot barriers provides unpolar-
ization of these cells. Finally, in the relax phase, it retains
unpolarized state until and unless a new adiabatic
pipelining cycle starts.
Clocking is the kernel of a QCA circuit, and it obeys the
rules of adiabatic switching. QCA clock drives information
from one end to another end, which is the only source of
information synchronization [16]. One clock zone accom-
modates two or more QCA cells. Four different numbers
(0, 1, 2 and 3) are used to specify different clock zones. In
QCA, three well-known clocking scheme is available in
QCA - 2DDWave [31], RES [12] and USE [10]. In this
paper, the USE clocking scheme is used to describe the
realization efficacy of the proposed designs. The USE
(universal, scalable, and efficient) clocking scheme is
considered as the best clocking scheme introduced in QCA
so far. The main idea behind this clocking scheme is that
adjacent clock zones must place sequentially one after
another to drive correct information from input to output.
3 Related work
Devadoss et al. explore configurable and programmable
QCA structure by realizing tiled programmable fabric and
named it as p-QCA [11]. p-QCA has an advantage over
other programmable structures due to its symmetric struc-
tures and also it is easy to modify. Another attempt to
realize a programmable array of logic (PLA) utilizing a
geometric layout of QCA is found in Ref. [28]. Recently, a
programmable crossbar network has been investigated
where a novel QCA inverter gate is introduced which can
support crossbar architectures [15]. Configurable memory
structure in QCA is first investigated in Ref. [2]. The
proposed configurable flip-flop (CFF) consists of three
modules: programmable signal width block (PSWB), pro-
grammable signal sign block (PSSB), and programmable
bit storage block (PBSB). The PSSB block behaves like
wire or inverter. PSWB block behaves as a pulse generator
and PBSB behaves as a bit storage. These blocks are cas-
caded to construct the proposed CFF, which has the
potential to produce D as well as T flip-flop. However, the
CFF can not generate inverted output (Q) from the design
itself. Moreover, the most serious concern of the proposed
design is that most of the inputs and outputs are surrounded
by closed loops. Thus, without multi-layer wire-crossing, it
is not possible to connect these nodes from outside.
4 Proposed configurable level triggered flip-flop
The proposed configurable level triggered flip-flop (in
short ConFF) is presented in this section. The proposed
ConFF, is shown in Fig. 5, have five inputs in total (K, L,
C1 , C2 and CLK). Input K and L are the primary inputs of
ConFF. Inputs C1 and C2 acts as control inputs and the
behavior of ConFF with C1 and C2 is presented in Table 1 .
The ConFF would behave as T FF if input C1 is fixed at
zero and input C2 fixed at one. If both the inputs C1 and C2
are fixed at zero, then ConFF act as D FF. The ConFF will
follow the rules of JK FF if input C1 is set, and input C2 is
fixed with X (here X denotes don’t care). The final output
of ConFF is as follows:
Qtþ1 ¼ fK:Qt þ fK:LðC1 þ C2 Þ þ K:LðC1
þ C2 Þ þ L:C1 þ C1 ðK:C2 þ K:C2 ÞgQt gCLK þ CLK:Qt
ð1Þ
The complete design can be divided into three units:
UNIT 1 (XNOR), UNIT 2 (2:1 MUX) and UNIT 3 (JK FF).
These units need to work together to generate the correct
output (Qtþ1 ). The working function of each unit is
explained below:
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Fig. 5 QCA configurable level triggered flip-flop (ConFF)
Table 1 The functional power of ConFF
Input (C1) Input (C2) Output (Q)
0 0 D FF
0 1 T FF
1 X JK FF
X don’t care
4.1 UNIT 1 (XNOR)
This unit have two inputs C2 and K and one output
(f1 ¼ K:C2 þ K:C2 ). Output (f1 ) of unit 1 is forwarded to
unit 2, which acts as an input for unit 2 as shown in Fig. 5.
Input C2 plays a key role in unit 1 as depending on the
value of input C2 ; unit 1 produces an uncomplemented or
complemented value of input K. If input C2 is fixed at zero,
then K is transferred to unit 2 else input K directly is
forwarded to unit 2.
4.2 UNIT 2 (2:1 MUX)
The primary output of unit 2 is f2 ¼ L:C1 þ f1 :C1 . The
effect of f1 is nullified if input C1 is set to 1. This means
input value of L is passed to unit 2 and unit 3 will act as a
JK flip-flop. Output f1 plays an important role in unit 2 as
depending on it, unit 2 act as D or T flip-flop (fixing C1 at
zero). If f1 ¼ A then the unit 3 act as D else as T flip-flop.
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4.3 UNIT 3 (JK FF)
This unit 3 is heavily depended on unit 1 and 2. It act as a T
FF if unit 1 generates f1 = K and at the same time unit 2
forward f2 = f1 . On the other hand, if unit 1 generates
f1 ¼ K and at the same time unit 2 forward f2 = f1 then unit
3 act as a D flip-flop. At the end, unit 3 acts as JK flip-flop,
if unit 2 produces f2 = L (unit 1: f1 = don’t care).
The ConFF design is capable of producing D, T, and JK
FF functions (degree of configurability is equal to 3). The
ConFF is compared with the existing level-triggered flip-
flops, and it is shown in Table 2. The proposed ConFF has
the potential to generate three logic functions using the
same circuit. The existing flip-flops are capable of pro-
ducing only one function. The configurable memory units
can be utilized in various area-efficient cost-effective
applications due to its architectural similarity, which
eliminates the need for separate hardware performing a
specific function.
4.4 USE clock implementation of ConFF
As we already discussed in the background section that for
the correct propagation of clocking signals, circuits need to
realize with a regular clocking scheme. To the best of my
knowledge USE clocking scheme is the most widely
accepted scheme in QCA [10]. Thus, the proposed ConFF
is converted to USE scheme (ConFF-USE) as shown in
Fig. 6. The ConFF-USE utilizes an area of 1.81 lm2 with
541 QCA cells. Table 3 compared the proposed ConFF-
USE with the existing design proposed in Ref. [2]. The
USE implementation (CFF-USE) proposed in Ref. [2] does
not follow the standard grid specification (5  5) mention
in Ref. [10]. Also, the CFF-USE can produce only two
functions (D and T), whereas the proposed ConFF-USE can
produce three different functions using the same circuit.
CFF-USE fails to produce an inverted output (Q) form the
design itself; however, it can be easily generated using the
proposed ConFF-USE. Moreover, the output of the pro-
posed ConFF-USE can be easily reached by using any
wire-crossing found in QCA. On the other hand, CFF-USE
primary output is inside a closed-loop, and hence multi-
layer wire-crossing is the only way to touch that output. It
is also worth to mention that the implementation com-
plexity of multi-layer wire-crossing is much higher than
any other wire-crossing found in QCA [20].
The level-triggered JK flip-flop is susceptible to noise
due to which it leads to race-around condition [40]. In
order to avoid such an unstable phenomenon, edge-trig-
gered (falling, rising, and dual) flip-flops are extensively
studied in QCA. There are two well-known schemes found
in QCA to implement edge-triggered flip-flop, the clock
Int. j. inf. tecnol.

Table 2 Comparison of ConFF

Design Area lm2 Cells Clock cycle Configurable DOC
with existing designs
D FF
In Ref. [19] 0.20 104 1.25 No –
In Ref. [33] 0.08 66 1 No –
In Ref. [14] 0.05 48 1 No –
In Ref. [22] 0.04 36 1.50 No –
T FF
In Ref. [19] 0.20 108 1.25 No –
In Ref. [33] 0.10 90 1 No –
In Ref. [7] 0.08 69 1.25 No –
In Ref. [27] 0.06 68 1.25 No –
In Ref. [4] 0.06 46 1.50 No –
JK FF
In Ref. [32] 0.75 415 2.50 No –
In Ref. [19] 0.12 80 1.25 No –
In Ref. [33] 0.10 68 1 No –
ConFF 0.20 159 2.75 Yes 3
DOC degree of configurability

(a) (b)
Fig. 6 a USE clocking scheme [10], b QCA ConFF-USE layout

Table 3 Comparison of ConFF-USE with the existing design

Design Clocking grid size Output under closed loop Wire crossing required Configurable power Inverted output (Q)

CFF-USE [2] 33 Yes Multi-layer 2 No

ConFF-USE 55 No Co-planner 3 Yes

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pulse generator scheme, and the MUX/latch scheme [37].
However, the clock pulse generator scheme is more pop-
ular than the MUX/latch scheme. The next section will
introduce a universal clock pulse generator that can be
applied to any flip-flop to produce all types of edges like
rising, falling, and dual edges.
5 Universal clock pulse generator (CPG)
This section investigates a universal clock pulse generator
that can produce all types of pulses as and when necessary.
Figure 7a shows the schematic of the proposed pulse
generator. It has two control inputs (C3 and C4 ). Control
inputs and their associated working functions are shown in
Table 4. It is understood that to generate a falling edge,
CPG utilizes previous clock pulses named as CLKold ,
which is compared with the current clock pulse (CLK). The
CLKold is produced by using four consecutive clock zones
(one clock cycle is equal to four clock zones) as shown in
Fig. 7b. The majority voter representation of the falling
edge operation is as follows:
Out1 ¼ MVðMVðCLK; C3 ; 1Þ; CLKold ; 1Þ
The value of (CLK. CLKold ) will produce a resultant
Boolean value of 1 which triggers a pulse in the output if
(a)
(b)
Fig. 7 The proposed universal clock pulse generator (CPG) a major-
ity voter representation, b QCA representation
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Int. j. inf. tecnol.
the control inputs are set to C3 = 1 and C4 = 0 (Table 4). On
the otherhand, the CPG can generate rising edge (CLK
ðCLKold Þ) which results to 1) if C3 = 0 and C4 = 1 and
hence producing a trigger in the final output. The majority
voter representation of the rising edge operation is as
follows:
Out2 ¼ MVðMVðCLK; C4 ; 1Þ; CLKold ; 1Þ ð3Þ
From Fig. 7a, it is clear that Out1 and Out2 is passed
through an OR gate to produce the final output. If both the
control inputs (C3 = 1 and C4 = 1) are set to 1 then the CPG
can produce pulses for both the edges (rising as well as
falling) and hence works as a dual edge-triggered CPG as
shown in Table 4. The majority voter representation of the
dual-edge operation is as follows:
Output ¼ MVðOut1 ; Out2 ; 1Þ ð4Þ
The QCADesigner outcome for the proposed CPG is
shown in Fig. 8, which establishes the correctness of the
proposed clock pulse generator. The duty of the control
inputs (C3 and C4 ) is to activate the CPG to get the nec-
essary output pulse. The function of the control inputs are
ð2Þ as follows:
1. If C3 = 1 and C4 = 0 then the CPG acts as a falling edge
triggered generator (Fig. 8a).
2. If C3 = 0 and C4 = 1 then the CPG acts as a rising edge
triggered generator (Fig. 8b).
3. If C3 = 1 and C4 = 1 then the CPG acts as a dual edge
triggered generator (Fig. 8c).
6 Configurable dual edge triggered flip-flop
Efforts have been made to increase the functionality of
ConFF by trying to incorporate a clock pulse generator
whose effectiveness is determined by implementing all
three types of pulses generated in a single design. The
additional design is incorporated within the proposed
structure to devise a configurable dual edge-triggered flip-
flop. The schematic of the proposed configurable dual
edge-triggered flip-flop (EConFF) is shown in Fig. 9a. The
universal clock pulse generator provides the necessary
clock pulses to ConFF. The QCA representation of a
configurable dual edge-triggered flip flop is shown in
Fig. 9b. The manifold advantage being that nine different
types of flip-flop designs usually done separately can be
incorporated within one. This means the proposed EConFF
can be reconfigured to falling edge D/T/JK FF, rising edge
D/T/JK FF and dual-edge D/T/JK FF using the same circuit
setting its control inputs. EConFF follows the rule of
ConFF, which are explained in Table 1. The required FF is
Int. j. inf. tecnol.

Table 4 Operations of cock pulse generator

C3 C4 CLKold CLK Out1 Out2 Output

Falling edge operation

1 0 0 0 0 0 0
1 0 0 1 0 0 0
1 0 1 0 1 0 1
1 0 1 1 0 0 0
Rising edge operation
0 1 0 0 0 0 0
0 1 0 1 0 1 1 (a)
0 1 1 0 0 0 0
0 1 1 1 0 0 0
Dual edge operation
1 1 0 0 0 0 0
1 1 0 1 0 1 1
1 1 1 0 1 0 1
1 1 1 1 0 0 0

configured using C1 , C2 and the required pulse is provided

by C3 , C4 control inputs. The outcome of JK flip-flop is
shown in Fig. 10 with three different versions.
The performance of the proposed EConFF is shown in
Table 5. The existing dual edge-triggered flip-flops (DET)
are compared with the proposed EConFF. It can be
observed that all the existing designs differ in size, cell
count, and clock cycle count. Therefore, in the actual
implementation, different underlying clocking layout will
be required in fabrication. This disparity behavior of pre-
vious designs can be removed by using configurable
designs such as CFF [2] and EConFF. However, the CFF (b)
[2] design can not configure to JK flip flop and due to
which fails to behave as universal design. On the other Fig. 9 The QCA configurable dual edge triggered flip-flop (EConFF)
a block diagram, b QCA layout
hand, EConFF can be utilized to all three types of flip flop
(JK, T, and D flip flop), hence, established as a one in all
design.

(a) (b) (c)

Fig. 8 The simulation result of universal clock pulse generator a falling edge, b rising edge and c dual edge

123
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(a) (b) (c)

Fig. 10 The simulator outcome for EConFF configured as JK FF a falling edge JK, b rising edge JK and c dual edge JK

Table 5 Performance of
Design Area lm2 Cells Clock cycle Configurable DOC
EConFF
DET D FF [14] 0.14 120 3.25 No –
DET D FF [37] 0.13 93 1.5 No –
DET D FF [39] 0.17 117 3 No –
DET T FF [38] 0.32 184 3 No –
DET JK FF [36] 0.34 197 3.2 No –
CFF [2] 0.09 103 1.50 Yes 6
EConFF 0.38 242 3.75 Yes 9
DET dual edge triggered

7 Realization of counter/shift register and C4 . An additional delay control circuit (DCC) is

In this section, the configurable dual edge triggered flip-
flop (EConFF) is used as a basic element to realize the
proposed counter as well as shift register employing the
same EConFF. The same circuit can behave as a syn-
chronous counter or a serial input parallel output (SIPO)
shift register.
7.1 Two bit counter or shift register
engaged with the main circuit to synchronize the clock.
The function of this DCC circuit can be monitored with the
help of input C5 . The previous clock pulse is propagated to
the output if input C5 is reset else the current clock pules is
forwarded. At the same time this input defines the logic
function in the output. If input C5 is reset then the circuit is
configured as shift register else as a counter. The QCA
realization of the 2-bit counter or shift register is shown in
Fig. 11b.

Two EConFF are used to realize the proposed 2-bit shift
register or counter as shown in Fig. 11a. The same circuit
can behave as a synchronous 2-bit counter or a serial input
parallel output (SIPO) 2-bit shift register as necessary. The
proposed 2-bit counter/shift register has seven control
inputs, two primary inputs (A, B) and two primary outputs
(Q0 and Q1 ). Inputs C1 and C2 are used to control the
EConFF module. The clock pulse generator (CPG) deter-
mines different edges as per requirement by fixing input C3
7.2 Three bit counter or shift register
The multi-functional 3-bit design of the proposed counter
or shift register is shown in Fig. 12. If control inputs C5 =
C6 = 0 then the circuit will act as a shift register else as a
counter. All the other control inputs are used to adjust the
flip flops and also the CPG. Similarly, by cascading ‘n’
number of EConFF modules, the n-bit counter or shift
register is constructed as shown in Fig. 13.

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Int. j. inf. tecnol.

(a)

(b)
Fig. 11 Two bit counter or shift register a schematic of 2-bit counter/shift register, b QCA representation

123

Fig. 12 Three bit design of counter or shift register
The proposed counter/shift register is compared with
existing counter designs, and it is reported in Table 6.
However, the proposed design is capable of serving counter
as well as shift register as per requirement. Also, it can be
configured to three different pulses (rising, falling and
dual), which is not found any of the previous designs.
QCADesigner (version 2.0.3) [34], a QCA simulation tool,
is employed to find out the effectiveness of proposed QCA
designs using both coherence vector and bistable approxi-
mation simulation engines using all the default parameters.
8 Conclusion
An efficient design of a configurable level triggered flip-
flop (ConFF) is investigated here. It has the power to
generate three logic as per the requirement. The USE clock
implementation of ConFF shows a significant improvement
over its existing counterpart. A configurable dual edge-
triggered flip-flop (EConFF) is also realized with the help
of a universal clock pulse generator (CPG). The CPG
proposed here is highly efficient in producing all types of
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Int. j. inf. tecnol.
pulses using the same circuit. The EConFF can be used in
nine different ways, which is not found on any of the
previous designs. Further, an efficient n-bit counter/shift
register is proposed, which can be configured as an n-bit
counter or n-bit shift register as and when necessary. The
proposed configurable structures are verified with
QCADesigner 2.0.3.
With the advancement of IOT, field programmable gate
arrays (FPGAs) are gaining more importance due to its
flexibility. Flexibility and performance are the two chal-
lenging issues of any digital logic circuit [8]. The inter-
mediate trade-off between flexibility and performance is
the utmost necessity for a digital logic circuit which can be
attained by configurable circuits like FPGA [9]. The core of
FPGAs is configurable logic blocks (CLBs). The primary
components of QCA based CLBs are LUT (look up table)
and D flip-flop. Therefore, to increase the flexibility of
CLB in FPGA, more flexible components need to be built.
In this regard, configurable flip-flops can play an vital role.
Moreover, the need of symmetric design requirements can
also be fulfilled with the help of configurable devices.
Int. j. inf. tecnol.

Fig. 13 The proposed n-bit counter/shift register

Table 6 Performance of
Design Area lm2 Cells Clock cycle Single layer Configurable
counter/shift register
Existing 2-bit counter
In Ref. [36] 0.74 430 4 Yes No
In Ref. [26] 0.26 240 2 No No
In Ref. [5] 0.22 141 2.25 Yes No
Proposed 2-bit counter/shift register 0.67 464 5.75 Yes Yes
Existing 3-bit counter
In Ref. [36] 1.02 677 6 Yes No
In Ref. [26] 0.48 428 2 No No
In Ref. [5] 0.36 328 2.25 Yes No
In Ref. [1] 0.22 196 2 Yes No
Proposed 3-bit counter/shift register 1.18 786 7.75 Yes Yes

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