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Microstepping Driver With Translator: Absolute Maximum Ratings Att +25°C
Microstepping Driver With Translator: Absolute Maximum Ratings Att +25°C
Microstepping Driver With Translator: Absolute Maximum Ratings Att +25°C
Data Sheet
26184.24F
MICROSTEPPING DRIVER WITH TRANSLATOR
The A3967SLB is a complete microstepping motor driver with
built-in translator. It is designed to operate bipolar stepper motors in
full-, half-, quarter-, and eighth-step modes, with output drive capabil-
ity of 30 V and ±750 mA. The A3967SLB includes a fixed off-time
REF 1 PWM 24 PFD
÷8 TIMER current regulator that has the ability to operate in slow, fast, or mixed
RC 2 2 23 RC 1
current-decay modes. This current-decay control scheme results in
SLEEP 3 22 RESET reduced audible motor noise, increased step accuracy, and reduced
OUT2B 4 21 OUT1B power dissipation.
LOAD LOAD
SUPPLY 2
5 VBB2 VBB1 20 SUPPLY 1 The translator is the key to the easy implementation of the
GND 6 19 GND
A3967SLB. By simply inputting one pulse on the STEP input the
GND 18 GND
motor will take one step (full, half, quarter, or eighth depending on two
7
logic inputs). There are no phase-sequence tables, high-frequency
SENSE2 8 17 SENSE1
control lines, or complex interfaces to program. The A3967SLB
OUT2A 9 16 OUT1A
interface is an ideal fit for applications where a complex µP is unavail-
STEP 10 TRANSLATOR 15 ENABLE able or over-burdened.
& CONTROL
LOGIC LOGIC
DIR 11 VCC 14
SUPPLY Internal circuit protection includes thermal shutdown with hyster-
MS1 12 13 MS2 esis, under-voltage lockout (UVLO) and crossover-current protection.
Special power-up sequencing is not required.
Dwg. PP-075-2
ABSOLUTE MAXIMUM RATINGS The A3967SLB is supplied in a 24-pin SOIC with four internally
at TA = +25°C fused pins for enhanced thermal dissipation. The pins are at ground
potential and need no insulation. A lead (Pb) free (100% matte tin
Load Supply Voltage, VBB ............. 30 V leadframe) version is also available.
Output Current, IOUT
Continuous ..................... ±750 mA* FEATURES
Peak ................................. ±850 mA
Logic Supply Voltage, VCC ........... 7.0 V ■ ±750 mA, 30 V Output Rating
Logic Input Voltage Range, VIN ■ Satlington® Sink Drivers
(tw >30 ns) ............. -0.3 V to +7.0 V ■ Automatic Current-Decay Mode Detection/Selection
(tw <30 ns) ................ -1 V to +7.0 V
■ 3.0 V to 5.5 V Logic Supply Voltage Range
Sense Voltage, VSENSE ............... 0.68 V
Reference Voltage, VREF ................ VCC ■ Mixed, Fast, and Slow Current-Decay Modes
Package Power Dissipation, ■ Internal UVLO and Thermal Shutdown Circuitry
PD ................................. See page 8 ■ Crossover-Current Protection
Operating Temperature Range,
TA ........................... -20°C to +85°C
Junction Temperature, TJ ......... +150°C Part Number Pb-free* Package Packing
Storage Temperature Range, A3967SLB-T Yes 24-Lead SOIC 31 per tube
TS ......................... -55°C to +150°C A3967SLBTR-T Yes 24-Lead SOIC 1000 per reel
*
* Output current rating may be limited by Pb-based variants are being phased out of the product line. The variants cited in this
duty cycle, ambient temperature, and heat footnote are in production but have been determined to be LAST TIME BUY. This
sinking. Under any set of conditions, do not classification indicates that sale of this device is currently restricted to existing
exceed the specified current rating or a customer applications. The variants should not be purchased for new design
applications because obsolescence in the near future is probable. Samples are no
junction temperature of 150°C.
longer available. Status change: October 31, 2006. Deadline for receipt fo LAST TIME
BUY orders: April 27, 2007. These variants include: A3967SLB and A3967SLBTR.
3967
MICROSTEPPING DRIVER
WITH TRANSLATOR
LOGIC LOAD
SUPPLY SUPPLY
UVLO
VCC AND
14
FAULT
REF. DETECT
SUPPLY VBB1
20
REF
1 ÷8 DAC SENSE
+ -
RC1 OUT1A
23 PWM LATCH
BLANKING 16
MIXED DECAY
OUT1B
21
3 PWM TIMER
STEP 10
DIR 11 SENSE1
TRANSLATOR
17
CONTROL LOGIC
RESET 22
MS1 12
MS2 13
5
VBB2
SLEEP 3
ENABLE 15
VPF
OUT2A
24 9
PWM TIMER OUT2B
PFD
3 PWM LATCH 4
BLANKING
MIXED DECAY
2
RC2
+ -
SENSE2
DAC 8
6 7 18 19
Dwg. FP-050-3A
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3967
MICROSTEPPPING DRIVER
WITH TRANSLATOR
Functional Description
Device Operation. The A3967 is a complete Microstep Select (MS1 and MS2). Input terminals
microstepping motor driver with built in translator for MS1 and MS2 select the microstepping format per
easy operation with minimal control lines. It is designed table 1. Changes to these inputs do not take effect until
to operate bipolar stepper motors in full-, half-, quarter- the STEP command (see figure).
and eighth-step modes. The current in each of the two
output H-bridges is regulated with fixed off time pulse- Direction Input (DIR). The state of the DIRECTION
width modulated (PWM) control circuitry. The H-bridge input will determine the direction of rotation of the motor.
current at each step is set by the value of an external Internal PWM Current Control. Each H-bridge is
current sense resistor (RS), a reference voltage (VREF), and controlled by a fixed off time PWM current-control circuit
the DAC’s output voltage controlled by the output of the that limits the load current to a desired value (ITRIP).
translator. Initially, a diagonal pair of source and sink outputs are
At power up, or reset, the translator sets the DACs and enabled and current flows through the motor winding and
phase current polarity to initial home state (see figures for RS. When the voltage across the current-sense resistor
home-state conditions), and sets the current regulator for equals the DAC output voltage, the current-sense com-
both phases to mixed-decay mode. When a step command parator resets the PWM latch, which turns off the source
signal occurs on the STEP input the translator automati- driver (slow-decay mode) or the sink and source drivers
cally sequences the DACs to the next level (see table 2 for (fast- or mixed-decay modes).
the current level sequence and current polarity). The The maximum value of current limiting is set by the
microstep resolution is set by inputs MS1 and MS2 as selection of RS and the voltage at the VREF input with a
shown in table 1. If the new DAC output level is lower transconductance function approximated by:
than the previous level the decay mode for that H-bridge
will be set by the PFD input (fast, slow or mixed decay). ITRIPmax = VREF/8RS
If the new DAC level is higher or equal to the previous The DAC output reduces the VREF output to the
level then the decay mode for that H-bridge will be slow current-sense comparator in precise steps (see table 2 for
decay. This automatic current-decay selection will % ITRIPmax at each step).
improve microstepping performance by reducing the
distortion of the current waveform due to the motor ITRIP = (% ITRIPmax/100) x ITRIPmax
BEMF.
Fixed Off-Time. The internal PWM current-control
Reset Input (RESET). The RESET input (active low) circuitry uses a one shot to control the time the driver(s)
sets the translator to a predefined home state (see figures remain(s) off. The one shot off-time, toff, is determined by
for home state conditions) and turns off all of the outputs. the selection of an external resistor (RT) and capacitor
STEP inputs are ignored until the RESET input goes high. (CT) connected from the RC timing terminal to ground.
The off time, over a range of values of CT = 470 pF to
Step Input (STEP). A low-to-high transition on the 1500 pF and RT = 12 kΩ to 100 kΩ is approximated by:
STEP input sequences the translator and advances the
motor one increment. The translator controls the input to toff = RTCT
the DACs and the direction of current flow in each wind-
ing. The size of the increment is determined by the state
of inputs MS1 and MS2 (see table 1).
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3967
MICROSTEPPING DRIVER
WITH TRANSLATOR
RC Blanking. In addition to the fixed off time of the Percent Fast Decay Input (PFD). When a STEP
PWM control circuit, the CT component sets the compara- input signal commands a lower output current from the
tor blanking time. This function blanks the output of the previous step, it switches the output current decay to either
current-sense comparator when the outputs are switched slow-, fast-, or mixed-decay depending on the voltage
by the internal current-control circuitry. The comparator level at the PFD input. If the voltage at the PFD input is
output is blanked to prevent false over-current detection greater than 0.6VCC then slow-decay mode is selected. If
due to reverse recovery currents of the clamp diodes, and/ the voltage on the PFD input is less than 0.21VCC then
or switching transients related to the capacitance of the fast-decay mode is selected. Mixed decay is between
load. The blank time tBLANK can be approximated by: these two levels.
1.5
1.0
Timing Requirements
(TA = +25°C, VCC = 5 V, Logic Levels are VCC and Ground)
STEP 50%
C D
A B
MS1/MS2/
DIR/RESET
SLEEP
Dwg. WP-042
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3967
MICROSTEPPING DRIVER
WITH TRANSLATOR
Applications Information
Layout. The printed wiring board should use a heavy Current Sensing. To minimize inaccuracies caused by
ground plane. ground-trace IR drops in sensing the output current level,
the current-sense resistor (RS) should have an independent
For optimum electrical and thermal performance, the
ground return to the star ground of the device. This path
driver should be soldered directly onto the board.
should be as short as possible. For low-value sense
The load supply terminal, VBB, should be decoupled resistors the IR drops in the printed wiring board sense
with an electrolytic capacitor (>47 µF is recommended) resistor’s traces can be significant and should be taken
placed as close to the device as possible. into account. The use of sockets should be avoided as
they can introduce variation in RS due to their contact
To avoid problems due to capacitive coupling of the resistance.
high dv/dt switching transients, route the bridge-output
traces away from the sensitive logic-input traces. Always Allegro MicroSystems recommends a value of RS
drive the logic inputs with a low source impedance to given by
increase noise immunity.
RS = 0.5/ITRIPmax
Grounding. A star ground system located close to the
Thermal protection. Circuitry turns off all drivers
driver is recommended.
when the junction temperature reaches 165°C, typically.
The 24-lead SOIC has the analog ground and the It is intended only to protect the device from failures due
power ground internally bonded to the power tabs of the to excessive junction temperatures and should not imply
package (leads 6, 7, 18, and 19). that output short circuits are permitted. Thermal shut-
down has a hysteresis of approximately 15°C.
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3967
MICROSTEPPING DRIVER
WITH TRANSLATOR
STEP
INPUT
SLOW
DECAY
70.7%
PHASE 1
CURRENT
–70.7%
SLOW
DECAY
70.7%
PHASE 2
CURRENT
–70.7%
Dwg. WK-004-19
STEP
INPUT
DECAY
DECAY
DECAY
DECAY
DECAY
DECAY
DECAY
DECAY
MIXED
MIXED
MIXED
MIXED
SLOW
SLOW
SLOW
SLOW
100%
70.7%
PHASE 1
CURRENT
–70.7%
–100%
DECAY
DECAY
DECAY
DECAY
DECAY
DECAY
DECAY
DECAY
MIXED
SLOW
MIXED
SLOW
MIXED
MIXED
SLOW
SLOW
100%
70.7%
PHASE 2
CURRENT
–70.7%
–100%
Dwg. WK-004-18
www.allegromicro.com 11
3967
MICROSTEPPING DRIVER
WITH TRANSLATOR
STEP
INPUT
8 Microstep/Step Operation
MS1 = MS2 = H, DIR = H
STEP
INPUT
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3967
MICROSTEPPING DRIVER
WITH TRANSLATOR
Terminal List
Terminal Terminal
Name Terminal Description Number
REF Gm reference input 1
RC2 Analog input for fixed offtime – bridge 2 2
SLEEP Logic input 3
OUT2B H bridge 2 output B 4
LOAD SUPPLY2 VBB2, the load supply for bridge 2 5
GND Analog and power ground 6, 7
SENSE2 Sense resistor for bridge 2 8
OUT2A H bridge 2 output A 9
STEP Logic input 10
DIR Logic Input 11
MS1 Logic input 12
MS2 Logic input 13
LOGIC SUPPLY VCC, the logic supply voltage 14
ENABLE Logic input 15
OUT1A H bridge 1 output A 16
SENSE1 Sense resistor for bridge 1 17
GND Analog and power ground 18, 19
LOAD SUPPLY1 VBB1, the load supply for bridge 1 20
OUT1B H bridge 1 output B 21
RESET Logic input 22
RC1 Analog Input for fixed offtime – bridge 1 23
PFD Mixed decay setting 24
24 13
0.0125
0.0091
0.2992 0.419
0.2914 0.394
0.050
0.016
0.020 1 2 3 0.050
Dimensions in Inches
0.013 0.6141 0° TO 8°
0.5985
BSC (for reference only)
NOTE 1
NOTE 3
0.0926
0.1043
24
0.32
0.23
7.60 10.65
7.40 10.00
1.27
0.40
2.65
2.35
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
3. Webbed lead frame. Leads 6, 7, 18, and 19 are internally one piece.
4. Supplied in standard sticks/tubes of 31 devices or add “TR” to part number for tape and reel.
www.allegromicro.com 15
3967
MICROSTEPPING DRIVER
WITH TRANSLATOR