1 P E C S

USN

PESIT Bangalore South Campus

Hosur Road, 1 km before Electronic City, Bengaluru -560100
Department of Computer Science and Engineering

INTERNAL ASSESSMENT TEST II

Date : 03/10/2018 Max Marks: 40
Subject & Code: Advanced Computer Architecture(15CS72) Section: VII A,B,C
Name of Faculty: Dr.Sudarshan/Prajwala Time: 8:30-10:00 AM
Note: Answer FIVE full questions. Select one question from each part.
Part I

Q1 Explain the following network routing properties 8

a. Node degree and network diameter b. bisection width
c. perfect shuffle and exchange d. broadcast and multicast
OR
Q2 Design and draw omega network by using 2 X 2 switch elements for following 8
processor
Input: 0 1 2 3 4 5 6 7
Output:1 0 3 2 5 4 7 6
Part II
Q3 Explain Amdhal’s law for fixed workload in detail. 8
OR
Q4 a. Compare the characteristics of RISC and CISC processor 8
b. Explain data path architecture and control unit of scalar processor
Part III
Q5 a. List the register based vector operations 8
b. List and explain any four characteristics of symbolic processor
OR
Q6 Consider the 3 level memory hierarchy designs with following specification. 8
calculate T2 and S3
Memory level Access time Capacity Cost/Kbyte
Cache T1=10ns S1=1MB C1=Rs.0.12
Main memory T2 S2=128MB C2=Rs. 0.02
Disk array T3=4ms S3 C3=Rs. 0.00002
Effective access time T=850ns,cache hit ratio H1=0.98 and H2=0.99.
Total cost is Rs. 1500/=
Part IV
Q7 a. Explain the address translation mechanism using TLB with a neat 8
diagram.
b. What is LRU page replacement policy?
OR
Q8 Calculate hit ratio for the following page trace using LRU and OPT algorithm 8
01242372131

BE(CSE), VII Semester

 Part V
Q9 Explain direct mapping of cache memory in detail with a neat block diagram. 8
Consider the cache memory of size 64KB and main memory of size 32MB and
value of n=220 blocks for word addressable memory. How many blocks are
mapped to single block frame in direct mapping?
OR
Q 10 Explain centralized and distributed bus arbitration schemes 8

Scheme and solution

Part1

a) node degree-number edges incident on node(1M)

Network diameter-maximum shortest path(hops) between any 2 nodes(1M)

b) bisection width-when network is cut into 2 equal halves minimum number of edges along the
cut-channel bisection width(1M)

B=bW(1M)

c) perfect shuffle and exchange -permutation function.n=2k objects, number x=(xk-1,…..x1,x0).

Maps x to y is obtained by shifting 1 bit left and wrap around most significant bit.(1M)

000 -000

001-010

010-100

011-110

100-001

101-011

110-101

111-111 (1M)

d) broadcast-one-to all mapping of processing elements(1M)

multicast- one-to many mapping elements.(1M)

2) number of switching elements=n log2n=12(1M)

Number of stages=n/2=4 (n=8)(1M)

BE(CSE), VII Semester

Arrangements=4 X 3(1M)

Omega network= connect straight for start and end

Remaining use perfect shuffuling.

Diagram(5M)- Straight connections for stage 1 and 2 (all elements)

Crossover for all elements in stage 3

3) amdhal law for fixed workload-

As number of processors increase, the fixed load is distributed to more processors(1M)

Minimal turnaround time is primary goal

Case 1:2M

Case 2:2M

Graph-3M

BE(CSE), VII Semester

4)

a)

CISC RISC
Large set of instructions Small set of instructions
Addressing modes-12-24 Addressing modes-3-5
8-24 GPR(less),Unified cache 32-192 GPR(more), separate cache for
instruction and data
CPI-more-2-15 CPI-less<1.5
CPU control-microcoded CPU control-hardwired
(4M)

4b)diagram-2M

Explaination-2M

 bus-data,address and control bus

 PC,IR
 PSW
 ALU
 Control unit- microcoded or hardwired.

5a)any 4 operations(4M)

5b)

BE(CSE), VII Semester

Any 4-1M each..

6)

C=c1s1+c2s2+c3s3

S3=5.9 X 1010

T=h1t1+(1-h1)h2t2+(1-h1)(1-h2)h3t3

T2=2.030 X 10-6

(4M each calculation.)

7)

a. address translation using TLB(6M)

(3M)

High speed lookup table which stores most recently referenced pages(1M)

If TLB hit-page found hence physical address

Else TLB miss-page table-not found-page fault(2M)

BE(CSE), VII Semester

b. LRU page replacement policy-replace page which has not been used for longest period of
time.

Or

Replace page with largest backward distance(2M)

8)for 3 frames

Hit ratio- LRU 3/11(4M)

Hit ratio-OPT-4/11(4M)

Valid for 4 frames as well

9)

Direct mapping (6M)

3M diagram

3M-explaination

• Direct mapping- unique block frame is given in cache for each block in main memory.

• Block_num MODULO num_of_blocks_in cache

BE(CSE), VII Semester

Problem-2M

512 blocks are possible.

N=220

S=20

64 bytes, word addressable => m=211

r=11 bits

2s-r=512 blocks

10)centralized arbitration scheme (4M)

2M-explaination

Bus request

Bus busy

Bus grant signal

2M-diagram

BE(CSE), VII Semester

Distributed arbitration scheme -4M

2M-diagran

2M-explaintion

– Unique arbitration number

– Largest AN-master gets bus grant

– SBRG-Shared bus request/grant line

BE(CSE), VII Semester