Government Engineering College Thrissur

07EC6206: Real-Time Digital Signal Processing

MTech II Semester: Electronics and Communication Engineering
Second Series Examination September 2021
Time: 1 hour Max.Marks=30
Answer all questions
Q.no Question Mark CO

1 Explain FPGA and elaborate on the typical architecture of FPGA. 6 CO5

2 Draw the state diagram of a mealy machine designed for detecting 6 CO5
the non-overlapping sequence ‘101’ and write the corresponding
VHDL code.

3 Differentiate between different delay models in VHDL.Draw proper 5 CO5

timing diagrams.

4 Give the general code structure of the VHDL with an example. 4 CO4

5 Explain the types of VHDL descriptions.Write the VHDL code for 5 CO5
4:1 Multiplexer.

6 Write the VHDL code for the given digital circuit using any 4 CO4
preferred modelling style.