Phase-Locked Loops

David Johns, Ken Martin

University of Toronto

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© D. Johns, K. Martin, 1997

Common PLL Applications

• Clock multiplier
- input is a fixed frequency clock
- output is a higher frequency clock signal that is a
multiple of input clock frequency
• Frequency synthesizer
- input is a fixed frequency clock
- output is a clock signal with arbitrary frequency
• Clock and data recovery
- input is a data signal (from a serial link)
- output is digital data as well as clock signal
- phase detector is different than other applications
• FM demodulation
- input is a radio signal
- output is demodulated signal

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 PLL Basic Architecture
Low-pass
filter Gain
Vpd V
Vin lp
Phase H (s) Output
lp K lp
detector voltage

Average voltage proportional to phase difference

Vcntl
VCO
Vosc
(voltage controlled oscillator)

• In general, output may be V cntl or V osc

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PLL Basics
• Feedback causes V in to be phase locked to V osc
• We start with a simple phase detector of ...
V pd = K M V in V osc (1)
K M is a multiplication constant
• Also assume filter is ...
1 + sτ z
H lp ( s ) = ----------------- (2)
1 + sτ p

which is a lead-lag filter. Usually τ z << τ p

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© D. Johns, K. Martin, 1997

 Example Waveforms
1

0.8

0.6 Vin Vosc

0.4

0.2 Vpd
0

−0.2

−0.4

−0.6

−0.8

−1
0 2 4 6 8 10 12 14 16 18 20

V in = E in sin ( ωt ) (3)
V osc = E osc sin ( ωt – φ d + 90° ) = E osc cos ( ωt – φ d ) (4)
• Above shows an example of φ d ≈ 90 (slightly less)

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PLL Basics
• Can show
E in E osc
V pd = K M ------------------- [ sin ( φ d ) + sin ( 2ωt – φ d ) ] (5)
2
• The lowpass filter removes second term and for
small φ d ...
E in E osc
V cntl ≅ K lp K M ------------------- φ d = K lp K pd φ d (6)
2
where we define
E in E osc
K pd = K M ------------------- (7)
2

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 PLL Basics
• Oscillator frequency given by
ω osc = K osc V cntl + ω fr (8)
ω fr is the free running freq of oscillator
K osc is the VCO gain constant
• Feedback forces ω osc to equal ω in
• However, if ω in does not equal ω fr , and loop filter
does NOT have infinite gain at dc, then phase
difference when in lock given by:
V cntl ω in – ω fr
φ d = -----------------
- = ------------------------------ (9)
K lp K pd K lp K pd K
osc

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© D. Johns, K. Martin, 1997

PLL Linear Model

K
pd
φ in ( s ) K H (s) V
cntl
lp lp

K osc
φ osc ( s ) 1⁄s

V cntl ( s ) = K pd K lp H lp( s ) [ φ in( s ) – φ osc( s ) ] (10)

K osc V cntl ( s )
φ osc ( s ) = ------------------------------ (11)
s

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 PLL Equations
• Combining above 2 equations ...
V cntl ( s ) sK pd K lp H lp(s)
------------------- = ------------------------------------------------------ (12)
φ in ( s ) s + K pd K lp K osc H lp(s)

• This is a highpass response from input phase to

control voltage
• Can also be written as
φ osc ( s ) K pd K lp K osc H lp(s)
----------------- = ----------------------------------------------------- (13)
φ in ( s ) s + K pd K lp K osc H lp(s)

• This is a lowpass response from input phase to

output phase

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© D. Johns, K. Martin, 1997

Charge Pump PLL

Ich
Pu
Vin Sequential S1
phase V lp
Vosc detector
Pd
S2 C1
Ich
(de-glitching cap)
R C2

Charge-pump phase comparator

Low-pass filter

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© D. Johns, K. Martin, 1997

 Sequential Phase Detector
Vin

Vosc
∆φ
in

Pu

2π

Pd
Time

• If V in leads V osc , P u (pulse up) goes high for lead time

• If V osc leads V in , P d (pulse down) goes high for lead
time.

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Charge Pump PLL Equations

• Average current flowing into lowpass filter is ...
∆φ in
I avg = ----------- I ch (14)
2π
• Lowpass filter is (ignoring C 2 )...
V lp ( s ) 1 1 + sRC 1
H lp ( s ) = ----------------- = R + --------- = ---------------------- (15)
I avg ( s ) sC 1 sC 1

• which results in
φ osc ( s ) ( 1 + sRC 1 )
----------------- = -------------------------------------------------- (16)
φ in ( s ) s 2 C1
1 + sRC 1 + ---------------------
K pd K osc

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© D. Johns, K. Martin, 1997

 Charge Pump PLL Equations
• The phase transfer curve is second-order (ignores
de-glitching cap C 2 ) so ω 0 and Q can be found as

1 I ch K osc
ω 0 = -------- = ------------------ (17)
τ pll 2πC 1
1 1 2π
Q = ----------------- = --- -------------------------- (18)
RC 1 ω 0 R C 1 I ch K osc

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Charge Pump Example

• Let K osc = 2π × 50 Mrad ⁄ V and I ch = 10 µA .

• ω fr = 2π × 50 Mrad ⁄ s . Desired loop time constant of

100 cycles, or 2 µs . Find loop filter components.
SOLUTION
1
ω 0 = ----------- = 500 krad ⁄ s (19)
2 µs
1 I ch
C 1 = ------ ------K osc = 2 nF (20)
ω 0 2π
2

• Let C 2 = C 1 ⁄ 10 = 2.5 pF and Q = 0.4

1 2π
R = ---- -------------------------- = 31.4 kΩ (21)
Q C 1 I ch K osc

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 Phase Frequency Detector
Pu Pd

FF1 FF2

Reset
Vin Vosc
Set1 Set2
Pu-dsbl Pd-dsbl

FF3 FF4

Set3 Set4

• Can be used for sequential phase detector but also

works when large frequency differences between osc
freq and input freq

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© D. Johns, K. Martin, 1997

Phase Frequency Detector

Vin

Vosc

Pu

Pd

Pu-dsbl

Pd-dsbl

• Above example is for osc freq much lower than input

freq
• Note that P u is high much longer than P d

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 Oscillators
Oscillators

Tuned oscillators Nonlinear oscillators

RC SC LC Crystal Relaxation Ring

osc. osc. osc. osc. osc. osc.

• Two main classes of oscillators

• Most common are LC osc and Ring osc (Crystal osc
is good but difficult to tune away from center freq)

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Ring Oscillators

• • Vout
• •

Vout (quadrature)

1 1
f osc = --- = --------------- (22)
T 2nτ inv

where τ inv is delay of each inverter

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 Fully Differential Delay Stage

IB IB
Vcntl
Q3 Q4
Vbiasl
+
Vout– Vout
+
Vin Q1 Q2 Vin–

2IB
Vcntl

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V2I Conversion
I I
Q9

Q8 • Q5 Q6

Vbias
Q3 Q4
Vcntl + Q7
To other
oscillators
V cntl
I = -----------
-
R Q1 Q2

R
2I

First inverter of
Control circuitry ring oscillator

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 Alternative Biasing

Ib Ib
Vcntl
Q2
Q3 Vref Q1 From other
Q4 stages

To other
R4 stages
R3 R1 R2
Vref

Bias stage Delay stage

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Computer Simulation of PLLs

• Simulation times can be very long due to large
variations in time-constants
• Make use of bilinear transform to simulate analog
signals in discrete timesteps.
• Loop Filter example
• Impedance looking into loop filter is ... ( G = 1 ⁄ R )
1 1
Z lp ( s ) = --------- + -------------------- (23)
sC 1 sC 2 + G

• So voltage to charge relationship is ...

V lp ( s ) G + s ( C1 + C2 )
---------------- = -------------------------------------- (24)
Q lp ( s ) GC 1 + sC 1 C 2

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© D. Johns, K. Martin, 1997

 Discrete-time loop filter
• Use bilinear transform
2 1 – z–1
s ← --- ----------------- (25)
T 1 + z–1
• giving
V lp ( z ) 2 ( 1 – z – 1 ) ( C 1 + C 2 ) + GT ( 1 + z – 1 )
M ( z ) = --------------- = -------------------------------------------------------------------------------------- (26)
Q lp ( z ) 2C 1 C 2 ( 1 – z – 1 ) + C 1 GT ( 1 + z – 1 )

which can be written as

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© D. Johns, K. Martin, 1997

V lp ( z ) m1 + m2 z –1
P ( z ) = ------------------- = -----------------------------------------------------------------
∆Q lp ( z ) 1 + z –1 ( k – 2 ) + z –2 ( 1 – k )
(27)
1  m1 + m2 z –1 
=  ----------------  ---------------------------------
 1 – z – 1  1 – z – 1 + kz – 1

where
2GC 1 T
k = ------------------ (28)
D
2 ( C 1 + C 2 ) + GT
m 1 = ------------------------------------------ (29)
D
– 2 ( C 1 + C 2 ) + GT
m 2 = ---------------------------------------------- (30)
D
D = 2C 1 C 2 + GC 1 T (31)

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 Discrete-time Loop Filter
m1
X2(z)

X1(z) m2
∆Q(z) z–1 Vlp(z)

z–1 –k

• Can use Matlab, Simulink, C, etc to simulate

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© D. Johns, K. Martin, 1997

A Fractional-N Frequency Synthesizer

• Use oversampling within a PLL
f xt Nf xt
----- ----------
f xt M PM
crystal phase loop
osc ÷M detect filter VCO ÷P

÷N

N = { k-1, k, k+1 }
A digital controlled oscillator

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© D. Johns, K. Martin, 1997