IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 66, NO.
8, AUGUST 2019
Efficient Temperature Sensor Based on SOI
Gate-All-Around Electrostatically Formed
Nanowire Transistor
K. Shimanovich , Z. Mutsafi, M. Shach-Caplan, E. Pikhay, Y. Roizin, and Y. Rosenwaks
Abstract — Electrostatically formed nanowire (EFN) tran-
sistor is a majority carrier silicon-on-insulator (SOI) device,
operated in the depletion mode, with the conducting
channel size and position modulated by surrounding gates.
When operated in the subthreshold regime, the EFN tran-
sistor is an efficient temperature sensor. We present a
novel EFN transistor design with a top gate, named gate-
all-around EFN (GAA EFN), allowing increased temperature
sensitivity. The new design enables the formation of the EFN
conductive channel in the volume of the SOI device layer,
far from the top and bottom silicon/oxide interfaces, thus
reducing the noise level and increasing the temperature
sensitivity to 13.3%/K.
Index Terms — CMOS temperature sensor, electrostati-
cally formed nanowire (EFN), low-frequency noise, multi-
ple gates field-effect transistor, silicon-on-insulator (SOI)
transistors.
I. I NTRODUCTION
E LECTROSTATICALLY formed nanowire (EFN) based
transistors formed on silicon-on-insulator (SOI) have
been recently suggested as effective temperature sensors with
a maximum sensitivity of 7.7%/K, and 0.2% tolerance in
the subthreshold regime [1]. The channels of these devices
were located at the top surface of SOI device layers and
their temperature sensitivity was found to depend on the
channel size and position. For surface channel transistors
like SOI MOSFETs, the noise level has been reported to
be significantly larger compared to buried-channel transistors
like four-gate field-effect transistors (G4 -FETs) [2]. This is
due to the Si/SiO2 interface traps [3], [4], leading to a large
1/ f noise current component. In order to reduce the noise
levels, several transistor designs were proposed, in which the
channel has been buried either by top gate bias or prop-
erly designed doping depth profile [5], [6]. Transistors with
Manuscript received March 13, 2019; revised May 3, 2019 and
May 20, 2019; accepted May 24, 2019. Date of publication June 12,
2019; date of current version July 23, 2019. The review of this paper was
arranged by Editor C. Yang. (Corresponding author: K. Shimanovich.)
K. Shimanovich, Z. Mutsafi, and Y. Rosenwaks are with the Department
of Physical Electronics, School of Electrical Engineering, Faculty of
Engineering, Tel Aviv University, Tel Aviv 69978, Israel (e-mail: klimont1@
gmail.com; yossir@tauex.tau.ac.il).
M. Shach-Caplan, E. Pikhay, and Y. Roizin are with the Research
and Development Department, TowerJazz Semiconductor Ltd., Migdal
HaEmeq 23109, Israel.
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2019.2919389
0018-9383 © 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
3549
buried channels also feature higher temperature sensitivity
due to the improved subthreshold swing, high transcon-
ductance, high transconductance-to-current ratio, and lower
noises [2], [7], [8]. For instance, in a G4 -FET operating in
the depletion all around (DAA) mode, the noise power spectral
density (PSD) was decreased by one–two orders of magnitude,
as the conducting channel was moved away from the top
surface. The normalized quasi variance was lower for strong
inversion than for depletion at the front interface of the device
because the minority carriers screened the front interface and
minimized the exchange between the channel majority carriers
and the oxide traps.
We present here a novel temperature sensor design where
the EFN transistor includes a top gate. The design of the SOI
GAA EFN transistor is very similar to the G4 -FET but differs
in reduced fabrication steps, and use of two photolithography
masks for drain–source, and for junction gates, respectively.
By biasing the top gate, the position of conducting channel
is repositioned from the top to the middle of the SOI
device layer resulting in increased temperature sensitivity and
smaller noise levels. We analyze the dc performance and low-
frequency noise characteristics of the modified transistor with
respect to the channel size and its vertical position.
II. G ATE -A LL -A ROUND EFN T EMPERATURE S ENSOR
A. Device Structure
The GAA EFN temperature sensor was designed in 3-D
TCAD tool (S-process, Synopsys) environment and fabricated
in Tower-Jazz 0.18-μm production SOI CMOS technology.
Fig. 1(a) shows the schematic device structure, which com-
prises a 145-nm silicon device layer on 1-μm buried oxide
(BOX). The n-type device layer was doped with Arsenic
(7 × 1019 cm−3 ) to fabricate the N+ source/drain regions and
Boron (2 × 1020 cm−3 ) to form two lateral p+ -n− junction
gates. Following the drive-in, the N+ and P+ diffusions
penetrated to the BOX interface. The channel region (n-type
device layer) is L = 1 − μm long and W = 0.7 − μm
wide and has vertical gradient n-type doping, ranging from
4.8 × 1017 cm−3 to 1.7 × 1017 cm−3 [1]. The p-type silicon
bulk of the SOI wafer is used as the back gate. A 6-nm SiO2
was thermally grown on the top of the channel region. The
top gate comprised 10-nm Ti and 150-nm Au films deposited
by E-beam evaporator onto the SiO2 dielectric in the Tel Aviv
University microelectronic facility.
3550
Fig. 1. (a) 3-D schematic illustration of the GAA EFN temperature
sensor. Cross section views of the simulated device with electron channel
formed: (b) At the top and (c) at the center of 145-nm n-type silicon layer.
Red is the EFN, and dark red lines are the metallurgical junction between
p- and n-doped device regions. VFB1 and VFB2 designate the flat-band
voltages associated with front and back gates, respectively.
B. Device Operation
In the EFN transistor, the initial channel size and position
are governed by the doping profile of n-type silicon region,
where the electrons channel in the shape of a nanowire is
formed at the top surface of the SOI film device layer. In the
GAA EFN configuration, the size and location of the EFN
are further controlled by the voltage applied to the side gates,
back gate, and top gate; this enables electrostatic tuning of
the channel dimension from full width and thickness of the
n-type device layer to several nanometers (∼6 nm). Fig. 1(b)
shows the n-type channel, i.e., EFN, formed near the front
surface; the channel is pinched by reverse biased junction
side gates, or vertically extended by applying positive bias
to the back gate at fixed biases of junction side gates and top
gate. The potentials at vertical gates influence the threshold
voltage of the junction side gates. The requirement for channel
formation at the top SOI surface is that the top gate is biased
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 66, NO. 8, AUGUST 2019
in excess of the flat band voltage of the front SOI surface
(VTG > VFB1 ), while the back gate biased below the flat band
voltage of the back SOI surface (VBG < VFB2 ).
For positioning the EFN in the middle of the SOI device
layer as shown in Fig. 1(c), negative voltage biases are applied
to the top gate [VTG < VTH(JG)] and back gate VBG < VFB2 ,
while junction gates are reverse biased (VJG ≤ 0). This
specific mode of device operation is known as depletion-all-
around (DAA) [2], when the top and bottom interfaces are
both depleted or depleted at the bottom and inverted at the
top interfaces, respectively.
The EFN channel can also be located at the bottom surface
of the SOI film by increasing the positive bias applied to the
back gate above the flat band voltage of the bottom surface
(VBG > VFB2 ) and applying negative biases to the top gate
below the threshold voltage of the junction side gates [VTG <
VTH(JG)]. This mode of operation is less favorable due to the
increase of the leakage currents through the side gates and
back gate and requires unique doping profile of the n-channel
area. Therefore, we focus our measurements at the top and
middle channel locations.
C. GAA EFN Transfer Characteristics
The drain–source current IDS , transconductance gmJG =
∂ I DS /∂ V JG , and subthreshold swing SSJG = ∂ V JG /∂log(I DS )
characteristics of a GAA EFN transistor operating in the DAA
mode at drain–source voltage VDS = 0.1 V are shown in
Fig. 2. The measurements are performed at room temperature
up to 363 K. In order to eliminate the current component from
lateral p+ -n junctions, the current was measured from the drain
terminal. At room temperature, the IDS values are below the
detection limit of measuring setup, therefore, the analysis is
performed at 305 K. The practical temperature sensor is made
of an array of the GAA EFN transistors, which increases the
IDS level and allows signal detection at low temperatures.
In Fig. 2(a) and (b), the bottom SOI region is driven to
depletion (VBG = −2.5 V), the lateral p+ -n junctions are under
reverse bias (VJG = −2.5 V), and the front surface is driven to
depletion and then to inversion by varying VTG from 50 mV
to −1.8 V. A depletion region is formed near the top surface;
and as it increases, it changes the EFN vertical position, its
size, and IDS . The gradual decrease in the EFN cross section
area in the DAA regime −1.8 V < VTG < 0 V, VBG =
−2.5 V results in a gradual increase in the threshold voltage
of junction side gates [VTH (JG)] [see Fig. 2(c)]. The VTH (JG)
depends linearly on VTG ’s and temperature. The VTH (JG)
decrease with VTG is −1.17 V/V, while with temperature
sensitivity is −2.1 mV/K. Therefore, VTH (JG) mainly depends
on VTG . In order to keep the GAA transistor to operate in the
subthreshold regime, VJG < VTH (JG), which ranges from
−0.9 to −2.5 V, for −1.8 V < VTG < −0.6 V. Similar
dependence of VTH (JG) with VTG ’s is observed for various
temperatures. In Fig. 2(d), the transconductance gmJG of the
buried EFN at VJG = 0 V is larger when the top SOI
surface is inverted at VTG = −1.8 V. Similarly, Fig. 2(e)
shows improvement in the subthreshold swing SSJG when the
bottom region is driven to strong depletion at VBG = −5.5 V.
SHIMANOVICH et al.: EFFICIENT TEMPERATURE SENSOR BASED ON SOI GAA EFN TRANSISTOR
Fig. 2. (a) IDS –VJG characteristics of the GAA EFN transistor in the DAA
regime measured at VDS = 0.1 V, VBG = −2.5 V, T = 305 K, and various
VTG ’s. Inset is IDS in logarithmic scale, with the junction side gates sub-
threshold swing (SSJG ) values presented. (b) IDS –VTG characteristics
measured for various VJG ’s. (c) Junction side gate threshold voltage VTH
(JG) behavior at various VTG ’s and temperatures. (d) Transconductance
gmJG as a function of VJG ’s in the DAA regime for: 1) back depleted and
front inverted surfaces of the SOI (VBG = −2.5 V; VTG = −1.8 V) and
2) both depleted surfaces (VBG = −2.5 V; VTG = −1 V or VTG =
−0.6 V). (e) SSJG for VBG ’s from (left) weak to (right) strong depletion
of back SOI surface, where VTG = −0.6 V—weak depletion, VTG = −1
V—strong depletion, and VTG = −1.8 V—inversion of the front surface.
The best SSJG is obtained for VBG = −5.5 V and VTG =
−1.8 V when the back and front surfaces are in strong
depletion and inversion, respectively.
D. GAA EFN Temperature Sensitivity
The temperature coefficient of current (TCC) is used to
quantify the temperature sensitivity of the GAA EFN transistor
at three operation regimes: subthreshold, linear, and saturation;
it is defined as the percentage change of current per degree
TCC = (d IDS /d T )/IDS .
3551
Fig. 3. Top gate EFN transistor sensitivity (TCC) to temperature
evaluated at room temperature to 363 K in three operation modes:
subthreshold, saturation, and linear, where the back surface is depleted
(VBG = −2.5 V) and front surface: in inversion (−1.8 V < VTG < −1.2 V;
DAA regime); in depletion (−1.2 V < VTG < 0.05 V; DAA regime); and
in accumulation VTG > 0.05 V.
Fig. 3 shows the TCC of the GAA EFN transistor where
the channel position depends on the front surface modes:
inversion, depletion, and accumulation, while the bottom sur-
face is in depletion. For front inversion and back depletion of
the SOI surfaces (−1.8 V < VTG < −1.2 V, VBG = −2.5 V),
the EFN is in the bulk of the SOI film and shrinks in size
to several nanometers (in the order of Debye length) by
varying VJG ’s to negative values. The device operation can be
tuned by VJG ’s to the subthreshold. In the subthreshold regime
(VTG = −1.5 V, VBG = −2.5 V) at VJG = −3 V, an increase
in the device temperature exponentially increases the intrinsic
carrier concentration n i that leads to a linear decrease of the
junction gate threshold voltage VTH (JG) and consequently
to an exponential increase in IDS [1]. The relative change in
the EFN cross-sectional area is large compared to the linear
and saturation operation regimes, and the TCC = 13.3%/K
at IDS ≈ 20 pA. To the best of author’s knowledge, this is
the largest TCC reported for CMOS SOI devices, where TCC
usually ranges from 6.8%/K to 7.7%/K at IDS from 0.1 to
20 pA [1], [9]. We attribute this improvement to the presence
of the top gate which as shown in Fig. 2 improves gmJG , and
SSJG due to the combined effect channel location size and
electron concentration. In addition, in the inversion regime,
the carrier exchange between the channel and top oxide surface
traps is minimized [2]. The last is an additional benefit of the
temperature sensor, but not the dominant mechanism, which
improves the TCC.
For the front and back surface depletion (−1.2 V < VTG <
0.05 V, VBG = −2.5 V), the EFN remains in the DAA mode
but the TCC reduces to 10.5%/K in the subthreshold operation.
For front accumulation and back depletion of the SOI
surfaces (VTG > 0.05 V, VBG = −2.5 V), the EFN channel is
adjacent to the front SOI surface. In this regime, the transistor
operates in the linear regime and becomes less sensitive to
VJG ’s variations (the channel area is large [1]). In the linear
regime, VJG > VTH (JG), the mobility temperature dependence
is significant, causing small variations in the channel size [1].
3552
Fig. 4. Simulated GAA EFN transistor current noise PSD for two
channel locations: near the top SOI film surface (VTG = 0.6 V, VBG =
−1 V, VJG = 0 V, and VDS = 0.1 V) and in the volume of the SOI
film in the DAA regime. In DAA, the top SOI film surface is in depletion
(VTG = −0.6 V) or inversion (VTG = −1.2 V). The front SOI surface is
with electron traps, distributed exponentially with maximum concentration
Nt = −4.5 × 1013 cm−2 at energy level E0 = 0.15 eV below the
conduction band.
The top oxide interface traps and mobility temperature
dependence are the major effects that reduce the TCC to
∼0.5%/K in the linear operation regime.
III. L OW-F REQUENCY N OISE S IMULATIONS
Simulations of the current noise PSD for EFN buried in the
thin SOI film or adjacent to the front SOI surface are shown
in Fig. 4. Significant noise reduction by around four orders of
magnitude is obtained when the channel changes its vertical
position from the top to the center of the SOI film, and when
the front surface becomes inverted. It confirms the TCC values
at various VTG ’s shown in Fig. 3, where the minority carriers
shield the front interface, minimizing the exchange between
the channel and the top oxide interface traps.
IV. 3-D DC S IMULATIONS
3-D electrostatic simulations (TCAD Sentaurus) of the
GAA EFN transistor are shown in Fig. 5. Fig. 5(a) and (b)
shows 2-D hole density maps of the GAA EFN device
for two VTG ’s 0 and −1.8 V. Fig. 5(c) shows the hole
density profile across the device layer of SOI in depletion
(VTG = 0 and 0.6 V) and inversion (VTG = −1.2 and
−1.8 V) at the front SOI surface. An inversion layer is
formed at the front SOI surface at −1.2 V (weak inversion)
and −1.8 V (strong inversion). The maximum hole density
varies from 1015 to 1019 cm−3 at the top layer surface.
Fig. 5(d) shows the EFN sensitivity to temperature for different
regimes at the front SOI surface (accumulation, depletion,
and inversion) with and without electron traps. The SOI
bottom surface at the BOX side is in depletion in all cases.
In the case of inversion and no interface traps (−1.8 V <
VTG < −1.2 V) at VJG = −0.5 V and VDS = 0.1 V,
the TCC reaches its maximum value of 10.2%/K. In the
presence of shallow interface traps (donors) with a surface
density of 4.5 × 1013 cm−2 , TCC = 8.5%/K. This difference
is attributed to the influence of the traps’ surface charge
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 66, NO. 8, AUGUST 2019
Fig. 5. (a) and (b) 2-D hole density maps of the GAA EFN device without
interface traps at the top Si/SiO2 interface simulated at T = 300 K, VBG =
−2.5 V, VJG = −0.5 V, and VDS = 0.1 V, for depletion (VTG = 0 V) and
inversion (VTG = −1.8 V) of the top Si surface, respectively. (c) Hole
density profile across the Si film at depletion and inversion of the top Si
surface at T = 300 K, VBG = −2.5 V, VJG = −0.5 V, and VDS = 0.1 V.
(d) Simulations of transistor sensitivity (TCC) to temperature with and
without electron interface traps at the top SiO2 /Si surface at different
VJG ’s, VTG ’s at VDS = 0.1 V, and VBG = −2.5 V similar to Fig. 3. The
electron traps distribution is exponential with maximum concentration
Nt = −4.5 × 1013 cm−2 at energy level E0 = 0.15 eV below conduction
band.
on the device electrostatics (EFN size and buried channel
location).
In the case of front depletion of the SOI film (−1.2 V <
VTG < 0 V), the TCC reduces monotonically with the increase
of VTG ’s and the same TCC’s for SOI with and without
interface traps is obtained. This is due to small densities of
holes, whose concentration strongly depends on the charge of
surface traps.
For VTG > 0 V at VJG = −0.5 V, TCC difference
between SOI with traps and SOI without traps is attributed
to the difference in front SOI surface regimes: depletion for
SOI with interface traps, and accumulation for SOI without
traps. At VJG = 0 V and VTG > 0 V, the front surface
is in accumulation and no significant difference in TCC is
observed. The dependence of TCC on temperature connected
with electron surface mobility (dμ/d T ) factor has a minor
effect [1].
SHIMANOVICH et al.: EFFICIENT TEMPERATURE SENSOR BASED ON SOI GAA EFN TRANSISTOR
V. C ONCLUSION
We have presented the operation of a GAA EFN transistor
as an effective temperature sensor. The high TCC = 13.3%/K
at IDS ≈ 20 pA measured for front inversion of the SOI film is
the best value reported for CMOS SOI devices operated in the
subthreshold regime. The low current noise level is associated
with the buried channel and inverted top surface. The 3-D
electrostatic simulations reveal the impact of the interface traps
on the TCC.
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