MOSFET Scaling

Dr. Rajan Pandey

Associate Professor, SENSE
 MOSFET Scaling Dennard Scaling (IBM)

Moore’s Law
(Intel)
Why scaling?

- Faster speed
- Lower power supply
- More devices per unit chip area
- Lower cost

Illustration of a “proper scaling” of Si technology by factor α.

 Number of devices on chip doubled  2018-19, 7nm (FinFET) technology in production.

every 2 years (roughly).  5nm and beyond technology choices –
 This means new technology node Architecture: Nanosheets, Vertical transport FET?
every 2 years. Materials: Si, Ge, SiGe, III-V?

• In order to keep the same electric field pattern as the original transistor in the substrate of the
scaled device, original transistor impurity doping concentration is increased in smaller device.
• Moore’s law is an observation but the semiconductor industry follows Dennard scaling!
 MOSFET Scaling
Technology Scaling
- for Cost, Speed, and Power Consumption

YEAR 1992 1995 1997 1999 2001 2003 2005 2007

Technology 0.5 0.35 0.25 0.18 0.13 90 65 45
Generation mm mm mm mm mm nm nm nm

• New technology node every two years or so.

• Feature sizes are ~70% of the previous node.
• Reduc on of circuit area by 2 ― good for cost and speed.
• After 45LP (bulk) – 32SOI (28LP), 22SOI (20LP), 14SOI (14LP),
10SOI, 7LP, 5LP, 3LP. Here LP means Low Power*.
• End of the road for SOI after 10nm. *IBM specific
terminologies!
• 7nm onwards – bulk FinFET. Other companies
• Beyond 5nm – nanosheet or gate all around FET. may have variations
• Silicon will live till 3nm and perhaps a few nodes more. in size & terminologies!
 International Technology Roadmap for Semiconductors

• Semiconductor researchers around the world have been meeting at-least once a year
or multiple times for the purpose of generating consensus on the transistor and circuit
performance that will be required to fulfill the projected market needs in the future.

• Their annually updated document: International Technology Roadmap for

Semiconductors (ITRS) sets out the goals and points out the challenging problems but
does not provide the solutions. It tells the vendors of manufacturing tools and
materials and the research community the expected roadblocks.

• The list of show stoppers is always long and formidable but innovative engineers and
scientists working together and separately have always risen to the challenge and
done the seemingly impossible.
 International Technology Roadmap for Semiconductors
Year of Shipment 2003 2005 2007 2010 2013 • Intel introduced high-k metal gate
at 45nm.
Technology Node (nm) 90 65 45 32 22
Lg (nm) (HP/LSTP) 37/65 26/45 22/37 16/25 13/20 • IBM introduced high-k and metal
EOTe(nm) (HP/LSTP) 1.9/2.8 1.8/2.5 1.2/1.9 0.9/1.6 0.9/1.4 gate in their 32nm node. EOTe
reduced due to HKMG technology.
VDD (HP/LSTP) 1.2/1.2 1.1/1.1 1.0/1.1 1.0/1.0 0.9/0.9
Ion,HP (μA/μm) 1100 1210 1500 1820 2200 • Intel FinFET in 22nm. Ioff reduced
Ioff,HP (μA/μm) 0.15 0.34 0.61 0.84 0.37 in FinFET.
Ion,LSTP (μA/μm) 440 465 540 540 540
• IBM FinFET in 14nm SOI and bulk.
Ioff,LSTP (μA/μm) 1e-5 1e-5 3e-5 3e-5 2e-5
Strained Silicon High-k/Metal-Gate • 7nm onwards – EUV Lithography.
Wet Lithography
HP: High performance; LSTP: Low stand-by power New Structure

• Vdd is reduced at each node to contain power consumption in spite of rising transistor density and frequency.
• Tox is reduced to raise Ion and retain good transistor behaviors.
EOTe or the electrical equivalent oxide thickness is the total thickness of the gate dielectric, poly-gate depletion
(if any), and the inversion layer expressed in equivalent SiO2 thickness. It is improved (reduced) at the 45 nm node
by a larger factor over the previous node. The enabling innovations are metal gate and high-k dielectric.
 Strained Silicon: example of innovations
Gate The electron and hole mobility can be raised
Mechanical strain Trenches filled with
epitaxial SiGe by carefully designed mechanical strain.

• The strained silicon technology introduced around the 90 nm node.

S D • The strain changes the lattice constant of the silicon crystal and
therefore the E–k relationship through the Schrodinger equation.

N-type Si • The E–k relationship, in turn, determines the effective mass and the
mobility.

• Ge is bigger than Si • For example, the hole surface

 It will expand mobility of a PFET can be raised
the lattice vectors. when the channel is compressively
• C is smaller than strained.
Si  It will
compress the • Similarly a tensile strain raises the
lattice vectors. electron surface mobility of a NFET.