MOSFET: Device Simulation,

and SPICE Models

Dr. Rajan Pandey
Associate Professor, SENSE
 Device and Process Simulation

• Device Simulation
– Commercially available computer simulation tools can solve all the equations
simultaneously with few or no approximations.
– Device simulation provides quick feedback about device design before long
and expensive fabrication.

• Process Simulation
– Inputs to process simulation: lithography mask pattern, implantation dose
and energy, temperatures and times for oxidization and annealing steps, etc.
– The process simulator generates a 2-D or 3-D structures with all the
deposited or grown and etched thin films and doped regions.
– This output may be fed into a device simulator as input together with applied
voltages.
 Example of Process Simulation
• FinFET Process

The small figures only show 1/4 of the

complete FinFET--the quarter farthest from
the viewer.
Manual, Taurus Process, Synoposys Inc.
Example of Device Simulation
Density of Inversion Charge in the Cross-Section of a FinFET Body

C.-H. Lin et al., 2005 SRC TECHCON

Tall FinFET Short FinFET

• The inversion layer has a significant thickness (Tch).

• There are more sub-threshold inversion electrons at the corners.
 MOSFET Compact Modeling for Circuit Simulation
• Circuit designers can simulate the operation of circuits containing up to hundreds of thousands or
even more MOSFETs accurately, efficiently, and robustly.
• Accuracy must be delivered for DC as well as RF operations, analog as well digital circuits, memory
as well as processor ICs.
• In circuit simulations, MOSFETs are modeled with analytical equations. These models are called
compact models to highlight their computational efficiency in contrast with the device simulators.
• It could be said that the compact model (and the layout design rules) is the link between two
halves of the semiconductor industry—technology/manufacturing on the one side and
design/product on the other.
• A compact model must capture all the subtle behaviors of the MOSFET over wide ranges of
voltage, L, W, and temperature and present them to the circuit designers in the form of equations.
• Some circuit-design methodologies, such as analog circuit design, use circuit simulations directly.
Other design methodologies use cell libraries.
• A cell library is a collection of hundreds of small building blocks of circuits that have been carefully
designed and characterized beforehand using circuit simulations.
• A good compact model should provide fast simulation times by using simple model equations.
• In addition to the IV of N-channel and P-channel transistors, the model also includes capacitance
models, gate dielectric leakage current model, and source and drain junction diode model.
• Noise and high-frequency models are usually provided, too.
 SPICE Modeling
- Simulation Program with Integrated Circuit Emphasis
or
Simulation Program for the Integrated Circuit Environment
- Developed by UC Berkeley in the late 1970’s
- SPICE is an electric circuit simulator (R, L, C, V, I,…)
- Its main contribution at the time was the ability to support transistor Models

- Berkeley SPICE is free for Unix/Linux. It is a text based program.

- CAD vendors take the free SPICE engine and add features like graphical user
interface and additional components

- The CAD vendors (Mentor, Synopsis, Cadence,…) then sell it for big money
SPICE Modeling
- How does SPICE work?

- For a given circuit, KCL and KVL equations can be written

- These equations can be solved using Matrix mathematics

- SPICE does the same thing, except on the front-end it is able to take the
entered circuit and create the KCL/KVL equations for us
SPICE Modeling
- The source file for a SPICE simulation is called a DECK

- The DECK can be thought of as a text netlist of the circuit.

- Even when using a graphical entry tool for the schematic, the first thing the tool does
when you click “simulate”, is create a text-based DECK that is plugged into the SPICE engine.

- the first letter of a component instantiation in the DECK tells SPICE what the component is.

- devices are then followed by the net names they connect to followed by their parameters
R1 n1 n2 VALUE=75 * resistor
L1 n2 n3 VALUE=1n * inductor
C1 n3 n4 VALUE=1p * capacitor

V1 n4 n5 DC=1v * DC voltage source

I1 n5 n6 ACmag=1 * AC current source
SPICE Modeling
- SPICE allows the use of MODELS to represent components with complex, non-linear responses
such as Diodes and Transistors

- Models are present in their own file (starting with the .MODEL keyword)

- A component is instantiated in the DECK, but then references the MODEL to describe its behavior

- MOSFETS are denoted with an “M” as their first letter

DECK MODEL
M1 D G S B NMOD (L=1U W=10U) .MODEL NMOD NMOS
+ KP=40
+ VT0=0.55
+ GAMMA=0.34
+ PHI=0.3
+ LAMBDA=0.2
:
MOSFET Terminal Model Parameters : Device Model Model Type
Connections Name Parameters Name (NMOS or PMOS)
 SPICE Modeling
- There are different levels of accuracy and complexity that a model can have.

- We give these different types of models the description of Level (i.e., Level 1 model, Level 2 model..)

- Increasing model accuracy increases simulation time

- Let’s start by looking at the simplest model for a MOSFET, Level 1

- Level 1 uses the basic IV equations

- it also includes:

1) Resistance of Source & Drain

2) Capacitance (bias dependant)

3) Reverse-Bias behavior of Junction Diodes

SPICE Modeling (Level 1)
- parameters can exist in the Model file. However, we can pass in parameters (i.e., override) the
parameters by putting them in the Deck instantiation

- there are different types of parameters for the model

“Design Parameters”

- these parameters are under the designer’s control

- these sometimes have default values, but if we are doing design, this is what we change

Parameter Description
L length of channel (drawn)
W width of channel
AS / AD area of Source/Drain
PS / PD perimeter of Source/Drain
SPICE Modeling (Level 1)

“Electrical Parameters”

- there are 5 parameters that fully characterize the base model

- these will have default values in the model based on the fab process

- we can overwrite these from the DECK if we want to perform sensitivity analysis

Parameter Description
KP k’, transconductance
VTO VT0, zero substrate bias threshold
GAMMA γ, substrate-bias coefficient
PHI |2F|, surface potential
LAMBDA λ, channel length modulation coefficient
SPICE Modeling (Level 1)
“Physical Parameters”

- there are parameters that describe the shape and material properties of the device

Parameter Description
U0 un, electron mobility
TOX tox, oxide thickness
NSUB NA, doping concentration
LD LD, lateral diffusion

- notice that these parameters are redundant with the Electrical parameters since these
quantities are used to calculate k’, VT0, γ, |2F|, and λ

- these allow you to get further into the details of the fabrication to see its effect on performance

- however, the “Electrical Parameters” OVERRIDE the “Physical Parameters”

- this means you wouldn’t supply both if you really want to see the effect of a physical parameters
on the performance of the device. You would need to remove the electrical parameter.
 SPICE Modeling (Level 1)

“Parasitic Parameters”
- these are the capacitances and resistances of the material
Parameter Description

CJ CJ0, zero-bias bulk capacitance per area

CJSW CJ0sw, zero-bias sidewall capacitance per area

- these parameters scale with the size of the device provided by W, L, AS, AD, PS, & PD.
- there are many more parameters we need SPICE to properly predict the behavior of a
transistor.
The LEVEL 1 model equation

• Equations
VT – Equation as derived previously
ID – Equations as derived previously with linear mode equation
times (1+λVDS) for continuity across linear-saturation boundary.
Both use Leff in place of L where: Leff = L – 2 LD
• Key Parameters: What do they represent?
NMOS, PMOS (obvious) – MOSFET channel type
KP – process transconductance k‘
VTO (note O, not 0!) – zero substrate-bias threshold voltage VT0
GAMMA – substrate-bias or body-effect coefficient γ
PHI – twice the Fermi potential 2F
LAMBDA – channel length modulation λ
SPICE Model Level 1 (Continued)
• Additional Parameters: What do they represent?
LD – Lateral diffusion (If not present, may need to find Leff manually!)
TPG – Type of gate material: 0 – A1, +1 – opposite to substrate, -1 – same as
substrate. Default +1. For the typical CMOS process, TPG = 1 for NMOS and –
1 for PMOS
NSUB – substrate impurity concentration NA (NMOS) ND (PMOS)
NSS – Surface state density – Used to define surface component of VT0.
TOX – Oxide thickness tox
U0 (note 0, not O) – Surface mobility µ0
RD, RS – Drain resistance, Source resistance
RSH – Drain and Source sheet resistance (Ω)
• Derived Parameters. Note that if some parameters missing, others, if present, can
be used to derive them. E. g. NSUB to derive PHI, and TOX and U0 to derive KP.
Question: What parameters to derive GAMMA? If the derivable parameters are
present in the model, they will be used; if not, derived if possible from other
parameters (and defaults), else, defined.
Variation of the drain current with model parameter
SPICE Modeling (Level 2)
- Level 2 adds the following behavior to the Level 1 model

1) Variation of the bulk depletion charge dependence on the channel voltage (we assumed it
was constant in Level 1).

2) Variation of electron mobility (un) with the applied E-field

3) Variation of effective Channel Length in Saturation model

4) Carrier Velocity Saturation

5) Subthreshold Conduction

- we also have the ability to indicate which level we want to use. For example, you can have a
Level 2 model, but in the instantiation you say:

this will tell the simulator to ignore all the parameters associated with Level 2 or higher accuracy.

- we can also put the “Level=1” as the first parameters in the model
The LEVEL 2 model equation
SPICE Models Level 2
• Level 2
• Analytical model that takes into account small geometry effects.
• Parameters in addition to those for Level 1:
NFS - Fast surface state density – Used in modeling subthreshold
condition.
NEFF – Total channel charge coefficient – Empirical fitting factor
multiplied times NSUB in the calculation of the short channel effect γ.
Used only in Level 2.
XJ – Junction depth of source and drain.
VMAX – Maximum drift velocity for carriers use for modeling velocity
saturation.
DELTA – Channel width effect on VT.
SPICE Models Level 2 (Continued)

• XQC – Coefficient of channel charge share. Used to specify the portion of the
channel charge attributed to the drain. Also, more importantly causes the
Ward capacitive model to replace the Myer capacitance model. Both have
their disadvantages.
• Next three parameters produce a multiplicative surface mobility degradation
factor to multiply times KP and appear in Level 2 only.
UCRIT – Critical electric field for mobility degradation.
UEXP – Exponent coefficient for mobility degradation.
UTRA – Transverse field coefficient for mobility degradation.
Coefficient of VDS in denominator of the factor.
Saturation of carrier velocity
SPICE Modeling (Level 3)

- Level 3 was developed to specifically address small geometry effects.

- instead of trying to come up with an expression for each and every bump
and wiggle on the IV curve, Level 3 instead moves toward a more empirical
approach.
- curve-fitting parameters are added to the IV equations from Level 1 and Level 2.
- these parameters are dialed-in based on measurement data from a test run of
transistors.
SPICE Models Level 3

• More empirical and less analytical than Level 2; this permits improved
convergence and simpler computation while sacrificing little accuracy.
• The parameters have beyond those in Level 2 (Note that the following Level 2
parameters are deleted: NEFF, UCRIT, UEXP, and UTRA.)
KAPPA – Saturation field factor. An empirical factor in the equation
for the channel length in saturation.
ETA – static feedback on VT. Models effect of VDS on VT, i.e., DIBL (Drain-
Induce Barrier Lowering)
THETA – Mobility modulation. Models the effect of VGS on surface
mobility.
Capacitance Models
• Level 1 through 3 use the Myer capacitance model as the default for the
channel capacitance with the option of the Ward model in Levels 2 and 3.
• For the source and drain capacitances, note the junction equation with
reverse bias V with VT, the thermal voltage,

I=Is(eV/VT-1)=-Is for V-4VT

and recall that
Cj =Cj0/(1-V/0)m

where m = 1/2 for an abrupt junction and m = 1/3 for a graded junction. The
parameters:
IS – Bulk junction saturation current.
JS – Bulk junction saturation current density (used with junction areas)
Capacitance Models (Cont.)

PB - 0 – Bulk junction Potential (Built-in voltage)

CJ – Zero-bias bulk junction capacitance per m2
MJ – m – Bulk junction grading coefficient
CJSW – Zero-bias perimeter capacitance per m
MJSW – m – Perimeter capacitance grading coefficient
FC – Bulk junction forward bias coefficient – used in evaluating capacitance under strong forward
bias.
CGBO – Gate-bulk overlap capacitance per meter of L; should be set to 0 if modeled as
interconnect instead.
CGDO – Gate-drain overlap capacitance per meter of W
GDSO – Gate-source overlap capacitance per meter of W
 SPICE Modeling (Level 4 and beyond - BSIM)
- Berkeley Short-Channel IGFET Model

- what is an IGFET?
- the term MOSFET implies a “metal” contact for the gate. Some say
that is in not accurate for transistors that use polysilicon for the gate
contact since polysilicon is not considered a true metal. Of course
polysilicon is a conductor, just not a pure metal.

- so the term “Insulated Gate FET” is used which describes any type
of conducting gate used.

- this is a totally empirical model which reduces the # of curve fitting parameters

- this actually reduces simulation time over the Level 3 models, and sometimes over Level 2 due to
moving away from IV equations with many coefficients.

- there have been many versions of the BSIM models, but the most current is BSIM3

- this is the most commonly used model for accurate simulations.

SPICE Model BSIM (Level 4)
• An empirical model that includes: all of the typical small geometry effects, the non-uniform
doping profile for ion-implanted devices, an automatic parameter extraction program which
produces a consistent set of parameters ΔL and ΔW for the channel
• We will not look at these parameters in detail, but it is quite important to look at the form of
the electrical parameters. Each electrical parameters P is represented by three process
parameters P0, PL, and Pw associated with P
PL PW
P  P0  
L
DL  W
 WL
 
Leff W eff
L and W are drawn dimensions and DL and DW are the net size changes in the drawn
dimensions due to the entire sequence of fabrication steps. The difference shown give Leff and
Weff. The equation for P allows for an adjustment of the electrical parameter as a function of the
effective length and width of the channel
• Parameter extraction uses devices sizes. P0 is for long, wide MOSFET.
• BSIM also uses a new approach to capacitance modeling that avoids the difficulties of errors
and lack of charge conservation in the Meyer model and the errors and convergence problems
in the Ward model.
More SPICE Models: HSPICE Level 28, BSIM2, BSIM3
• HSPICE Level 13 is BSIM
• HSPICE Level 28 - a very popular modification of BSIM, but can only be used in HSPICE
• BSIM2 (HSPICE Level 39) – typical model today for those not using HSPICE
• BSIM3 Version 3.2 (HSPICE Level 49) – a complex new public domain model that is frequently
used today.
Examples of BSIM Model Results
Example of BSIM Model Results

A compact model needs

to accurately model the
transistor behaviors for
any L and W that circuit
designers may specify.
Which Model Should We Use?
- Simulation is always a tradeoff of accuracy vs. simulation time
- Simulation time is a big problem. You’ll never ship if each simulation takes a month.

• Level 1: At best, for quick estimates not requiring accuracy. Very poor for small geometry devices.
Viewed as obsolete by some.
• Level 2: Due to convergence problems and slow computation rate, abandoned in favor of Level 3
or higher.
• Level 3: Good for MOSFET down to about 2 microns.
• BSIM – Level 4 (HSPICE Level 13): good for small geometry MOSFETS with L down to 1 micron and
tox down to 150 Angstroms. Problems near Vsat; negative output conductance; discontinuity in
current at VT. For submicron dimensions, replaced by BSIM2 and HSPICE Level 28.
• BSIM2 (HSPICE Level 39): Good for small geometry MOSFETs with L down to 0.2 micron and tox
down to 36 Angstroms.
• HSPICE Level 28: BSIM with its problems solved; good choice for HSPICE users.
• BSIM3 Version 3 (HSPICE Level 49): Most accurate, but complex.