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CHAPTER 1 Analysis and Design of Biasing Circuits
CHAPTER 1 Analysis and Design of Biasing Circuits
CHAPTER 1 Analysis and Design of Biasing Circuits
-1-
SINGLE STAGE AMPLIFIERS
where, IC is the dc collector current, hFE the dc current gain, IB the dc base current and
ICBO the reverse saturation current of the collector junction with emitter terminal open.
The first term on the right hand side of eq.(1.01) represents a part
of the output current IC proportional to the input current IB , where the proportionality
factor hFE is a large dimensionless number. This term, therefore, represents the amplifying
property of the transistor. The second term on the right hand side represents a dc current
controlled by ICBO and hFE. It does not contribute anything to the amplifying process.
Moreover, since ICBO is very sensitive to temperature, the second term on the right hand
side of eq.(1.01) can become comparable to the first term under certain circumstances,
resulting in operating point instability in an amplifying circuit. It is, therefore, desirable
in amplifier design, in the interest of operating point stability, to make the second term in
eq.(1.01) negligible compared to the first term so that IC will not vary appreciably even if
ICBO changes due to variation in temperature. It is shown in section 1.xx that for low
power transistors the maximum value that the term (1 + h FE) ICBO can assume is
of the order of a few tens of microamperes. Hence the choice of a collector current of the
order of a milliampere or more will make the second term in eq.(1.01) negligible
compared to the first term, thereby ensuring operating point stability against variations in
ICBO. Assuming that the collector current is chosen to be large enough to
make IC ≈ hFE IB >> (1 + hFE) ICBO , eq.(1.01) can be approximated as
IC ≈ hFE IB …………..(1.02)
Note that eq.(1.02) is the equation characterizing an ideal current amplifier for which I B
is the input current and IC the output current with hFE representing the current gain.
Since hFE is typically larger than 100, the BJT offers good current amplification. So it
should be possible to construct an amplifier using this device to amplify any given signal.
-2-
RS ° º
° º
- 3–
RS
IB
+ Signal
VS source
−
IC
RS
VCC
IB
+
VS
−
B
−
VAB
RC
+
IC A
VCC
RS
+
IB
+ VO
VS
− −
C
(c). Connecting RC to obtain Vo proportional to IC. This circuit amplifies
only one half of the signal waveform.
−4 –
Need for Biasing
-5-
Vs
IB , IC
VCC
VCE
-6-
VS
t
IBdc, ICdc
IB , IC
t
(b) Base and collector current waveforms.
VCC
VCEO
VCE
t
(c) Output voltage waveform.
−7 −
Fig.1.04 shows that the full cycle of the signal waveform can be
amplified without distortion if a dc bias current larger than the peak value of the signal
current is injected into the base terminal along with the signal current. Two different
methods of supplying the required bias current to the circuit of Fig.1.02(c) are shown in
Fig.1.05(a) and (b). In the circuit of Fig.1.05(a) the bias source VBB and a resistance RB
RC RC
VCC
RS RS C1
C C2
+ + VCC
VS VS RB
−
− −
RB VBB VBB
(a) Series connection of bias source (b) Shunt connection of bias source
are connected in series with the signal source VS . The resistance RB is inserted in the
circuit so that its magnitude can be adjusted to obtain the required bias current in the base
loop. The capacitor C is used to block the dc component of the output voltage
waveform so that only the amplified signal voltage is allowed to reach the load connected
to the output terminals of the amplifier. In the circuit of Fig.1.05(b) the bias source VBB
in series with the resistance RB is connected in parallel with the signal source VS .
Resistance RB can be used to adjust the magnitude of the bias current. The capacitor C1
prevents the bias battery VBB from sending a dc current through the signal source
unnecessarily. The capacitor C2 blocks the dc component of the output voltage.
−8 –
All the drawbacks listed above for the circuit of Fig.1.05(a) are
absent in the biasing circuit shown in Fig.1.05(b). Since the bias battery VBB as well as
the collector supply battery VCC in Fig.1.05(b) provide positive voltages with respect to
the ground terminal, it should be possible to use a single battery for both purposes. If this
modification is incorporated in Fig.1.05(b), the circuit shown in Fig.1.06 is obtained.
Note that Fig.1.06 is the same as Fig.1.05(b) with the nomenclature VBB changed to VCC.
The circuit shown in Fig.1.06 is a proper amplifier capable of amplifying signals fed to it
without serious distortion and is known as the “fixed bias” amplifier circuit.
RB RC
VCC
is RS i s ib
C2 +
+ C1
VS Vo
− −
Fig.1.06. The fixed bias amplifier circuit which can amplify the full cycle of the
signal waveform
−9 −
+ VCC
RC
+
+
Vin = VBE Vo = VCE
− −
-
Fig.1.07. Circuit for drawing voltage-to-voltage transfer characteristics
− 10 −
C
E
A O VBE VBEon VBE VBEsat
0.5v 0.6v 0.7v
− 11 −
Saturation point
S D VCEsat = 0.2v
− 12 −
Voutac A O C
Output
signal No output No output No output E
VCC Voutac
Vo Q
Voutac
S D
No output
0.2v
Vin
A O C E Q S D
Input
signal
Fig.1.10. Output waveforms for the circuit of Fig 2.01 for various input waveforms
− 13 −
the input of the circuit, there will be no output since for this range of input voltage the
output voltage remains constant at VCC. This is shown as Voutac at O in the figure. An
input waveform, such as that shown at A is obtained by superimposing the signal voltage
on a dc bias voltage equal to −0.2 volts. For this waveform as well as the waveform
shown at C the output remains zero for all time since the output voltage does not vary
within this range of input voltage. For the input waveform shown at E the output voltage
does not vary for all negative values of the ac signal. Positive values of the input signal
causes the output voltage to drop giving rise to the output wave form shown at E. Note
that only the positive half cycles of the input waveform is amplified. The half-waveform
is also inverted at the output. The input voltage waveform shown at Q keeps the full
waveform in the linear range and, correspondingly, the full waveform appears at the
output with reasonable amplification. Such operation makes it a good amplifier and the
0.6 volts dc on which the input signal is superimposed is known as the bias voltage. In
well designed linear amplifiers the dc or quiescent bias voltage will be around 0.6v. The
case of the input voltage shown at F is similar to that of E, except that in this case only
the negative half cycles of the ac signal waveform are amplified with phase inversion.
For the input signal waveform shown at D there will be no output since the transistor
remains in saturation at VCEsat = 0.2v throughout the full period of the ac signal.
− 14 −
VCC
Vo = Vin
VCC
2 Q R1
+ V=0 −
Vo IDC = 0
Vin Vo = Vin
0
0 VCC VCC
Vin 2
amplifiers. It is easy to bias the logic gate to operate at Q, the center of its transfer
characteristics. A CMOS gate, draws no input current since it is constructed using
MOSFETs which have their input gate terminal insulated from the rest of the device by
an oxide layer. Therefore, if a resistance R1 is connected between the input and output
terminals of the logic gate, as shown in Fig.1.11(b), no dc current will flow through R 1
and there will be no voltage across it. This forces the voltage Vo to be equal to Vin. This
constraint Vo = Vin is shown graphically as the dotted straight line in Fig.1.11(a). Since
the quiescent or dc operating point must obey this constraint it must lie on this line. The
quiescent point must also necessarily lie on the transfer characteristics. It follows that the
quiescent point lies at Q, the intersection of the dotted line and the transfer characteristics
as shown in Fig.2.05(a). Therefore, a resistance connected between the input and output
of a CMOS gate forces the quiescent point Q to lie at the center of the transfer
characteristics, as required, and makes Vo = Vin = Vcc / 2 . Note that the magnitude of
resistance of R1 is immaterial as far as biasing is concerned since no current flows
through it. However, the input resistance of the amplifier being dependent on it, low
values are avoided. Typical values for R1 rage between 100K and 20M. A similar
method is used to bias TTL logic gates to operate them in the linear range.
− 15 −
Introduction
− 16 −
RB = 1M RC = 4.7K
VCC = 20v
IB IC
hFE = 100
•
Fig.1.12. Circuit suitable for dc analysis of fixed bias amplifier of Fig.1.06
with circuit and device parameters specified.
Quiescent point
Whenever the dc supply voltage VCC is switched on for the fixed
bias circuit shown in Fig.1.12, voltages and currents settle down to steady state or dc or
quiescent values almost immediately. The steady state dc collector current IC and the
corresponding collector-to-emitter dc voltage VCE across the transistor represent what is
known as the quiescent operating point, or more concisely, the “quiescent point” of the
device.
Load line
The quiescent values of IC and VCE are not independent, but are
related through the circuit equation
Note that eq.(1.03) represents KVL applied around the collector loop in Fig.1.12.
Eq(1.03), known as the load line equation with variables I C and VCE , represents a
straight line, referred to as the collector circuit load line or more commonly “load line”.
This straight line is known as load line because it can be drawn once the load resistance
RC and VCC are known. The easiest way of drawing the load line is to determine the y-
axis and x-axis intercepts named A and B respectively. The y-axis intercept A can
− 17 −
IC
B (Cutoff point)
VCE VCC
The first phase of the graphical analysis of the fixed bias circuit
of Fig.1.12 deals with the problem of locating the quiescent point or dc operating point of
the device on the device characteristics. For this the first step is to draw the collector
circuit load line as explained in connection with Fig.1.13, using numerical values of the
− 18 −
circuit parameters specified in Fig.1.12. For the parameters defined for this circuit, A, the
intercept on the y-axis will be located at IC = VCC / RC = 20 / 4.7K = 4.25 mA and B, the
x-axis intercept will be at VCE = VCC = 20v. If A and B are located on the respective axes
and joined by a straight line the load line is obtained. This is shown in Fig.1.14.
The quiescent point ( V CEO , ICO ) must necessarily lie on the load
line since VCEO and ICO must satisfy eq.(1.03), the load line equation. The exact location
of the quiescent point on the load line is decided by the second constraint imposed by the
device. The device constrains the quiescent point to lie on the device characteristic it is
forced to operate by the circuit. Since the quiescent point must lie on the load line and
also on a particular device characteristic, the intersection of these two lines will specify
the location of the quiescent point. It is necessary to draw these two lines on the same
graph to locate their point of intersection. Because of this it will be very convenient to
draw the load line in step 1 on the common emitter output characteristics as shown in
Fig.1.14 since both graphs have the same variables on the axes.
Saturation line
IB = 50µ A
5mA IB = 40µ A
IB ≈ 42µ A
Saturation point S
A = 4.25mA
4mA
IB = 30µ A
3mA
X Xop X 23µ A
IB = 20µ A
ICO Q IBO
3 2mA 1
Y Yop Y 17µ A
IC IB = 10µ A
1mA
Cutoff point B
VCEO
IB = 0
0 VCE 10v20v
X 2
Y
VCC = IB RB + VBE
Or VBE = VCC − IB RB ……….(1.04)
It is observed that eq.(1.04) has the same form as eq.(1.03), if VBE and IB are taken to be
the variables similar to VCE and IC in eq.(1.03). Eq.1.04 can, therefore, be considered as
the base circuit load line equation represented graphically in Fig.1.15
.
Base circuit load line [ eq.(1.04) ]
VCC
RB
DC operating point
IBO P
To meet
Base-emitter junction VBE axis at VCC
IB characteristics
VBEO
VBE
The dc operating point (VBEO, IBO) of the base-emitter junction must lie on the base load
line since the point (VBEO, IBO) must satisfy eq.(1.04). It must also lie on the base-emitter
characteristics. Therefore the dc operating point of the base-emitter junction will be P, the
intersection of base load line and the base-emitter characteristics as shown in Fig.1.15.
− 20 −
In reasonably well designed amplifiers the operating point VBEO
is designed to be near the center of the linear range. Typical values of VBEO is found to lie
between 0.55v and 0.65v, i.e., 0.6v ± 50mv for silicon transistors. Therefore,
in circuit analysis nominal value of base emitter dc voltage can be
assumed to be 0.6v with little error since most of the commonly used transistors
at present are silicon transistors. For example, if VBE is assumed to be 0.6v in eq.(3.02)
and the numerical values of VCC and RB as given in Fig.1.12 are used IB is obtained as
19.4µ A ≈ 20µ A. It is expected that the graphical method shown in Fig.1.15 will yield a
value for VBEO close to 0.6v and a value for IBO close to 20µ A. This means that the
quiescent operating point must lie on the output characteristics corresponding to IB =
20µ A. Since the quiescent point must also lie on the load line, the intersection of load
line and the characteristics for IB = 20µ A, i.e., the point marked Q in Fig.1.14 will be the
quiescent point. At the quiescent point Q, the collector-to-emitter voltage VCE = VCEO will
be around 11 volts and the collector current IC = ICO will be around 2.2mA as seen from
Fig.1.14.
When the signal voltage reaches the positive peak, the signal
current is in the base loop will reach a positive peak equal to 3µ A and the total base
current ib will be equal to 23µ A. This will correspond to the point marked X in
waveform “1” shown in Fig.1.14.The operating point at this ib will lie at the intersection
of the device characteristics for 23µ A and the load line, i.e., at the point marked Xop on
the load line in Fig.1.14. Corresponding to this VCE will drop to around 9v indicated by
the point X in waveform “2” and IC will increase to around 2.6mA as shown by the point
X in waveform “3”.
At the end of the positive half cycle, the signal voltage will
reduce to zero and the base current will drop to its quiescent value. The operating point
will return back to the point Q on the load line with corresponding quiescent values of
VCE and IC.
When the signal voltage V s reaches its negative peak, the signal
current is will reach a negative peak of −3µ A, the total base current ib will be equal to
17µ A. The operating point will shift to the point marked Yop on the load line in Fig.1.14.
VCE, correspondingly, will increase to 13v and IC will drop to 1.8mA.
At the end of the full cycle, the signal voltage will again reduce
to zero and the base current will drop to its quiescent value. The operating point will
again return back to the point Q on the load line with V CE and IC attaining quiescent
values once more.
(b) Circuit analysis technique for dc analysis of fixed bias amplifier circuit
− 22 −
DC equivalent circuits or dc circuit models for bipolar junction transistors
(VCC − V BE )
IB = …...
RB
(1.06)
In the numerator of eq.(1.06) it will make very little difference whether V BE is taken as
0.6v or 0.6v ± 50mv, since VCC is usually quite large. So in most dc analysis VBE is
taken to be a fixed voltage equal to 0.6v assuming the transistors to be made of silicon
material. This fixed voltage of 0.6v between base and emitter can be represented by a
0.6v dc battery connected between base and emitter in the circuit model of the transistor,
as shown in Fig.1.16(a).
IC = hFE IB …..(1.07)
This linear relation between collector current and base current can be represented by a
current controlled current source connected between collector and emitter in the circuit
model of the BJT, as shown in Fig.1.16(a).
Base Collector
IB IC = hFE IB
Emitter Emitter
− 23 −
VBEsat VCEsat
≈ 0.7v ≈ 0.2v
− 24 −
1. Assume (1 + hFE) ICBO << hFE IB. The approximation IC = hFE IB is then valid.
2. Draw the amplifier circuit modified for dc analysis. (See, for example, Fig.1.12)
3. Assuming the transistor to be in the active region, replace the transistor symbol by
its dc equivalent circuit for active region shown in Fig.1.16(a).
4. Analyse the circuit to find out IB , IC and all the relevant voltages and currents.
5. Verify the validity of the two assumptions made in step 1 and step 3.
− 25 −
VCC = 20v
2mA IB = 20µ A
RB Q (10v, 1mA)
(1.94M) RC (10K)
1mA
IC IB = 10µ A
IC = 1mA
hFE = 100
IB 0 10v 20v
VCE
•
V0
(a) Fixed Bias Circuit (b) Quiescent point for hFE = 100
IB = 10µ A
3mA
Q (0v, 2mA)
Saturation point Q (0v, 2mA)
2mA 2mA Saturation point
IB = 10µ A
0 20v 0 20v
VCE VCE
(c) Quiescent point for hFE = 200 (d) Quiescent point for hFE = 300
Fig.1.17. Shift of quiescent point with change in hFE for a fixed bias circuit.
− 26 −
− 27 −
(a) If hFE shifts to 100 (b) For hFE = 200 (c) If hFE shifts to 300
Fig.1.18. Performance of optimal design of fixed bias circuit using hFE = hFEtyp = 200
− 28 −
200
150
hFE 150oC
100
60oC
50 0oC
− 55oC
0 5 IC 10 15
− 29 −
1. Fixed bias
+ VCC
RB RC
hFE ( VCC − VBE 0 ± ∆VBE )
IC IC = + ( 1 + hFE ) I CB 0
RB
IB
2. Collector-to-base bias
+ VCC
RC
IB
− 31 −
3. Emitter bias
+ VCC
RC
RB
IC
hFE ( VCC − VBE 0 ± ∆ VBE ) ( 1 + hFE ) I CB 0
IC = +
IB RB + ( 1 + hFE ) RE h R
1 + FE E
RB + RE
RE
•
Fig.T.1.1.03. Emitter bias circuit
+ VCC
RC
RB
IC + IB
IC
RE
•
Fig.T.1.1.04. Collector-to-base cum emitter bias
− 32 −
+ VCC
R1 RC
IC
IB
hFE ( ETH − VBE 0 ± ∆VBE ) ( 1 + hFE ) I CB 0
IC = +
RTH + ( 1 + hFE ) RE h R
1 + FE E
RTH + RE
R2 RE
VCC R2
where, RTH = R1 ⁄ ⁄ R2 and ETH =
R1 + R 2
•
+ VCC
RC
R1
I + IC
I IC
IB
R + RC
hFE VCC − (1 + 1 ) (VBE 0 ± ∆VBE )
IC = R2 + (1 + hFE ) I CB 0
R2 +
R1 + (1 + hFE ) RC hFE RC
1+
R1 + RC
VBE
−
•
Fig.T.1.1.06. VBE multiplier bias circuit
− 33 −
All the six biasing circuits shown in Table.1.1 can provide the
bias current required. The fixed bias circuit provides no stability for the quiescent point
as explained earlier. The collector-to-base bias, the emitter bias and the collector-to-base
cum emitter bias provide varying degrees of stability for the collector current and the
quiescent point. The voltage divider bias and the VBE multiplier bias can provide
reasonably good stability for the collector current and the quiescent point through careful
design.
Eliminating IB between eq.(1.08) and eq.(1.01), the expression for IC given in Table.1.1 is
obtained.
R1 RC RC
IB IB
ETH = VCC R2
R2 RE
R1+ R2 RE
− 34 −
drawn with slight modification of the voltage divider bias circuit, will have the same
voltage and current at all points as the original circuit. This is due to the fact that in the
redrawn circuit also the upper end of both resistors R1 and RC has the same voltage VCC as
the original circuit. The second step is to replace the circuit to the left of the dotted line
by its Thevenin equivalent as shown in part (b) of the figure. Thevenin voltage E TH of the
equivalent circuit will be [VCC R2] ⁄ [R1 + R2] and Thevenin resistance RTH will be [R1
⁄ ⁄ R2] = [R1 R2] ⁄ [R1 + R2]. The loop equation for the base loop can be written as
Eliminating IB between eqs.(1.09) and (1.01) the expression for collector current IC for the
voltage divider bias circuit, given in Table.1.1, is obtained.
The V BE multiplier bias circuit uses the transistor to simulate a
zener diode. A good understanding of this type of bias can be obtained by an analysis of
the BJT circuit which simulates a zener diode.
A A
I = IR1 + IC
R1 IC
IR1 = IR2 + IB R 1 + R2
IB VZ = VBE
R2
IR2 = VBE ⁄ R2
R2
B B
− 35 −
P
O VAB VBE (R1 + R2)
R2
(c) Current – Voltage relation of the VBE multiplier
Eq.(1.11) shows that once the transistor enters the active region VAB tends to remain
constant at VBE ( R1 + R2 ) ⁄ R2 . Any attempt to increase VAB above this value will result
− 36 −
in abnormally high values of current and, unless this current is limited to safe values by
an external series resistance, it will cause destruction of the transistor. In the active region
of the transistor, where VAB remains constant, the current-voltage relation of the circuit
can be represented by the vertical straight line PQ shown in Fig.1.21(c).
RA A
RB
RC
RD B
− 37 −
From Fig.T.1.1.06
IB = I − VBE ……..(1.15)
R2
− 38 −
− 39 −
T j − Tjref
I CB 0 (Tj ) = ICB0ref
10
……..(1.21)
2
− 40 −
where, ICB0 (Tj) is the magnitude of ICB0 at any arbitrary collector junction temperature
Tj and ICB0ref is the magnitude of ICB0 at a reference collector junction temperature Tjref
specified by the manufacturer. The data sheets of the transistor BC 107, given in
Appendix X, specifies ICB0 to be less than 15µ A at 150oC so that for this transistor
ICB0ref = 15µ A and Tjref = 150oC. If a maximum ambient temperature of 55oC is
assumed and a further increase of 5oC in collector junction temperature due to power
dissipation in the transistor is estimated, the maximum possible junction temperature can
be taken to be 60oC. Corresponding to a maximum junction temperature of 60oC and
the specifications of the transistor indicated above, ICB0max the maximum value of the
collector junction reverse saturation current for BC 107, calculated using eq.(1.21), will
be 29.3nA. hFEmax for BC 107A is specified as 220 in the data sheets. Using this value of
hFEmax the maximum value of (1 + hFEmax) ICB0max is calculated as 6.45µ A. The data sheets
also shows that the BC 107B and BC 107C has hFEmax equal to 450 and 800 respectively.
For hFEmax equal to 450 and 800 the maximum value of (1 + hFEmax) ICB0max is obtained as
13.2µ A and 23.4µ A respectively. If IC is chosen to be greater than about 0.5mA it
will make IC >> (1 + hFEmax) ICB0max and variations in ICB0 will have negligible effect on IC .
Conclusion :
• A choice of IC ≥ 0.5mA will stabilize IC against variations in ICB0 for all the six
biasing circuits shown in Table.1.1.
The h FE of the transistor, inserted into the circuit after the design
is completed, can take any value between hFEmin and hFEmax specified by the manufacturer.
For most transistors hFEmin and hFEmax are separated by a ratio 1:3. In many cases the ratio
is larger and in a few cases it is smaller. The main reason for variation in hFE of the
transistor used in any circuit is the wide tolerance specified by the manufacturer. The
change in hFE due to ambient temperature variation and temperature variation due to
power dissipation in the transistor in low power circuits is less significant.
− 41 −
The expressions for I C for collector-to-base bias, emitter bias and
collector-to-base cum emitter bias circuits show that hFE occurs in the numerator as well
as the denominator of the first term. This means that these circuits provide varying
degrees of stability of IC with respect to hFE variations and are better than the fixed bias
circuit in this respect. A satisfactory way of designing these circuits is to use the typical
value of hFE for their design, as was recommended for the fixed bias circuit, and accept
any possible shifts in the quiescent point due to variations in hFE .
hFE is usually larger than 100 and hFE ⁄ (1 + hFE) can be approximated to unity with less
than 1% error. With this approximation eq.(1.23) reduces to
The expression given in eq.(1.24) for IC is independent of hFE . This shows that making
RTH << (1 + hFE)RE stabilizes IC against variations in hFE for voltage divider bias circuits.
This condition for stability has to be satisfied even for the lowest value of h FE . So the
stability condition is usually written as RTH << (1 + hFEmin)RE . Once the stability
condition is satisfied the voltage drop across RTH becomes negligible and, as seen from
Fig.1.20(b), the voltage drop between the base terminal and ground can be approximated
to ETH . This means that for normally expected variations in base current the voltage at
the base terminal remains constant at ETH , the voltage across R2 . Fig.1.20(a) shows that
the voltage across R2 remains constant at ETH = [VCC R2] ⁄ [R1 + R2] for all values of IB
only if IBmax is negligible compared to the current through R1 and R2 . A different way of
expressing the stability condition is to specify IBmax << IR1 ≈ IR2 . Stability condition
expressed this way is very often more useful for designing certain types of circuits.
− 42 −
The expression for IC , given in table.1.1, for VBE multiplier bias
shows that, with the last term rendered negligible by design, the first term will be
independent of hFE if R1 << (1 + hFE)RC . Eq.(1.20) shows that the same condition will
make the quiescent voltage VCE independent of hFE . Obviously, this condition for
stability has to be satisfied even for the minimum value of hFE . So the stability condition
is usually expressed as R1 << (1 + hFEmin)RC
Conclusion :
• The collector current of fixed bias, collector-to-base bias, emitter bias and
collector-to-base cum emitter bias circuits cannot be stabilized against variations
in hFE . A satisfactory way of designing them will be to complete the design using
typical value of hFE .
• The collector current of voltage divider bias circuit can be stabilized against
variations in hFE by making RTH << (1 + hFEmin)RE or RTH = (1⁄ K) (1 + hFEmin)RE ,
where, a value of K equal to or larger than 10 is usually satisfactory.
• For the VBE multiplier bias circuit the collector current can be stabilized against
variations in hFE by making R1 << (1 + hFEmin)RC .
25oC and a further temperature rise of 5oC above ambient is assumed for the collector
junction due to power dissipation in the transistor, the collector junction temperature Tj
can be expressed as 30o ± 25oC. Corresponding to this the base-emitter voltage can be
expressed as VBE0 ± ∆ VBE , where VBE0 is the base-emitter voltage at the average
temperature and ± ∆ VBE is the change in base-emitter voltage corresponding to ±
o
25 C temperature variation. A nominal value of 0.6v is assumed for VBE0 in the case of
silicon transistors and ± ∆ VBE corresponds to ± 62.5mV for a temperature variation
of ± 25oC.
For the first four biasing circuits of Table.1.1 the expression for
IC contains ∆ VBE in the form (VCC − VBE0 ± ∆ VBE). Since VCC − VBE0 is usually of the
order of 10 volts or more and ∆ VBE has been estimated to be 62.5mV , the term (VCC −
VBE0 ± ∆ VBE) will show negligible variation corresponding to a change in base-emitter
voltage ∆ VBE of the order of 62.5mV. This means that the quiescent point of the first
four circuits in Table.1.1 are inherently stable against variations in VBE .
− 43 −
voltage approximately equal to ETH as indicated earlier. Fig.1.20 shows that (ETH − VBE0)
represents the voltage drop VRE across the emitter resistance RE at the average
temperature. The stability condition for IC against variations in VBE can be expressed as
∆ VBE << VRE . The change in base-emitter voltage ∆ VBE has been estimated as
62.5mV. Therefore, if VRE >> 62.5mV the voltage divider bias circuit will be stabilized
against variations in VBE . A choice of VRE of the order of 0.6v to 2v is usually
satisfactory. A higher VRE will provide better stability, but it will reduce the peak-to-peak
undistorted output available from the circuit. If eq.(1.24) is stabilized with respect to VBE
by making its variable part ∆ VBE << ( ETH − VBE0 ) it reduces to
E TH − V BE 0
IC = ……..
RE
(1.25)
IC given by eq.(1.25) is independent of variations in ICB0 , hFE and VBE as required.
Eqs.(1.11) and (1.20) show that the quiescent voltage V CE for the
VBE multiplier bias circuit is given by the expression
R + R2
VCE = VBE 1 ……..
R1
(1.26)
Eq.(1.26) shows that the quiescent voltage VCE will have a temperature coefficient equal
to the temperature coefficient of VBE multiplied by [(R1 + R2) ⁄ R2] . For a temperature
variation of ± 25oC the quiescent voltage will vary by ± 62.5 mV multiplied by
[(R1 + R2) ⁄ R2] . This variation is typically of the order of ± 1.25 volts if VCE is
designed to be around 12v. This order of variation is not very serious in amplifier
circuits.
Conclusion :
• The collector current IC for fixed bias, collector-to-base bias, emitter bias and
collector-to-base cum emitter bias circuits are inherently stable against variations
in VBE .
• The collector current IC for the voltage divider bias circuit can be stabilized
against variations in base-emitter voltage if VRE >> ∆ VBE ( ≈ 62.5mV ). A value
of VRE between 0.5v and 2v is usually satisfactory.
• The VBE multiplier circuit is reasonably stable against variations in VBE .
The steps for designing the six biasing circuits given in Table.1.1
can be written in three different sets. The first set of steps is a common set suitable for
designing the first four biasing circuits given in Table.1.1, namely, the fixed bias,
collector-to-base bias, emitter bias and collector-to-base cum emitter bias circuits. The
second set of steps is specifically written for the voltage divider bias circuit and a third
set specifically for the VBE multiplier bias circuit.
− 44 −
Steps for designing fixed bias, collector-to-base bias, emitter bias and collector-to-
base cum emitter bias circuits.
V R R1 R2 1
ETH = CC 2 and RTH << (1 + hFE min ) or = (1 + hFE min ) RE
R1 + R2 R1 + R2 K
− 45 −
Eq.1.25 shows that for a voltage divider bias circuit the collector
current IC can be designed to be a constant, independent of variations in ICB0 , hFE and
VBE . Since ETH = [(VCC R2) ⁄ (R1 + R2)] the collector current is seen to be independent
of RC also. Even if the collector resistance is replaced by a short circuit so that RC = 0,
the collector current remains the same with VCE = VCC . When RC is increased from zero
to finite values IC remains constant and VCE decreases below VCC . As RC is increased
continuously IC stays constant and VCE decreases steadily till the transistor is saturated,
beyond which eq.(1.25) is no longer valid. This shows that as far as the collector load
resistance is concerned the voltage divider bias circuit behaves like a constant current
circuit so long as the transistor remains in the active region. Voltage divider bias circuit
as a constant current circuit finds many uses such as differential amplifier circuits,
analogue dc voltage regulators, emitter-coupled multivibrators, etc.
− 46 −
where, IDS is the drain current, IDSS the saturation drain current with VGS = 0, VGS the gate-
to-source voltage and VP the pinch off voltage of the JFET. The parameters IDSS and VP
for the FET s are specified by the manufacturer.
RD
RS
RS VDD
+ + +
VGS − +
VS Vo
VS −
− −
• •
(a) Connecting signal source to JFET (b) Connecting RD and VDD to obtain Vo
to obtain VGS proportional to VS Amplifies waveform with distortion
− 47 −
R
Manufacturer specifies IDSS and VP IDSS = 10mA
P
A B
Q IDS0
VO VO
M
Pinch off voltage VP = − 8v
S Output signals
VGS0
− 8v − 6v − 4v − 2v 0 VGS
VIN
Input signals
VIN
VS
0
t
VGS
0
− 49 −
VGS
VGS0
− VGS0
−50 −
+ VDD + VDD
RD RD
RS RS C
+ +
RG
VS VS
VGG
− −
RG VGG
• •
(a) Bias applied in series with VS (b) Bias applied in parallel with VS
Fig.1.27. Two methods of applying negative bias to JFET circuits : both inconvenient.
biasing if bias is applied in series with VS or a single battery with connections to each
stage if bias is applied in parallel with VS . Both methods are inconvenient since extra
batteries are required for biasing.
RD
IDS = 4mA
RS C
+ + +
VS VRG RG RSO = 750Ω
3v
− −
•
Fig.1.28. JFET amplifier with self bias
− 51 −
connected from the source terminal of the JFET to ground, the 4mA quiescent current
passing through it will develop 3 volts across it, as shown in the figure. If the gate-to-
ground voltage is negligibly small VGS = − IDS RSO = − 3 volts and the quiescent point
will be located at the point chosen. With RG absent, the voltage between gate and ground
is, by and large, indeterminate. RG is connected to fix the voltage between these two
points. With RG connected the dc current through it will be the reverse saturation current
ISG of the gate-channel junction which is usually around 10nA. If RG is restricted to
10MΩ , VRG the voltage drop across it will be of the order of 100mV, which is
negligible compared to the 3 volts across RSO so that VGS = VRG − IDS RSO ≈ − 3 volts as
required. In JFET amplifiers the resistance RG is required and its value should be
restricted to a maximum of around 10MΩ to make VRG the voltage across it negligible
compared to the bias voltage VGS0 developed across RSO . If this is not done the reverse
saturation current ISG , which is temperature sensitive, will cause VRG and, consequently,
the quiescent bias voltage to vary with temperature. This circuit is known as the ‘‘self
bias’’ circuit because the current through the device itself is used for developing the
voltage required for biasing.
It is seen from Fig.1.28 that the gate-to-source voltage VGS of the JFET is given by
VGS0 and IDS0 must satisfy eq.(1.29) also. Substituting VGS0 for VGS and IDS0 for IDS in eqs.
(1.28) and (1.29) and solving, the quiescent parameters VGS0 and IDS0 can be evaluated.
− 52 −
Transfer characteristics
IDS = IDSS [ 1 − (VGS ⁄ VP)] 2
IDSS = 10mA
Bias line
VGS = − IDS RSO
Q IDS
IDS0 = 4mA
− 8v − 6v − 4v − 2v 0 VGS
The first step in the graphical analysis of the JFET self bias
circuit is to draw the transfer characteristics of the JFET defined by eq.1.28, as shown in
Fig.1.29. The quiescent point lies on this curve. The quiescent point must also satisfy eq.
(1.29) which represents a straight line known as the ‘‘bias line’’. The second step in the
graphical analysis is to draw the bias line as shown in Fig.1.29. The point of intersection
of transfer characteristics and bias line represents the quiescent point indicated as Q in the
figure.
− 53 −
Transfer characteristics
IDS = IDSS [ 1 − (VGS ⁄ VP)] 2
IDSSmax = 10mA
IDS
Bias line
VGS = − IDS RSO IDSStyp = 6mA
Q1 IDS0max = 4mA
Q2 IDSSmin = 3.3mA
2mA
Q3 IDS0min = 1.2mA
− 8v − 6v − 4v − 2v 0 VGS
+ VCC + VCC
R1
VCC R2
VGG = ……..(1.30)
R1 + R2
Eq.(1.31) is represented graphically as the bias line in Fig.1.32. The quiescent points
corresponding to this bias line will be located at QA , Q and QB. Note that the location of
the quiescent point lies between QA and QB . This variation is less than that seen in
Fig.1.30 for the self bias circuit which means that voltage divider bias circuit gives better
stability for IDS than self bias circuit. Obviously, larger values of VGG gives better
stability of IDS in voltage divider bias circuit. This type of biasing is, therefore, suitable in
cases where the supply voltage VCC is large so that VGG , derived from VCC , can be made
large to obtain better stability for IDS . This will automatically mean a large voltage
between source terminal and ground since VGS is likely to be around 1 to 4 volts only.
This type of biasing is very much suitable for common drain amplifiers, i.e., source
followers.
IDSSmax
IDS
QA
Q Q3 IDSSmin IDS = I0
Bias line (Constant current bias)
QB
VGG
− 8v − 6v − 4v − 2v 0 VGS
Fig.1.32. Bias lines for constant current and voltage divider bias circuits
− 55 −
MOSFETs
− 56 −
2
V
I DSon 1 − GS
Vth
I DS = 2 ……..(1.33)
V
1 − GSon
Vth
Typical
characteristics
IDSO1
IDSon
Constant current bias line
IDS
IDSO2
Vth VGSon
VGS
− 57 −
The bias voltage VGSO is a constant independent of the transistor used. Such an
arrangement constitutes a constant voltage bias represented by a vertical bias line parallel
to IDS axis as shown in Fig.1.33. For such an arrangement IDSO , the quiescent drain
current varies very widely from IDSO1 to IDSO3 for the three characteristics shown for the
same transistor. Such a biasing arrangement is to be avoided in the interest of a stable
quiescent point.
+ VDD + VDD
R1 RD R1 RD
VGG VGG
R2
R2 RSO
•
•
(a) Constant voltage bias with poor (b) Voltage divider bias with acceptable
stability for quiescent point stability of quiescent point
− 58 −
where, Vth is the threshold voltage of the transistor and IDSS the value of IDS when VGS is
zero. Eq.(1.35) is valid for the region where VGS > Vth . The manufacturer specifies Vth
and IDSS for the transistor. Vth in this case can be thought of as the pinch-off voltage of the
transistor similar to that of the JFET.
IDS
IDSS1
IDSS2
− Vth VGS
− 59 −
+ VDD + VDD
RD
R1 RD
R3 R1
R2
R2
RE R4 RSO
• •
− 60 −
Current Mirrors
+ VCC + VCC
R
ICref Q1 Q2 Qn
IB1
Qref Q1 Qref
IBref
• •
(a) Two-transistor (b) Multi-transistor
The two transistors in Fig.1.37(a) have the same base-emitter voltage. Assuming Qref and
Q1 to have identical characteristics because they are on the same IC chip and because
they have the same base-emitter voltage, ICref = IC1 and IBref = IB1. Substituting these values
in eq.(1.36),
− 61 −
( VCC −0.6 ) I C1 2
Iref = = IC1 + IB1 + IB1 = IC1 + 2 = IC1 1 + ……
R hFE hFE
(1.37)
Or
I ref ( VCC −0.6 )
IC1 = 2 = 2 ……..
1 + R 1 +
hFE hFE
(1.38)
Note that IC1 given by eq.(1.38) is a constant current with the collector voltage of Q1 free
to swing with the signal. Using the same approach it can be easily shown that for the
multi-transistor circuit shown in Fig.1.37(b)
Eq.(1.39) shows that each of the transistors Q1 to Qn behaves like a constant current
device and can be used at a different place in an IC.