1050 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 23, NO.
6, JUNE 2015
Scan Test Bandwidth Management for
Ultralarge-Scale System-on-Chip
Architectures
Wu-Tung Cheng, Fellow, IEEE, Yan Dong, Grady Gilles, Member, IEEE, Yu Huang, Senior Member, IEEE,
Jakub Janicki, Mark Kassab, Senior Member, IEEE, Grzegorz Mrugalski, Senior Member, IEEE,
Nilanjan Mukherjee, Senior Member, IEEE, Janusz Rajski, Fellow, IEEE,
and Jerzy Tyszer, Fellow, IEEE
Abstract— This paper presents several techniques employed
to resolve problems surfacing when applying scan bandwidth
management to large industrial multicore system-on-chip (SoC)
designs with embedded test data compression. These designs pose
significant challenges to the channel management scheme, flow,
and tools. This paper introduces several test logic architectures
that facilitate preemptive test scheduling for SoC circuits with
embedded deterministic test-based test data compression. The
same solutions allow efficient handling of physical constraints in
realistic applications. Finally, state-of-the-art SoC test scheduling
algorithms are rearchitected accordingly by making provisions
for: 1) setting up time-effective test configurations; 2) optimiza-
tion of SoC pin partitions; 3) allocation of core-level channels
based on scan data volume; and 4) more flexible core-wise
usage of automatic test equipment channel resources. A detailed
case study is illustrated herein with a variety of experiments
allowing one to learn how to tradeoff different architectures and
test-related factors.
Index Terms— Bandwidth management, embedded determin-
istic test (EDT), scan-based test, test access mechanism (TAM),
test application time, test compression, test scheduling.
I. I NTRODUCTION
T ODAY’S multicore chip architectures require no trivial
test solutions imposed by the relentless miniaturization
of semiconductor devices, which have become much faster
and less power hungry than their predecessors. This trend has
given rise to the growing popularity of system-on-chip (SoC)
designs because of their ability to encapsulate many disparate
types of complex IP cores running at different clock rates
Manuscript received February 19, 2014; revised May 14, 2014; accepted
June 9, 2014. Date of publication July 16, 2014; date of current version
May 20, 2015. The work of J. Janicki and J. Tyszer was supported by the
Semiconductor Research Corporation under Grant 2011-TJ-2117.
W.-T. Cheng, Y. Huang, M. Kassab, G. Mrugalski, N. Mukherjee,
and J. Rajski are with Mentor Graphics Corporation, Wilsonville,
OR 97070 USA (e-mail: wu-tung_cheng@mentor.com; yu_huang@
mentor.com; mark_kassab@mentor.com; grzegorz_mrugalski@mentor.com;
nilanjan_mukherjee@mentor.com; janusz_rajski@mentor.com).
Y. Dong and G. Giles are with Advanced Micro Devices Inc., Sunnyvale,
CA 94088 USA (e-mail: yan.dong@amd.com; grady.giles@amd.com).
J. Janicki and J. Tyszer are with the Faculty of Electronics and Telecommu-
nications, Poznan University of Technology, Poznan 60-965, Poland (e-mail:
jjanicki@et.put.poznan.pl; jerzy.tyszer@put.poznan.pl).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TVLSI.2014.2332469
1063-8210 © 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
with different power requirements and multiple power-supply
voltage levels. Many SoC-based test schemes proposed so
far utilize dedicated instrumentation, including test access
mechanisms (TAMs) and test wrappers [7], [9], [22]. TAMs
are typically used to transfer test data between the SoC
pins and embedded cores, whereas test wrappers form the
interface between the core and SoC environment. Solutions
involving both TAMs and wrappers accomplish such tasks as
optimizing test interface architecture [26] or control logic [20]
while addressing routing and layout constraints or hierarchy
of cores [2], [5], scheduling test procedures [1], [18], [19],
[21], [31], and minimizing power consumption [8], [16], [30].
Techniques proposed in [4], [9], [10], and [25] attempt to
minimize SoC test time. The integrated scheme of [9] reduces
the test time by optimizing dedicated TAMs and pin-count-
aware test scheduling. Packet-switched networks-on-chip [25]
can replace dedicated TAMs in testing of SoC by delivering
test data through an on-chip communication infrastructure.
There are techniques addressing synergistically TAM and
wrapper design as well as test data compression [3], [11],
[12], [27]–[29]. In fact, test compression is now becoming
an integral part of SoC-based design-for-test (DFT) schemes.
For example, the approach of [17] encodes tests for
each core separately through linear feedback shift
register (LFSR) reseeding with time-multiplexed automatic
test equipment (ATE) channels delivering data to successive
cores. Similarly, a scheme of [32] utilizes static reseeding to
test SoCs, where all cores share a single LFSR. The XOR
test logic performs compression in [6], which further guides
a TAM design process.
ATE channel bandwidth management for SoC designs can
play a key role in increasing test data compression with
no visible impact on test application time. The approach
presented in [13] encompasses: 1) a solver capable of using
input and output channels dynamically; 2) test scheduling
algorithms; and 3) TAM design schemes, all devised for
the embedded deterministic test (EDT) environment [24].
It is assumed that all cores in the SoC are either hetero-
geneous modules, or wrapped testable units, and they come
with their individual EDT-based compression logic, which
is subsequently interfaced with ATE through an optimized
CHENG et al.: SCAN TEST BANDWIDTH MANAGEMENT FOR ULTRALARGE-SCALE SoC ARCHITECTURES
number of channels. As a result, test scheduling and TAMs
can assign a fraction of the ATE interface capacity to each
core. It increases compression ratios and allows tradeoffs
between the test application time, volume of test data, test
pin count, and interface design complexity. The scheme of
[13] is applicable to any SoC-based test data reduction scheme
capable of working with a varying number of In and output
channels.
Implementing a hierarchical DFT methodology for designs
with a large number of cores poses significant challenges.
First of all, the number of chip-level pins is limited and
does not suffice to drive all cores in parallel. Given the pin
limitations, it is impossible to determine the optimal allocation
of pins to cores for the best compression. Furthermore, since
a particular core can be reused in multiple designs, an optimal
number of channel pins for this core when embedded in one
design may invalidate test reuse in other designs. Under such
circumstances, the chip integrators collect data for all indi-
vidual cores, examine the data along with all constraints for
the design, and then manually determine test schedules. This
may result in suboptimal test data volume and compromised
test application time, especially because of some outlier blocks
having large pattern counts (PCs).
Bandwidth management mitigates the dependence of core
channels on the number of available chip-level pins, allows
automatic scheduling of tests by making it transparent to the
users, and significantly improves test planning at the core-
level. It also arbitrates the sharing of the chip-level channel
pins, thereby guaranteeing the best data volume and test time
reductions for the overall design. In this paper, we present a
bandwidth management scheme for hierarchical designs that
lets a designer tradeoff fixed and flexible channel allocations
per core as well as physical constraints to minimize the
routing overhead of the TAM-based networks. Furthermore,
several techniques to deliver the control data during test are
examined altogether with a new scheduling algorithm that
allows changing the In and output channel allocations when
switching the channel configurations.
The remainder of this paper is organized as follows. After
recalling principles of the EDT-based bandwidth management
in Section II, Section III describes cost-effective schemes used
to deliver control data, and subsequently to setup SoC test con-
figurations. Section IV introduces a conditional merging-based
test scheduler. It paves the way for more advanced test time
reduction techniques based on balanced I/O pins partitioning,
priority-based routing, and selective adjusting of interface
throughput. Partitioning of SoC designs and handling their pin
layout constraints are among key factors characterizing a large
industrial SoC test case introduced in Section V. Section VI
details experimental results obtained for this design. This paper
concludes with Section VII.
II. P RIOR W ORK
The SoC test environment (Fig. 1) of this paper comprises
two switching networks, as introduced in [13]. An external
ATE In channel i (ICi ) feeds an In-switching network that
reroutes compressed test data to different cores (in the remain-
ing parts of this paper a given core k is denoted as Ck )
1051
Fig. 1. SoC test environment with on-chip compression.
based on the control data produced by a test scheduler. Since
the scan routing paths from the chip-level test pins to the
core-level test pins are dynamically selected by patterns, this
interconnection network is also referred to as a dynamic scan
router (DSR). Identical modules may share the same test
data in the broadcast mode. In addition to individual EDT
decompressors, each core features X-masking logic protecting
its response compactor against unknown states and connecting
the core with an output-switching network. This network
allows the compressed output streams from successive cores
to reach an output channel i (OCi ), and to be sent back
to the ATE. In order to facilitate test pattern reuse, test
wrappers isolate all cores so that they are independent of
each other.
As shown in Fig. 1, the In DSR consists of demultiplexers
whose number matches the number of ATE In channels. Given
a group of test patterns, each demultiplexer connects the
corresponding channel to one of several destination cores, as
indicated by the content of address register. The number of
ATE In channels cannot be smaller than the capacity of the
largest single core in terms of its EDT In. Clearly, in the
worst case, we can still test the largest cores, one at a time.
Typically, low-order In of each core are used more frequently
than others [13]. Hence, OR gates are deployed to assure that
these In can receive data from more than a single ATE channel
to increase flexibility of a test scheduler.
Given the ATE In channels, the associated demultiplexers,
and all cores with OR gates driving their EDT In, the actual
connections between these terminals are arranged as follows.
The EDT In (alternatively, OR gate In, if any) are connected
with the demultiplexers in such a way that n EDT In of a given
core are linked with n different ATE In channels, and each
ATE channel serves approximately the same number of cores.
This method yields the actual size of the In demultiplexers and
their control registers. Some final adjustments within a single
module are also possible to simplify the resultant DSR layout
and avoid costly and long connections.
1052 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 23, NO. 6, JUNE 2015
The output DSR (Fig. 1) interfaces all core outputs with the
ATE by reducing the number of test response streams so that
they fit into the number of output ATE channels. It is made
up of a number of multiplexers such that each multiplexer
serves to connect several cores with a designated ATE output
channel. Again, the address registers specify which cores are
to be observed for a given group of test patterns. The output
channel mapping is carried out in a manner similar to that of
the In DSR. Note that all core outputs feature a user-defined
fan-out in order to increase flexibility of selecting observation
points connected to the multiplexers. It is also assumed that
all core outputs need to be observed when tested.
It is worth noting that a flexible use of ATE channels results
in increased compression and elevated encoding efficiency.
Moreover, testing many cores in parallel by dynamically
allocating ATE channels to different cores in accordance with
their needs may shorten test application time. Finally, having
individual decompressors running in appropriate time slots
makes it easier to reduce the number of external channels
compared with the total number of EDT In featured by all
cores together. In preparation for the actual test session, the
following steps are carried out (a detailed description of this
procedure can be found in [13]).
1) For each core, automatic test pattern generation (ATPG)-
produced test cubes are passed to a solver that merges
and encodes them to arrive with final compressed test
patterns; furthermore, the solver determines the minimal
number of EDT In channels needed to compress a given
test pattern.
2) For each test pattern at the core level, information
regarding the minimal number of EDT In channels is
paired with data concerning the required EDT output
channels.
3) All test patterns are clustered to form groups (classes)
of patterns having identical both In channels and obser-
vation points.
4) Upon completion of the above operations for each core,
all classes are passed to a test scheduler; given architec-
ture of both test access networks and various constraints
(ATE channels, DSR architecture, power consumption,
and others), it yields the final allocation of ATE In/output
channels to selected cores when applying successive test
patterns.
Given both DSRs, one can now schedule application of test
patterns. Every test pattern t is characterized by its descriptor
comprising module m that is to be exercised when applying
test t, and the channel capacity c, i.e., the number of EDT In
and outputs needed for this purpose. All test patterns having
the same descriptor form a setup class x represented by its
PC P(x). Every setup class can be split into multiple segments
such that test patterns from the same class are applied in
disjoint time intervals. The ability to preempt a class may
improve the ATE channel utilization, shorten the total test
time, and reduce the volume of control data.
In principle, test scheduling merges complementary setup
classes to form clusters of cores that can be tested in parallel
given constraints imposed by ATE channels and DSRs. Setup
classes are complementary if they comprise disjoint subsets of
cores. Let L be a sorted list of setup classes with a class x
having the largest value of c · P(x) seating in the front.
We begin by assigning the first element of L to the current
result b of merging to form a base. Then, the algorithm iterates
over all the remaining setup classes and expands the base by
one class at a time, always taking the first class from L that
satisfies all constraints, including availability of ATE channels
and the ability of DSRs to serve the base.
The process of forming the base class terminates when
either there are no more setup classes complementary with
the base, or one of the constraints cannot be satisfied. The
merging algorithm removes then the first element from list L
and attempts to form another base cluster until the list of
setup classes becomes empty, in which case the scheduling
algorithm returns a list of base classes that determines the
actual schedule, i.e., an order according to which cores will be
tested, as well as actual channel allocations. It can be further
reordered to group tests for the same core in contiguous time
intervals, finally forming test configurations indicating which
ATE channels are to connect with which EDT channels of
which cores and for how long.
III. C ONTROL DATA D ELIVERY
The approach summarized in Section II does not make any
specific provisions for the way control data is delivered to
SoC test logic in order to setup test configurations. It appears,
however, that the number of test configurations, and hence
the amount of control data one needs to employ and transfer
between the ATE and DSR address registers, may visibly
impact test scheduling and the resultant test time. Conse-
quently, we begin this paper by analyzing three alternative
schemes that can be used to upload control bits and show
how they determine the final SoC test logic architecture.
A. Using IJTAG
The IEEE 1687 is a proposed standard for accessing
on-chip test and debug features via the IEEE 1149.1 test
access port (TAP). The purpose of this internal Joint Test
Action Group (IJTAG) standard is to automate the way one
can manage on-chip instruments, and to describe a language
for communicating with them via the IEEE 1149.1 test data
registers (TDRs). If there is an IJTAG network available on the
SoC, and the total number of test configurations is relatively
small, one can use it to deliver the control data, as shown in
Fig. 2.
The SoC design of Fig. 2 has a single TAP and three
different blocks: 1) two cores (C1 and C2 ) under test and
2) the DSR interfacing ATE with C1 and C2 . TAP can be
instructed to enable a test path via the IEEE 1687 segment
insertion bits (SIBs). Every SIB is used to either enable or
disable the inclusion of an instrument into the path from a
test data In to a test data output. The TDR in C1 or C2 can
be either bypassed or loaded with data putting both cores into
specific test modes. The TDR in DSR receives the control
data indicating which core and which of its test channels are
connected to which ATE channels.
CHENG et al.: SCAN TEST BANDWIDTH MANAGEMENT FOR ULTRALARGE-SCALE SoC ARCHITECTURES
Fig. 2. Using IJTAG network to transfer control data.
Fig. 3. Dedicated control chain-based architecture.
The advantage of using the IJTAG network to deliver the
DSR control data is a simple and easy way to implement
flow as the network is frequently used to set the cores TDRs.
However, such an approach can only support a limited number
of configurations. This is because the IJTAG shift clock is
typically 10 to 20 times slower than the scan shift clock. Deliv-
ering a large volume of control data can incur an unacceptable
total test time overhead. Consequently, this architecture can
be used for a relatively small number of test configurations.
If the TDRs work with parallel update registers and many
patterns use the same configuration, a low throughput IJTAG
control can be mitigated. If one changes the control state
rather seldom, the next configuration vector can be shifted
in coincidently with application of test patterns, followed by
updating TDR when ready to switch to the new configuration.
It requires more DFT logic, though.
B. Dedicated Control Chain
The SoC design of Fig. 3 uses two dedicated control chains
(shown as red squares) to deliver the control data. In princi-
ple, these structures are obtained by daisy chaining address
registers of both DSRs. Let the design have n In test pins and
m output test pins at the chip-level. One can insert n control
chains driven by n In test pins through n demultiplexers. The
1053
selector pin of each demultiplexer is controlled by a signal
CFS. It is worth noting that if n ≥ m, then n control chains
suffice to supervise both In and output sides. If n < m, one
chain can be used to control one In channel and multiple output
channels for the number of control bits per channel is typically
much smaller than the pattern shift cycles.
When CFS is set to 0, a test pattern is only used to deliver
the control data for demultiplexers and multiplexers of the In
and output DSR, respectively. This particular pattern does not
have to be observed, and hence it only features an upload
phase. Typically, however, the number of shift cycles for
control patterns has to match the shift cycles of conventional
tests as many ATEs may not distinguish between control
patterns and regular test vectors. If CFS is equal to 1, patterns
are applied as regular test vectors. The DSR, which has already
been configured, connects then the respective ATE channels
with the core test channels as indicated by the content of the
address registers.
As can be seen in Fig. 3, CF is the pipelining flip-flop at the
beginning of one of the In channels. CFS is the shadow register
of CF, and it is updated at the end of each test pattern upload.
CF and CFS are initialized to 0, so the first test pattern must be
a control pattern. Once the control data is shifted in, flip-flop
CF becomes asserted, so does CFS. As a result, the regular
scan test patterns can be applied. Given a test configuration,
all patterns but the last one set CF and CFS to 1. The last
scan pattern of a test configuration sets CF back to 0 and
subsequently CFS is deasserted. In the next pattern, it uses the
deasserted CFS to upload the new control data into the control
chain and to setup a new test configuration. The remaining
configurations and test patterns are applied in a similar manner
by toggling the values of CF and CFS. The advantage of this
architecture is its ability to support as many test configurations
as desired since the control chain shift frequency is the same
as that of conventional scan chains.
C. Using Pipelines
One can also use the regular scan channels to deliver
controls through pipelining stages, as shown in Fig. 4. For
each channel, this approach concatenates n + m control bits,
where n and m are the numbers of control bits used by
the In demultiplexers and output multiplexers, respectively.
Moreover, each control bit is shadowed to avoid distorting
test configurations in the middle of test data shifting. The
shadow registers are updated at the end of each pattern
upload. Thus, when a test pattern launches a new test con-
figuration, the corresponding control data need to be loaded
with its predecessor. Clearly, the first vector is exclusively a
setup one.
The architecture of Fig. 4 supports as many test configura-
tions as required. However, the control data is always uploaded
through the ATE channels as an integral part of a test vector.
Hence, given a test configuration, the same control data is
repeated for all test patterns. The amount of control data
is small, though, as the number of control bits per channel
is typically a tiny fraction of the test pattern shift cycles.
1054 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 23, NO. 6, JUNE 2015
Fig. 4. Pipeline architecture.
IV. T EST T IME R EDUCTION
The tester bandwidth management in present large SoC
designs and future kilo-core architectures with considerable
diversity in the design styles and test needs of individual
modules requires solutions beyond the capabilities of state-
of-the-art DFT schemes. In particular, a test scheme will have
to dynamically adapt to particulars of a given SoC architecture
to assure an optimal utilization of its interface bandwidth.
In this section, we identify the key reasons for existing
solutions’ inability to further reduce test application time and
demonstrate how rearchitecting a test scheduler and DSR
networks can mitigate it. Finally, we show how these methods
reduce the test time in a global bandwidth management
scheme.
A. Conditional Merging
The test-scheduling algorithm of Section II attempts (in a
greedy fashion) to optimize the total test application time,
whereas the number of test configurations remains virtually
unlimited. Under certain circumstances, however, minimizing
the number of test configurations may decrease the actual test
time. Indeed, considering one would need to transfer control
data necessary to reconfigure DSRs many times, reducing
this activity may translate into some significant test time
savings. The additional test-scheduling step taking care of this
phenomenon will be further referred to as conditional merging,
and it can be detailed as follows.
Assume we know the total number of control bits needed
to reconfigure the In DSR(s). Let us also assume that we
know the frequency of a shift clock used when moving
the control data. As a result, one can easily assess time
Tc spent on updating test configurations. The resulting new
test scheduling comprises an additional verification step that
precedes a possible merging (or bin-packing) of a new setup
class with the existing base. It estimates the resultant impact
on test time, if we decide to proceed with merging. Clearly, if
the setup class is not merged with the base, it may reduce test
time as there is no need to send extra control data forming a
new test configuration. On the other hand, as part of tradeoff,
Fig. 5. Conditional merging cases. (a) No merging, Tc < t1 , t2 , t3 .
(b) Merging, Tc < t1 , t2 , t3 . (c) No merging, Tc > t1 , t2 , t3 . (d) Merging,
Tc > t1 , t2 , t3 .
one may observe performance degradation due to unutilized
(idle) ATE channels.
Consider a bin-packing diagram representing a part of a
hypothetical test schedule, as shown in Fig. 5(a). Here, two
cores, C1 (white boxes) and C2 (gray boxes), are to be tested.
Core C1 requires three channels to apply t1 test patterns
(it forms a setup class a), two channels to deliver t2 tests
(setup class b), and then a single channel for the remaining t3
patterns (class c). Core C2 needs two channels to deliver t3
test patterns (class d), and a single channel to apply t2 patterns
(setup class e). Let t1 , t2 , and t3 be much longer than the
duration Tc of test configuration setup. If classes b and e as
well as classes c and d are merged as shown in Fig. 5(b),
then extra time is needed to reconfigure the network three
times. More importantly, however, we reduce the actual test
time since C2 is tested in parallel with C1 . On the other hand,
if these classes are not merged, then two test configurations
suffice to complete tests of C1 and C2 . Unfortunately, test of
C2 is delayed, thus increasing visibly the total test application
time. As shown in Fig. 5(a), this scenario can be characterized
by some unused space (in the schedule diagram) whose area
A can be easily computed. Let k be the total number of SoC
In channels. Then, the total test time increase τ caused by
not merging some of the setup classes can be estimated as
τ = A/k. If τ < Tc , then one can reduce the total test time
by actually not merging some of the classes. Consequently, the
above condition can be used to dynamically decide whether
given setup classes should be merged when running test
CHENG et al.: SCAN TEST BANDWIDTH MANAGEMENT FOR ULTRALARGE-SCALE SoC ARCHITECTURES
Fig. 6. Test data volume for industrial design.
scheduling. This is illustrated in Fig. 5(c), where we assume
that t1 , t2 , and t3 are shorter than reconfiguration time Tc .
Without merging [Fig. 5(c)], test of C2 is going to be delayed.
Nevertheless, this approach is still recommended as setting up
an additional test configuration [Fig. 5(d)] will take longer
than testing C2 separately.
B. SoC In–Output Pin Partition
Optimizing SoC pin allocation based on scan data
volume (SDV) at the In and output sides can further improve
test scheduling. As typical SoC designs pack hundreds of
cores—interfaced by strictly limited channel resources—into
a space of a single chip, it is not unusual that the number
of channels assigned to a single core as well as the ratio of
EDT In to EDT outputs vary significantly. The same ratio
also depends on a test pattern as the solver always selects
the minimal number of In that suffice to encode a given
vector while still observing all outputs. This disproportion is
even more pronounced when several identical cores receive
the same data in the broadcast mode, whereas their outputs
must be observed independently to guarantee high quality of
fault detection and diagnosis. Consider, for example, a circuit
comprising eight identical cores with five In and outputs. Such
a design would require supplying different subsets of five In
channels while uninterruptedly monitoring all 40 outputs.
The above observations clearly indicate that the DSRs
should provide each core with channel resources adequate to
its bandwidth requirements. Although the total number of ATE
channels is typically fixed, most of SoC pins are bidirectional
and can be configured either as In or outputs. One can exploit
this flexibility; ultimately, it is the optimal proportion between
the In and outputs that will count in reducing test time or
improving bandwidth management.
According to our findings, the most suitable partitions of
ATE channels can be obtained by comparing the corresponding
SDVs on both sides. Consider a channel profile for a single
industrial core, as shown in Fig. 6. It gives, for every test
pattern, the number of In (black curve) and output (red line)
channels required to apply this test. Areas below both curves
1055
Fig. 7. Core-level test data volume statistics.
estimate SDV for the In and output side, as indicated in the
figure. SDV for the remaining cores of a given design can be
computed based on similarly shaped curves. By summing up
over all individual SDVs, one can arrive with the final ratio
of data volumes on the In and output sides. For example, the
ratio for one of examined industrial designs was equal to 0.44.
Subsequently, all SoC-level channels are assigned to the In and
output DSRs in accordance with the ratio determined earlier.
In the aforementioned test case, we would have two outputs
per one In, on the average. Occasionally, the desired ratio can
also be determined using the upper bound on the number of
In channels assigned to a given core, especially when channel
profiles similar to those of Fig. 6 are not readily available. The
same design would have then the ratio 0.51.
C. Priority-Based Routing
It is worth recalling that DSR networks are generic and
regular structures that remain independent of optimized SoC
pin partitions and SDV requirements of individual cores.
In particular, their OR gates (Fig. 1) help increase flexibility
of a test scheduler as proportionally more ATE channels can
be deployed to feed cores with larger fan-ins. However, the
number of EDT In channels and SDV do not correlate well.
For example, test PCs of two cores with the same number
of EDT channels may differ significantly. Consequently, the
number of EDT channels may not suffice to accurately guide
test resource partitioning. It applies primarily to those indus-
trial multicore designs whose crucial components (typically
cores running key functions) have aggressive data and test
time requests compared with the remaining modules of the
same chip.
Consider, for example, core-level SDV statistics for a single
SoC design with 141 heterogeneous cores, as shown in Fig. 7.
These numbers clearly follow the law of the vital few—the
major part of SDV is used to test only a few cores, whereas
the minority of tests is delivered to a wide spectrum of the
remaining blocks. It is, therefore, unreasonable to arrange
the same DSR connections—with many wires and inflated
control data—for both groups of cores. On the other hand, if
routing constraints permit, these additional wires can be used
to increase connectivity of the most demanding cores.
1056 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 23, NO. 6, JUNE 2015
Fig. 8. Core-level PC statistics.
The above analysis clearly indicates that adjusting DSR
networks in accordance with the SDV statistics can maintain
the central role of test scheduling in reducing test application
time. Thus, our approach groups cores with similar SDV
numbers in order to handle every group—through properly
adapted DSR networks—in an individual manner determined
by cores’ test data demands. As can be seen in Fig. 7,
141 cores are partitioned into three groups, each comprising
47 blocks. The accumulated SDVs (represented by the area
below the red curve) for groups A, B, and C are equal
to 73%, 25%, and 2% of the total data volume, respec-
tively. The core groups that emerge from this partitioning
get DSR wires proportionally to their SDV requests. As a
result, cores with larger SDVs will have access to more ATE
channels than cores with less demanding requests. Back to
Fig. 7—the group of cores that needs 73% of the total SDV
is likely to be served by a part of DSR networks that offer
the most comprehensive connectivity within the ATE interface.
For example, this approach may let every single core of group
A use one out of three ATE channels per In, while having
cores of groups B and C constrained to two and one ATE
channel, respectively.
The use of SDV figures in designing a DSR is remarkable
on its own, especially when all SoC cores have their ATPG
patterns ready. Still, the exact PC for each core may not always
be available at the DSR design stage. In this scenario, one can
run a compression analyzer [23] to estimate the total PC and
corresponding test data volume. A costly ATPG for a large
number of cores can deploy in this case a fault sampling
instead of working with a complete fault list. These actions
are feasible as the key parameter needed here is just an SDV
distribution among all cores rather than the accurate individual
PC for each of them.
D. Selective Elevation of Pin Counts at Core Level
A large number of patterns that are needed by a small
fraction of cores is another factor that may severely impact
the actual test time. Consider, for example, the core-level
PCs (Fig. 8) for the SoC design of Fig. 7. The total
SDV—here 3 269 098—and 151 available channels indicate
that the best schedule possible could reduce the test time
to 3 269 098/151 = 21 650 patterns. However, there are sev-
eral cores that require more than 21 650 patterns (including
module 1 coming with more than 35 000 tests). They form a
TABLE I
T OP PC C ORES
bottleneck, which prevents test scheduling from reaching solu-
tions close to a theoretical boundary. Fortunately, as resizing
of a decompressor does not impact SDV [14], increasing the
number of In channels can visibly and safely reduce individual
EDT-based PCs due to advanced dynamic compaction methods
that allow one to produce very compact test sets scaling almost
linearly with the number of In.
Clearly, the cost of ATPG recomputing can be high, espe-
cially for designs with hundreds of cores. Furthermore, it
may be impossible to increase EDT interface for every single
core. Therefore, choosing top cores with excessive PCs is the
solution. Here, the idea is to exclusively rebuild EDT interface
of these cores in such a way that the PC of the resultant test
set is below the lower bound determined by the optimal test
schedule. In particular, the number of decompressor In should
be increased as indicated by a ratio between the number of
patterns produced for a baseline configuration and number of
desired vectors. Table I presents stuck-at test pattern data for
the top seven cores of the SoC design analyzed earlier. Let
us assume that the number of channels feeding these cores
doubles. For each core, successive columns report the number
of EDT In, test coverage (TC), the PC for the baseline (left
part of the table) and resized (right part) EDT interfaces, and
finally the ratio between the resultant PCs. As can be seen,
all cores reduce their PCs approximately by half, whereas the
TC remains unaffected. As a result, the PCs for all cores are
now below the lower bound and testing can be completed in
an optimal time.
V. I NDUSTRIAL T EST C ASE
The schemes proposed in this paper were tested on a large
industrial SoC design comprising 281 isolated cores. This
number includes 121 unique cores plus 20 groups of identical
cores, each having eight modules (note that the number
of functionally different cores is thus 141—some statistics
regarding this design have already been used in Section IV).
When testing identical cores in one group, test stimuli are
broadcasted to the In of these eight identical cores while test
responses from all outputs of eight cores are observed together.
The core gate counts vary from a few million to more than
10M, whereas the core PCs ranges from a few thousands to
over 36k.
The trend of producing such complex designs adds another
constraint to the already complicated test scheduling process—
CHENG et al.: SCAN TEST BANDWIDTH MANAGEMENT FOR ULTRALARGE-SCALE SoC ARCHITECTURES 1057

TABLE II
S O C C HARACTERISTICS

Fig. 9. Pin layout constraints. (a) Baseline. (b) Partitioned.

certain cores can only use a subset of I/O pins because of

layout congestions. As shown in Fig. 9(a), all design pins and
cores can be then partitioned into a number (here four) of
disjoint subsets. A single core can only be interfaced through
a subset of pins hosted by the corresponding group. This
approach alleviates many practical problems, such as routing
complexity, aggressive timing parameters, signal integrity, or
power dissipation requirements. However, it impacts test logic
architecture and test scheduling algorithms. In particular, one
has to employ a number of routers [Fig. 9(b)] driven by subsets
of In test channels and feeding subsets of output test channels. TABLE III
Although the test scheduler is aware of these constraints, it S O C G ROUP S ETUP
may not produce as optimal test scenarios as those of single-
partition SoC designs due to their reduced flexibility (not
every channel can be connected freely to a desired core) and
unbalanced test requirements between successive groups. The
latter feature represents scenarios when, for example, the ratio
of In and output channels allocated to a given group does
not match the corresponding ratio of In and output test data
volumes, as discussed earlier, leading to underutilization of
some test resources within one group while compromising test
time within another partition.
Following the general scheme presented above, each core
or a group of identical cores in our design employ only a
subset of pins. There are 477 out of 497 SoC digital pins
that were used for testing. Similar to Fig. 9, the design was
partitioned into four quadrants Q 1 –Q 4 with the corresponding
allocation of cores and I/O pins into individual quadrants, as For example, the cores of Fig. 9(a) could be tested as follows:
listed in Table II. The same table provides some vital statistics 1) G 1 = {C1 , C5 , C9 , C13 }; 2) G 2 = {C2 , C6 , C10 , C14 };
of the design that include the gate count, number of scan cells, 3) G 3 = {C3 , C7 , C11 , C15 }; and 4) G 4 = {C4 , C8 , C12 , C16 }.
total number of EDT In (it would define the interface size if Once test scheduling arrives at the four test configurations,
no scheduling was used), total number of EDT outputs, and we use JTAG to setup each configuration. The results obtained
corresponding ratios of In to outputs: the actual one and the this way (Table III) form a baseline that can be compared
most preferable, obtained as shown in Section IV based on against our dynamic SoC bandwidth management outcomes.
the In test data volume and the output test data volume given The second row of Table III indicates the number of cores
in the table for both stuck-at and transition fault tests, with a that ended up within each configuration while the next row
further data breakdown with respect to successive quadrants. provides the number of scan shift cycles per pattern (pattern
All cores were manually partitioned into four groups length). The next three rows show, for each group, the number
G 1 –G 4 . One group corresponds to one configuration where of EDT In, the number of EDT outputs, and their sum,
all cores are tested in parallel, whereas different configurations respectively. Finally, the table reports the total number of
are tested in series. The core partitioning procedure picks one test patterns (determined by the largest PC of the largest
core from each quadrant and schedules these four cores to be core in a group) and the total number of shift cycles. The
tested in parallel within one configuration. If there are still SoC JTAG shift cycles deployed to setup each configuration are
pins available, it picks more cores from each quadrant until ignored because of only four configurations. The resultant
either there are no more SoC pins or all cores are selected. test schedule for patterns targeting stuck-at faults is illustrated
1058 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 23, NO. 6, JUNE 2015
TABLE IV
E XPERIMENTAL R ESULTS - I
Fig. 10. Baseline bin-packing diagram for stuck-at patterns.
in Fig. 10 as a bin-packing diagram for both the In (the
upper part) and output (the lower part) sides. Different colors
correspond to different cores or identical core groups. White
areas within eight boxes represent time slots when certain
channels (oriented horizontally) are unused. It is worth noting
that the baseline is a fully static channel assignment, as
connections between core test channels and SoC test pins
(within each configuration) are fixed.
VI. E XPERIMENTAL R ESULTS
The test architectures of Sections III and IV as well as
the SoC design of Section V were subsequently employed to
run our dynamic SoC bandwidth management. Given stuck-at
fault and transition fault test sets, the experimental results are
summarized in Table IV for eight test cases, out of which four
correspond to a fixed core-level channel count scenario where
a given core is always assigned SoC pins to all of its EDT
channels regardless of the actual test pattern requirements,
whereas the next four cases represent a scalable core-level
channel count scenario with the minimal number of SoC
pins allocated to a given core for a particular test pattern.
Furthermore, we consider four test setups, as described in
Section III: two of them use the IJTAG architecture with a shift
clock being 10 and 20 times slower than the scan shift clock,
whereas the remaining two solutions deploy dedicated control
chains and control bits attached to test patterns, respectively.
In all experiments, the total number of internal wires within
all (eight) DSRs, as shown in Fig. 1, was equal to 1795 (In)
and 4200 (outputs). Furthermore, the same DSRs deployed
exclusively In demultiplexers and output multiplexers driven
by 4-bit address registers. In other words, the amount of
control data per either In or output channel, whenever it needs
to be provided, is equal to 4 bit.
For each test case, successive columns of Table IV report
the following performance-related statistics of the proposed
schemes:
1) the total number of test patterns and the resultant number
of base classes;
2) the channel fill rate indicating the actual usage of the
ATE channels; it assumes the value of 1 only if all
channels are used uninterruptedly till the end of test;
CHENG et al.: SCAN TEST BANDWIDTH MANAGEMENT FOR ULTRALARGE-SCALE SoC ARCHITECTURES
TABLE V
E XPERIMENTAL R ESULTS - II
Fig. 11. Test time reduction.
3) the test application time reported as the total number of
shift cycles needed to deliver all test data in terms of the
actual test patterns and the accompanying control bits;
moreover the data to control ratio of both quantities is
also reported here;
4) the test time reduction ratio relative to the original shift
cycles given in Table III.
As indicated in Table IV, it appears that one can reduce up to
3.26 times the test application time compared with the baseline
and still be able to deliver all necessary test patterns, thus
preserving the original test quality. In particular, the largest test
application time reduction is observed for test scenarios based
on per pattern dynamic channel allocation while employing
dedicated chains to deliver all required control test data. These
results are even more evident for transition fault test sets.
Further experimental results, not presented in Table IV, reveal
an intrinsic relation between the ratio of In and output channels
and the resultant test time reduction. This is illustrated in
Fig. 11. As can be seen, the test time reduction clearly
depends on the aforementioned ratio, and hence its careful
selection, as shown in Section IV, may guarantee the shortest
test application time.
Additional results, reported in Table V, try to capture
the impact of a priority-based routing (as described in
Section IV-C) on test time reduction. The experiments were
run for stuck-at fault test sets by deploying scalable channel
counts and dedicated control scan chains. The proposed test
scheduling techniques have produced test scenarios for six
test cases. In the first three ones, all core In are connected
1059
Fig. 12. SoC complexity versus test time reduction.
by means of demultiplexers to the same number (given by
the Setup column) of different ATE channels. The next three
cases correspond to a priority-based configuration with the
connecting wires allocated individually per core In and for
every group of cores (as shown again by the Setup column,
which lists the number of wires used by each core In of
each group). For example, in the first case (3, 2, and 1),
there are three groups in total (A, B, and C), and each
core In in A, B, and C is connected with 3, 2, and 1 ATE
channels, respectively. For each test case, Table V reports
performance statistics similar to those of Table IV. As can be
seen, the test time can be significantly reduced if appropriate
interconnection networks are used. For example, compare the
last test cases reported for both scenarios. It appears that the
test application time for the priority-based configuration is
reduced up to 3.41 times, i.e., it outperforms the corresponding
solution for the baseline configuration by 12% with the number
of connecting wires reduced from 2760 to 2382.
An interesting tradeoff between the SoC complexity and
test time reduction is presented in Fig. 12. Each group of
bars corresponds to a given number of control bits used per a
single ATE output, whereas each color indicates the number
of control bits per an ATE In. As can be seen, one can reduce
the test time by increasing the amount of either In or output
control bits. However, the most prominent time savings occur
when both factors go up in parallel. For example, with two
control bits per output and a single control bit per In, one
can reduce test duration 1.57 times. The same two output bits
1060 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 23, NO. 6, JUNE 2015
Fig. 13. Optimized test schedule.
paired with three control bits per In yield about a 2.55x test
time reduction. Interestingly, adding more control bits on the
In side has virtually no performance impact. Eventually, the
best test time reduction is observed when five control bits per
every In and output ATE channel are used.
Fig. 13 pictures the complete and optimized test schedule
for In and output sides obtained by allocating test channels in
a dynamic manner for 145 In and 332 output test channels.
As can be seen, there is a well-pronounced difference between
the test schedules of Figs. 10 and 13—note that the time axis
of Fig. 10 has been largely squeezed compared with the same
axis of Fig. 13.
VII. C ONCLUSION
As Moore’s law continues to provide smaller devices,
designs with a range of core counts, capability per core, and
energy per core make a dramatic impact on SoC design and
test procedures. As shown in this paper, the I/O resources
provided by a tester can be dynamically allocated to selected
cores, whereas the total number of channels in use may remain
unchanged. This paradigm clearly calls for efficient schemes
minimizing the overall test application time, while taking into
account physical constraints, in particular, SoC pin allocations.
Assuming that all SoC cores are wrapped testable
units, this paper studies several practical issues regarding
SoC-based testing that deploys on-chip test data compres-
sion with the ability to dynamically use ATE channels. The
proposed solutions include methods used to deliver control
data and test scheduling algorithms minimizing the overall
test application time. Experimental results obtained for a large
industrial SoC design confirm feasibility of the proposed
schemes and their ability to trade-off the number of test pins,
design complexity of the TAM, and test application time.
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Wu-Tung Cheng (S’84–M’85–SM’90–F’00)
received the B.S. and M.S. degrees in electrical
engineering from National Taiwan University,
Taipei, Taiwan, in 1978 and 1982, respectively,
and the Ph.D. degree in computer science from
the University of Illinois at Urbana-Champaign,
Champaign, IL, USA, in 1985.
He was with AT&T Bell Laboratories, Princeton,
NJ, USA, from 1985 to 1990, where he was
developing a test pattern generation system for
digital circuits. From 1990 to 1993, he was the
Co-Founder of CheckLogic System, Inc., Dayton, OH, USA, and the
Vice President of Engineering, where he was leading a team to develop
commercial automatic test-generation products, which included FastScan,
FlexTest, and DFTAdvisor. In 1993, CheckLogic was merged with Mentor
Graphics Corporation, Wilsonville, OR, USA, where he has held various
technical and management positions in design for test area since 1993. He is
currently a Chief Scientist and the Director of Advanced Test Research,
involved in research on new design-for-test solutions for future semiconductor
quality and yield issues. He has authored over 130 research papers in these
areas, and is the co-inventor of 40 patents.
Yan Dong received the B.S. and M.S. degrees
in electrical engineering from Zhejiang University,
Hangzhou, China, in 1984 and 1987, respectively.
He has started his career as an ASIC Design Engi-
neer. His current research interests include network
computing processors, embedded CPUs, and graphic
chip designs. He has been involved in DFX features
design, including scan, memory BIST, and built-in
functional tests since joining ATI, Markham, ON,
Canada, in 2004, which became a part of Advanced
Micro Devices, Sunnyvale, CA, USA, in 2006. He is
currently a Senior Design Manager leading DFX IP design, flow, and
methodology development for GPU and APU.
1061
Grady Gilles (M’90) received the B.S. degree
in physics from Texas A&M University, College
Station, TX, USA, in 1978.
He has been privileged to practice design for
testability (DFT) on some of the most commercially
successful microprocessors, first with Motorola,
Schaumburg, IL, USA, and is currently with
Advanced Micro Devices, Sunnyvale, CA, USA,
where he has been since 1999. He holds numerous
patents and publications related to DFT. His current
research interests include di/dt mitigation techniques
and multiple orthogonal strategies to better utilize tester bandwidth.
Mr. Gilles was a co-recipient of the 1991 and 2008 Best Paper Awards at
the IEEE International Test Conference. He helped to develop two test-related
IEEE Standards, 1149.1 and 1500.
Yu Huang (M’99–SM’12) received the B.S. degree
in electronic science and the M.S. degree in
semiconductor devices and technology from Nankai
University, Tianjin, China and the Ph.D. degree in
electrical and computer engineering from the Uni-
versity of Iowa, Iowa City, IA, USA.
He is a Senior Research and Development
Staff Member with the Division of Silicon Test
Systems, Mentor Graphics Corporation, Wilsonville,
OR, USA. He has authored more than 100 research
papers, and holds seven U.S. patents and 16 patents
pending. His current research interests include VLSI testing, test compression,
and fault diagnosis.
Jakub Janicki received the M.S. and Ph.D. degrees
in telecommunications from Poznań University of
Technology, Poznań, Poland, in 2009 and 2014,
respectively.
He is currently with Mentor Graphics Polska,
Poznań. He has authored several technical papers
in the IEEE journals and conferences. He is a
co-inventor of two U.S. patent applications. His
current research interests include the design for
testability, testing of system-on-chip designs, low-
power embedded test, and test compression.
Mark Kassab (M’91–SM’14) received the M.S.
and Ph.D. degrees in electrical engineering from
McGill University, Montreal, QC, Canada, in 1994
and 1996, respectively.
He joined the Design-for-Test Group at Mentor
Graphics Corporation, Wilsonville, OR, USA, in
1996, where he is currently the Engineering Direc-
tor. He is a co-inventor of the EDT compression
technology, the Lead Developer and Architect of
TestKompress, and a Co-Designer of the Tessent
platform. He has authored several papers, and is a
co-inventor of 37 patents. His current research interests include the design for
testability, improving test quality, test cost reduction, design automation, and
design of high-performance CAD tools.
Dr. Kassab was a co-recipient of the Best Paper Award at the VLSI Test
Symposium in 1995 and the Honorable Mention Award at the International
Test Conference in 1999. Two of the papers he published were included by
ITC 2004 among the most significant papers published in the 35 years of
ITC. He was also a co-recipient of the IEEE Circuits and Systems Society
Donald O. Pederson Outstanding Paper Award recognizing the paper on
embedded deterministic test in the IEEE T RANSACTIONS ON C OMPUTER -
A IDED D ESIGN OF I NTEGRATED C IRCUITS AND S YSTEMS in 2006. He was
also a recipient of the 2012 Most Significant Paper Award at the International
Test Conference.
1062 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 23, NO. 6, JUNE 2015
Grzegorz Mrugalski (M’06–SM’13) received the
M.S. and Ph.D. degrees in electrical engineering
from Poznań University of Technology, Poznań,
Poland, in 1995 and 2002, respectively.
He joined Mentor Graphics Corporation,
Wilsonville, OR, USA, in 2002. Previously,
he was with the Institute of Electronics and
Telecommunications, Poznań University of
Technology. Since 2009, he has been the Manager
of the Research and Development Laboratory
for Design-for-Test products at Mentor Graphics
Polska, Poznań, Poland. He has co-authored over 40 technical papers in the
area of test, and holds 21 U.S. patents. His current research interests include
computer-aided design of digital circuits, design for testability, built-in
self-test, and test compression.
Dr. Mrugalski was a co-recipient of the 2011 Best Paper Award at the
IEEE European Test Symposium and the 2012 IEEE International Test
Conference Most Significant Paper Award.
Nilanjan Mukherjee (S’87–M’89–SM’14) received
the B.Tech. (Hons.) degree in electronics and electri-
cal communication engineering from IIT Kharagpur,
Kharagpur, India, in 1989 and the Ph.D. degree
from McGill University, Montreal, QC, Canada, in
1996.
He is currently the Software Development Director
of the Design-to-Silicon Division at Mentor Graph-
ics Corporation, Wilsonville, OR, USA. Prior to
joining Mentor Graphics Corporation, he was with
Lucent Bell, Holmdel, NJ, USA. He is a co-inventor
of the EDT technology, and was a Lead Developer for the leading test
compression tool in the industry, TestKompress. He has authored more than 45
technical articles, and is a co-inventor of 39 U.S. patents. His current research
interests include next-generation test methodologies for deep submicrometer
designs, test data compression, test synthesis, memory testing, and fault
diagnosis.
Dr. Mukherjee was a co-recipient of the Best Paper Award at the 1995
IEEE VLSI Test Symposium, the Best Paper Award at the 2009 VLSI Design
Conference, the Best Student Paper Award at the 2001 Asian Test Symposium,
the 2006 IEEE Circuits and Systems Society Donald O. Pederson Outstanding
Paper Award recognizing the paper on embedded deterministic test in the
IEEE T RANSACTIONS ON C OMPUTER -A IDED D ESIGN OF I NTEGRATED
C IRCUITS AND S YSTEMS , and the 2012 IEEE International Test Conference
Most Significant Paper Award. He served on the program committees of
several IEEE conferences.
Janusz Rajski (A’87–SM’10–F’11) received the
M.S. and Ph.D. degrees in electrical engineering
from the Technical University of Gdańsk, Gdańsk,
Poland, and Poznań University of Technology,
Poznań, Poland, in 1973 and 1982, respectively.
He was a Faculty Member of the Poznań Uni-
versity of Technology from 1973 to 1984. In 1984,
he joined McGill University, Montreal, QC, Canada,
where he became an Associate Professor in 1989. In
1995, he was a Chief Scientist at Mentor Graphics
Corporation, Wilsonville, OR, USA. He has authored
more than 150 research papers in these areas, and is a co-inventor of 84 U.S.
patents. He is also the Principal Inventor of the Embedded Deterministic
Test Technology used in the first commercial test compression product,
TestKompress. His current research interests include the testing of VLSI
systems, design for testability, built-in self-test, and logic synthesis.
Dr. Rajski was the Guest Co-Editor of the special issue of the IEEE C OM -
MUNICATIONS M AGAZINE devoted to testing of telecommunication hardware
in 1999. He was also the Associate Editor of the IEEE T RANSACTIONS ON
C OMPUTER -A IDED D ESIGN OF I NTEGRATED C IRCUITS AND S YSTEMS , the
IEEE T RANSACTIONS ON C OMPUTERS , and the IEEE D ESIGN AND T EST
OF C OMPUTERS M AGAZINE. He has served on technical program committees
of various conferences. He was a co-recipient of the 1993 Best Paper Award
for the paper on logic synthesis published in the IEEE T RANSACTIONS ON
C OMPUTER -A IDED D ESIGN OF I NTEGRATED C IRCUITS AND S YSTEMS , the
1995 and 1998 Best Paper Awards at the IEEE VLSI Test Symposium, the
1999 and 2003 Honorable Mention Awards at the IEEE International Test
Conference, the 2006 IEEE Circuits and Systems Society Donald O. Pederson
Outstanding Paper Award recognizing the paper on embedded deterministic
test published in the IEEE T RANSACTIONS ON C OMPUTER -A IDED D ESIGN
OF I NTEGRATED C IRCUITS AND S YSTEMS , the 2009 Best Paper Award at the
VLSI Design Conference, the 2011 Best Paper Award at the IEEE European
Test Symposium, and the 2012 IEEE International Test Conference Most
Significant Paper Award.
Jerzy Tyszer (M’91–SM’96–F’13) received the
M.S. and Ph.D. degrees in electrical engineering
from Poznań University of Technology, Poznań,
Poland, in 1981 and 1987, respectively, and the
Dr. Hab. degree in telecommunications from the
Technical University of Gdańsk, Gdańsk, Poland, in
1994.
He was a Faculty Member of the Poznań Uni-
versity of Technology from 1982 to 1990. In 1990,
he joined McGill University, Montreal, QC, Canada,
where he was a Research Associate and an Adjunct
Professor. In 1996, he was a Professor with the Faculty of Electronics and
Telecommunications, Poznań University of Technology. He has authored eight
books, more than 120 research papers in the above areas, and is a co-
inventor of 55 U.S. patents. His current research interests include the design
automation and testing of very large-scale integration (VLSI) systems, design
for testability, built-in self-test, embedded test, and computer simulation of
discrete event systems.
Dr. Tyszer was the Guest Co-Editor of the special issue of the IEEE
C OMMUNICATIONS M AGAZINE devoted to testing of telecommunication
hardware in 1999. He has served on technical program committees of various
conferences. He was a co-recipient of the 1995 and 1998 Best Paper Awards
at the IEEE VLSI Test Symposium, the 2003 Honorable Mention Award at
the IEEE International Test Conference, the 2006 IEEE Circuits and Systems
Society Donald O. Pederson Outstanding Paper Award recognizing the paper
on embedded deterministic test published in the IEEE T RANSACTIONS ON
C OMPUTER -A IDED D ESIGN OF I NTEGRATED C IRCUITS AND S YSTEMS , the
2009 Best Paper Award at the VLSI Design Conference, the 2011 Best
Paper Award at the IEEE European Test Symposium, and the 2012 IEEE
International Test Conference Most Significant Paper Award.