01-Verilog Introduction-Merged

Fundamental of
Verilog HDL
Overview of Digital Design Using Verilog
• Evolution of Computer-Aided Digital Design

• Emergence of HDLs
• Typical Design Flow
• Importance of HDLs
• Popularity of Verilog HDL
• Trends in HDLs
Ravikant Suryawanshi
Evolution of Computer-Aided Digital Design
• SSI: Small scale integration

– A few gates on a chip
• MSI: Medium scale integration

– Hundreds of gates on a chip
• LSI: Large scale integration

– Thousands of gates on a chip
– CAD: Computer-Aided Design
– Logic and circuit simulators
– Prototyping on bread board
– Layout by hand (on paper or a computer terminal)
• VLSI: Very Large Scale Integration
– Hundred thousands of gates
– Not feasible anymore:
• Bread boarding and Manual layout design
– Simulator programs
– Automatic place-and-route
– Bottom-Up design
– More and more emphasis on logic simulation
Emergence of HDLs
• Need to a standardized language for hardware description
– Verilog and VHDL
• Simulators emerged
– Usage: functional verification
– Path to implementation: manual translation into gates
• Logic synthesis technology

– Dramatic change in digital design
• Design at Register-Transfer Level (RTL) using an HDL

History of Verilog HDL
– Market divided between Verilog & VHDL
• VHDL mostly in Europe
• Verilog dominant in US
– VHDL
• More general language
• Not all constructs are synthesizable
– Verilog:
• Not as general as VHDL
• Most constructs are synthesizable
Typical Design
Flow
Typical Design Flow
• Most design activity
– In 1996:
• Manually optimizing the RTL design
• CAD tools take care of generating lower-level details
• Reducing design time to months from years
– Today
• Still RTL is used in many cases
• But, synthesis from behavioral-level also possible
• Digital design now resembles high-level computer
programming
Typical Design Flow
• NOTE:
– CAD tools help, but the designer still has the
main role
• GIGO (Garbage-In Garbage-Out) concept
• To obtain an optimized design, the designer needs

to know about the synthesis technology
– Compare to software programming and compilation
Importance of HDLs
• Retargeting to a new fabrication technology
• Functional verification earlier in the design cycle
• Textual concise representation of the design

– Similar to computer programs
– Easier to understand
Popularity of Verilog HDL
• Verilog HDL
– General-purpose
– Easy to learn, easy to use
– Similar in syntax to C
– Allows different levels of abstraction and mixing them
– Supported by most popular logic synthesis tools
– Post-logic-synthesis simulation libraries by all
fabrication vendors Ravikant Suryawanshi
Trends in HDLs
• Design at behavioral level
• Formal verification techniques
• Very high speed and time critical circuits

– e.g. microprocessors
– Mixed gate-level and RTL designs
• Hardware-Software Co-design
– System-level languages: SystemC, SpecC, …
Verilog HDL
Hierarchical Modeling Concepts

Design Methodologies
• Top-Down Design Methodology
• Bottom Up Design Methodology
Top- Down Design Methodologies
• Define the top level block and identify the sub-
blocks necessary to build the top-level block.
• Further sub-divide the sub-blocks until come
to leaf cells, which are the cells that can not

further be divided.
Advantages of top-down design
• Increase Productivity
• Reduce Non-Recurring (NRE) cost
• Design Reuse
• Increase flexibility to design changes
• Faster exploration to alternative architecture
• Testability
• Better and easier verification

Bottom Up Design Methodologies
• Identify the building blocks that are available to
us.
• Build bigger cells, using these building blocks.
• These cells are then used for higher-level blocks
until we build the top-level block in the design.
4-bit Ripple Carry Counter
T-flipflop and the Hierarchy
Lexical Conventions
Lexical Conventions
Data Types
Data Types
Data Types
Data Types
Components of Verilog Module
Modules
module <module_name>(<module_terminal_list>);
...
<module internals>
...
endmodule
• Example:
module T_ff(q, clock, reset);

...
<functionality of T_flipflop>
...
endmodule
Modules
• Verilog supported levels of abstraction
– Behavioral (algorithmic) level
• Describe the algorithm used
• Very similar to C programming
– Dataflow level
• Describe how data flows between registers and is
processed
– Gate level
• Interconnect logic gates
– Switch level
• Interconnect transistors (MOS transistors)
• Register-Transfer Level (RTL)
– Generally known as a combination of behavioral+dataflow that
is synthesizable by EDARavikant
toolsSuryawanshi
Instances
Instances
module ripple_carry_counter(q, clk, reset);
output [3:0] q;
input clk, reset;
//4 instances of the module TFF are created.

TFF tff0(q[0],clk, reset);
TFF tff1(q[1],q[0], reset);
endmodule
module TFF(q, clk, reset);
output q;
input clk, reset;
Instances
wire d;
DFF dff0(q, d, clk, reset);

not n1(d, q); // not is a Verilog provided primitive.
endmodule
// module DFF with asynchronous reset

module DFF(q, d, clk, reset);
output q;
input d, clk, reset;
reg q;
always @(posedge reset or negedge clk)

if (reset)
q = 1'b0;
else
q = d;
endmodule Ravikant Suryawanshi

• Illegal instantiation example:
– Nested module definition not allowed
Instances
– Note the difference between module definition and module
instantiation
// Define the top level module called ripple carry

// counter. It is illegal to define the module T_FF
//inside this module.
module ripple_carry_counter(q, clk, reset);

output [3:0] q;
input clk, reset;
module T_FF(q, clock, reset);// ILLEGAL MODULE NESTING

:
<module T_FF internals>
:
endmodule // END OF ILLEGAL MODULE NESTING
endmodule Ravikant Suryawanshi

Components of Simulation
• Functionality can be tested by applying

stimulus and checking results
• Stimulus block
• Keep stimulus block and design block separate
• Can be done using Verilog
• Two styles of stimulus operation
• First
• Two styles of stimulus operation
• Second
Example
• Design block was shown before
– ripple_carry_counter, T_FF, and D_FF modules
• Stimulus block
module stimulus;
reg clk; reg reset; wire[3:0] q;
// instantiate the design block

ripple_carry_counter r1(q, clk, reset);
// Control the clk signal that drives the design block.

initial clk = 1'b0;
always #5 clk = ~clk;
// Control the reset signal that drives the design block

initial
begin
reset = 1'b1;
#15 reset = 1'b0;
#180 reset = 1'b1;
#10 reset = 1'b0;
#20 $stop;
end
initial // Monitor the outputs

$monitor($time, " Output q = %d", q);
endmodule
Output
Digital System Design
Verilog HDL
Basic Concepts
Content
 Lexical Conventions
 Data Types
 System Tasks and Compiler Directives
Lexical Conventions
• Very similar to C
– Verilog is case-sensitive
– All keywords are in lowercase
– A Verilog program is a string of tokens
• Whitespace
• Comments
• Delimiters
• Numbers
• Strings
• Identifiers
• Keywords
Lexical Conventions
• Whitespace • Comments
– Blank space (\b) – Used for readability and
– Tab (\t) documentation
– Newline (\n) – Just like C:
• // single line comment
• Whitespace is ignored
• /* multi-line
in Verilog except comment
– In strings */
– When separating tokens /* Nested comments
/* like this */ may not
be acceptable (depends
on Verilog compiler) */
Lexical Conventions
• Operators
– Unary
a = ~b;
– Binary
a = b && c;
– Ternary
a = b ? c : d; // the only ternary
operator
Lexical Conventions
• Number Specification
– Sized numbers
– Unsized numbers
– Unknown and high-impedance values
– Negative numbers
Lexical Conventions
• Sized numbers
• Unsized numbers
– General syntax:
<size>’<base><number> – Default base is decimal
• <size> number of bits (in – Default size is at least 32
decimal) (depends on Verilog compiler)
• <number> is the number in – Examples
radix <base> • 23232
• <base>: • ’habc
– d or D for decimal (radix 10) • ’o234
– b or B for binary (radix 2)
– o or O for octal (radix 8)
– h or H for hexadecimal (radix
16)
• Examples:
– 4’b1111
– 12’habc
– 16’d255
Lexical Conventions
• X or Z values
– Unknown value: lowercase x
• 4 bits in hex, 3 bits in octal, 1 bit in binary
– High-impedance value: lowercase z
• 4 bits in hex, 3 bits in octal, 1 bit in binary
– Examples
• 12’h13x
• 6’hx
• 32’bz
– Extending the most-significant part
• Applied when <size> is bigger than the specified value
– Filled with x if the specified MSB is x
– Filled with z if the specified MSB is z
– Zero-extended otherwise
• Examples:
– 6’hx
Lexical Conventions
• Negative numbers
– Put the sign before the <size>
– Examples:
• -6’d3
• 4’d-2 // illegal
– Two’s complement is used to store the value
• Underscore character and question marks

– Use ‘_’ to improve readability
• 12’b1111_0000_1010
• Not allowed as the first character
– ‘?’ is the same as ‘z’ (only regarding numbers)
• 4’b10?? // the same as 4’b10zz
Lexical Conventions
• Strings
– As in C, use double-quotes
– Examples:
• “Hello world!”
• “a / b”
• “text\tcolumn1\bcolumn2\n”
Lexical Conventions
• Identifiers and keywords
– identifiers: alphanumeric characters, ‘_’, and ‘$’
• Should start with an alphabetic character or ‘_’
• Only system tasks can start with ‘$’
– Keywords: identifiers reserved by Verilog
– Examples:
• reg value;
• input clk;
Lexical Conventions
• Escaped identifiers
– Start with ‘\’
– End with whitespace (space, tab, newline)
– Can have any printable character between start and end
– The ‘\’ and whitespace are not part of the identifier
– Examples:
• \a+b-c // a+b-c is the identifier
• \**my_name** // **my_name** is the identifier
– Used as name of modules

Basic Concepts
Data Types
Data Types
• Value set and strengths
• Nets and Registers
• Vectors
• Integer, Real, and Time Register Data Types
• Arrays
• Memories
• Parameters
• Strings
Value Set
• Verilog concepts to model hardware circuits
– Value level
– Value strength
• Used to accurately model

– Signal contention
– MOS devices
– Dynamic MOS
– Other low-level details

Value Set
Value level HW Condition Strength level Type
0 Logic zero, false supply Driving
1 Logic one, true strong Driving

pull Driving
x Unknown
large Storage
z High imp., floating
weak Driving
medium Storage
small Storage
highz High
Impedance
Nets
• Used to represent connections between HW elements
– Values continuously driven on nets
– Fig. 3-1
• Keyword: wire
– Default: One-bit values
• unless declared as vectors
– Default value: z
• For trireg, default is x
– Examples
• wire a;
• wire b, c;
• wire d=1’b0; Ravikant Suryawanshi
Registers
• Registers represent data storage elements
– Retain value until next assignment
– NOTE: this is not a hardware register or flipflop
– Keyword: reg
– Default value: x reg reset;

initial
– Example:
begin
reset = 1’b1;
#100 reset=1’b0;
end
Vectors
• Net and register data types can be declared as vectors
(multiple bit widths)
• Syntax:
– wire/reg [msb_index : lsb_index] data_id;
• Example
wire a;
wire [7:0] bus;
wire [31:0] busA, busB, busC;
reg clock;
reg [0:40] virtual_addr;
Vectors
• Consider
wire [7:0] bus;
wire [31:0] busA, busB, busC;
reg [0:40] virtual_addr;
• Access to bits or parts of a vector is possible:
busA[7]
bus[2:0] // three least-significant bits of bus
// bus[0:2] is illegal.
virtual_addr[0:1] /* two most-significant bits
* of virtual_addr
*/
Integer, Real, and Time Register Data Types
• Integer
– Keyword: integer
– Very similar to a vector of reg
• integer variables are signed numbers
• reg vectors are unsigned numbers
– Bit width: implementation-dependent (at least 32-bits)
• Designer can also specify a width: integer [7:0] tmp;
– Examples: integer counter;
initial
counter = -1;
Example:
• Real real delta;
– Keyword: real initial
begin
– Values:
delta=4e10;
• Default value: 0
delta=2.13;
• Decimal notation: 12.24
end
• Scientific notation: 3e6 (=3x106) integer i;
– Cannot have range declaration initial

i = delta;
// i gets the value 2
//(rounded value of 2.13)
• Time
– Used to store values of simulation time
– Keyword: time
– Bit width: implementation-dependent (at least 64)
– $time system function gives current simulation time
– Example: time save_sim_time;

initial
save_sim_time
= $time;
• Only one-dimensional arrays supported
Arrays
• Allowed for reg, integer, time
– Not allowed for real data type
• Syntax:
<data_type> <var_name>[start_idx : end_idx];
• Examples:
integer count[0:7];
reg bool[31:0];
time chk_point[1:100];
reg [4:0] port_id[0:7];
integer matrix[4:0][4:0]; // illegal
count[5]
chk_point[100]
port_id[3]
• Note the difference between vectors and arrays

Memories
• RAM, ROM, and register-files used many times in
digital systems
• Memory = array of registers in Verilog
• Word = an element of the array
– Can be one or more bits
• Examples:
reg membit[0:1023];
reg [7:0] membyte[0:1023];
membyte[511]
• Note the difference (as in arrays):
reg membit[0:127];
reg [0:127] register;
Parameters
• Similar to const in C
– But can be overridden for each module at compile-time
• Syntax:
parameter <const_id>=<value>;
• Gives flexibility
– Allows to customize the module
• Example:
parameter port_id=5;
parameter cache_line_width=256;
parameter bus_width=8;
wire [bus_width-1:0] bus;

Strings
• Strings are stored in reg variables.
• 8-bits required per character
• The string is stored from the least-significant part to the most-
significant part of the reg variable
• Example:
reg [8*18:1] string_value;
initial
string_value = “Hello World!”;
• Escaped characters
– \n: newline \t: tab
– %%: % \\: \
– \”: “ \ooo: character number in octal
Basic Concepts
System Tasks and

Compiler Directives
System Tasks
• System Tasks: standard routine operations

provided by Verilog
– Displaying on screen, monitoring values, stopping
and finishing simulation, etc.
• All start with $
System Tasks (cont’d)
• $display: displays values of variables, strings,
expressions.
– Syntax: $display(p1, p2, p3, …, pn);
– p1,…, pn can be quoted string, variable, or

expression
– Adds a new-line after displaying pn by default
– Format specifiers:
• %d, %b, %h, %o: display variable respectively
in decimal, binary, hex, octal
• %c, %s: display character, string
• %e, %f, %g: display real variable in scientific,

decimal, or whichever smaller notation
• %v: display strength
• %t: display in current time format
• %m: display hierarchical name of this module

System Tasks :$display examples:
– $display(“Hello Verilog World!”);
Output: Hello Verilog World!
– $display($time);
Output: 230
– reg [0:40] virtual_addr;
– $display(“At time %d virtual address

is %h”, $time, virtual_addr);
Output: At time 200 virtual address is
1fe000001c Ravikant Suryawanshi
System Tasks :$display examples:
• reg [4:0] port_id;
• $display(“ID of the port is %b”, port_id);
Output: ID of the port is 00101
• reg [3:0] bus;

• $display(“Bus value is %b”, bus);
Output: Bus value is 10xx
• $display(“Hierarchical name of this module

is %m”);
Output: Hierarchical name of this module is top.p1
• $display(“A \n multiline string with a %%

sign.”);
Output: A
multiline string with a % sign.
System Tasks
• $monitor: monitors a signal when its value
changes
• Syntax: $monitor(p1, p2, p3, …, pn);

– p1,…, pn can be quoted string, variable, or signal names
– Format specifiers just as $display
– Continuously monitors the values of the specified variables or

signals, and displays the entire list whenever any of them
changes.
System Tasks
$monitor needs to be invoked only once (unlike
$display)
Only one $monitor (the latest one) can be active

at any time
$monitoroff to temporarily turn off monitoring
$monitoron to turn monitoring on again
System Tasks
• $monitor Examples:
initial
begin
$monitor($time, “Value of signals
clock=%b, reset=%b”, clock, reset);
end
– Output:
0 value of signals clock=0, reset=1
System Tasks
• $stop: stops simulation
– Simulation enters interactive mode when reaching a
$stop system task
– Most useful for debugging
• $finish: terminates simulation
• Examples:
initial
begin
clock=0;
reset=1;
#100 $stop;
#900 $finish;
end
Compiler Directives
• General syntax:
`<keyword>
• `define: similar to #define in C, used to define macros

• `<macro_name> to use the macro defined by `define
• Examples:
`define WORD_SIZE 32
`define S $stop
`define WORD_REG reg [31:0]

`WORD_REG reg32;
Compiler Directives
• `include: Similar to #include in C, includes
entire contents of another file in your Verilog source
file
• Example:
`include header.v
...
<Verilog code in file design.v>
... Ravikant Suryawanshi

What we learned today
• Basic concepts in Verilog
– Verilog is very similar to C
• Various data types available in Verilog
– Verilog uses 4-valued logic: 0, 1, x, z
• System tasks are Verilog statements used to request
something from simulator
• Compiler directives instruct the compiler to do
something for us at compile-time
Other Notes
• Course web-page
– http://ce.sharif.edu/courses/84-85/1/ce223/
• Exercise 2
– Chapter 3 exercises
– Due date: Next Sunday (Aban 8th)

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Fundamental of

• Evolution of Computer-Aided Digital Design

• SSI: Small scale integration

• MSI: Medium scale integration

• LSI: Large scale integration

– CAD: Computer-Aided Design

– Logic and circuit simulators

– Prototyping on bread board

– Layout by hand (on paper or a computer terminal)

– Not feasible anymore:

• Bread boarding and Manual layout design

– More and more emphasis on logic simulation

– Path to implementation: manual translation into gates

• Logic synthesis technology

• Design at Register-Transfer Level (RTL) using an HDL

• To obtain an optimized design, the designer needs

• Retargeting to a new fabrication technology

• Functional verification earlier in the design cycle

• Textual concise representation of the design

• Formal verification techniques

• Very high speed and time critical circuits

– Mixed gate-level and RTL designs

Hierarchical Modeling Concepts

• Top-Down Design Methodology

• Bottom Up Design Methodology

blocks necessary to build the top-level block.

• Further sub-divide the sub-blocks until come

to leaf cells, which are the cells that can not

• Reduce Non-Recurring (NRE) cost

• Increase flexibility to design changes

• Faster exploration to alternative architecture

• Better and easier verification

• Identify the building blocks that are available to

• Build bigger cells, using these building blocks.

• These cells are then used for higher-level blocks

until we build the top-level block in the design.

module T_ff(q, clock, reset);

//4 instances of the module TFF are created.

DFF dff0(q, d, clk, reset);

// module DFF with asynchronous reset

always @(posedge reset or negedge clk)

endmodule Ravikant Suryawanshi

// Define the top level module called ripple carry

module ripple_carry_counter(q, clk, reset);

module T_FF(q, clock, reset);// ILLEGAL MODULE NESTING

endmodule Ravikant Suryawanshi

• Functionality can be tested by applying

• Keep stimulus block and design block separate

• Can be done using Verilog

// instantiate the design block

// Control the clk signal that drives the design block.

// Control the reset signal that drives the design block

initial // Monitor the outputs

 System Tasks and Compiler Directives

– Unknown and high-impedance values

• Underscore character and question marks

• Only system tasks can start with ‘$’

– Keywords: identifiers reserved by Verilog

– End with whitespace (space, tab, newline)

– Can have any printable character between start and end

– The ‘\’ and whitespace are not part of the identifier

• \a+b-c // a+b-c is the identifier

• \my_name // my_name is the identifier