Chapter6-1 Part I 12-10-2003

Chapter 6 (I)
Designing
Combinational
Logic Circuits
•Static CMOS
•Pass Transistor Logic
V1.0 4/25/03, V2.0 5/4/03
V3.0 5/15/03, V4.0 12/10/03
1
EE141
Combinational Circuits
Revision Chronicle
5/2: Add some NAND8 figures (to compare NAND8
circuits) from old Weste textbook to this slide.
5/4:
Add 4 Pass-Transistor Logic Slides from Weste
textbook
Split Chapter 6 into two parts: Part I focuses on
Static and Pass Transistor Logic. Part II focuses
on Dynamic Logic
5/15: Add the Transmission Gate slides (x5)
from Steve Kang’s textbook
12/10: Major modifications on Logic Efforts
2
EE141
Combinational vs. Sequential Logic
In Out
Combinational Combinational
In Logic Out Logic
Circuit Circuit
State
Combinational Sequential
Output = f(In) Output = f(In, Previous In)
3
EE141
Static CMOS Circuits
•At every point in time (except during the switching
transients) each gate output is connected to either
VDD or Vss via a low-resistive path (PUN, PDN)
•The outputs of the gates assume at all times the

value of the Boolean function, implemented by the
circuit (ignoring the transient effects during
switching periods).
•This is in contrast to the dynamic CMOS circuit

class, which relies on temporary storage of signal
values on the capacitance of high impedance circuit
nodes.
4
EE141
Static Complementary CMOS
VDD
In1
PMOS only
In2 PUN
… (good for transfer 1)
InN
F(In1,In2,…InN)
In1
In2 PDN
…
NMOS only
InN
(good for transfer 0)
Pull-up Network (PUN) and Pull-down Network (PDN)

are Dual Logic Networks
5
EE141
Threshold Drops in NMOS and PMOS
-- Check Candidates for PUN and PDN
VDD VDD
PUN
S D
G VDD G
D 0 → VDD S 0 → VDD - VTn

VGS
CL CL
PDN VDD → 0 VDD → |VTp|

VGS
D CL S CL
VDD
G G
S D
6
EE141
Complementary CMOS Logic Style
7
EE141
NMOS Transistors
in Series/Parallel Connection
Transistors can be thought as a switch controlled by its gate signal
NMOS switch closes when switch control input is high
A B
X Y Y = X if A and B
X B Y = X if A OR B
Y
NMOS Transistors pass a “strong” 0 but a “weak” 1

8
EE141
PMOS Transistors
in Series/Parallel Connection
PMOS switch closes when switch control input is low
A B
X Y Y = X if A AND B = A + B
X B Y = X if A OR B = AB
Y
PMOS Transistors pass a “strong” 1 but a “weak” 0

9
EE141
Example 1: NAND2 Gate
(DeMorgan’s Law)
PDN : G = A ⋅ B ⇒ Connect to GND
PUN : F = A ⋅ B = A + B ⇒ Connnet to VDD
G ( In1, In2, In3, …) ≡ F ( In1, In2, In3, …)
10
EE141
Example2: NOR2 Gate
VDD
PDN : G = A + B ⇒ Connect to GND

PUN : F = A + B = A ⋅ B ⇒ Connnet to VDD
G ( In1, In2, In3, …) ≡ F ( In1, In2, In3, …)
(DeMorgan’s Law)
11
EE141
Design of Complex CMOS Gate
VDD
B
A
C
D
F = D + A ⋅ (B + C)
A
D
B C
12
EE141
Constructing a Complex Gate
VDD VDD
C
F SN4 A SN2
F SN1
SN2 B
A A
D D SN3
B C B C D SN1
F
(a) pull-down network (b) Deriving the pull-up network A

hierarchically by identifying
D
sub-nets
B C
SN2
SN1
(c) complete gate
13
EE141
Static CMOS Properties
Full rail-to-rail swing: High noise margins
Logic levels not dependent upon the relative device
sizes: Ratioless
Always a path to Vdd or GND in steady state: Low
output impedance
Extremely high input resistance; nearly zero steady-
state input current (input to CMOS gate)
No steady-state direct path between power and ground:
No static power dissipation
Propagation delay function of output load capacitance
and resistance of transistors
14
EE141
Static Properties of CMOS Gates
VGS 2 = VA − VDS1
VGS 2 = VA − VDS1 Vt of M2 > Vt of M1 VTn 2 = VTn 0 + γ ( 2φ f +V int − 2φ f )
VGS1 = VB (Body Effect)
VTn1 = VTn 0
15
EE141
Switch Delay Model
A Req
A
NAND2
16
EE141
Switch Delay Model
A Req
A
Rp
Rp Rp
B
A B Rp
A Rp Cint
Rn CL A
B Rn CL
A Rn Rn CL
Rn
Cint
A B
A
INV NOR2
NAND2 17
EE141
Input Pattern Effects on Delay
Delay is dependent on the pattern
of input (Assume Rp = 2 Rn for
same size of transistors)
Rp Rp
Low-to-high transition:
A B
Both inputs go low
Rn
– Delay is 0.69 (Rp/2) CL
CL
One input goes low
B
– Delay is 0.69 (Rp) CL
Rn High-to-low transition:
Cint
A Both inputs go high (required
for NAND)
– Delay is 0.69 (2Rn)CL
18
EE141
Transistor Sizing for Symmetric Rise/Fall Time
Assumes Rp = 2Rn at same W/L
RP RP RP
Rp Rp RP = RN Rp + = = RN
2 4 4 2
2 A B 2 4 B
Rn Rp Cint
CL 4
2 A
A
Rn Rn Rn CL
2 Cint
1
B A B 1
NAND is preferred than NOR implementation!!

19
EE141
Delay Dependence on Input Patterns
NAND2 is true
OUT connects to GND
3
Input Data Delay
2.5 A=B=1→0
Pattern (psec)
2 A=B=0→1 69
A=1→0, B=1 A=1, B=0→1 62
Voltage [V]
1.5
1 A= 0→1, B=1 50
A=1, B=1→0
0.5 A=B=1→0 35
0 A=1, B=1→0 76
0 100 200 300 400 A= 1→0, B=1 57
-0.5
time [ps]
A=1, B=1→0 (for both Cint and CL) NMOS = 0.5µm/0.25 µm
PMOS = 0.75µm/0.25 µm
A=1, B=0→1 (Consider Body effect) CL = 100 fF 20
EE141
Transistor Sizing a Complex
CMOS Gate
B 8
RP RP RP RN
A 4 + = =
8 8 4 2
C 8
D 4 RP / 4 = RN / 2
OUT = D + A • (B + C)
A 2 RN / 2
D 1
B 2C 2 RN / 2 (wide, only one for critical case)
21
EE141
Fan-In Considerations
4-input
NAND Gate
22
EE141
The Elmore Delay (1st-order approximation)
R44 = R1 + R3 + R4
= R1C1 + R1C2 + ( R1 + R3 )C3 + ( R1 + R3 )C4 + ( R1 + R3 + Ri )Ci
(Elmore delay for node i) 23

EE141
Fan-In Considerations
Distributed RC model
A B C D (Elmore delay)
R4 A CL tpHL = 0.69(R1C1+(R1+R2)C2
R3 B C3 + (R1+R2+R3)C3
R2 C + (R1+R2+R3+R4)CL
C2
R1 D C1
=0.69 Reqn(C1+2C2+3C3+4CL)
= O(N^2)
Source 5VÆ 0V
Propagation (HÆ L) delay deteriorates rapidly as a

function of fan-in number (N): Quadratically in the
worst case. 24
EE141
tp as a Function of Fan-In
1250
Quadratic
1000 (H->L)
750
tp (psec)
tpHL tp
500
250 tpLH (L Æ H)
0
Linear Increase in
2 4 6 8 10 12 14 16 Intrinsic Capacitance,
fan-in
Assume Only one
PMOS is ON for critical
case
25
EE141
(tpHL, tpLH) as a Function of Fan-Out
Gates with a fan-in greater than or equal to 4 becomes

excessively slow and should be avoided!
26
EE141
tp as a Function of Fan-In and Fan-Out
Fan-in: quadratic due to increasing
resistance and capacitance
Fan-out: each additional fan-out gate
adds two gate capacitances to CL To the
preceding stage)
27
EE141
Fast Complex Gates: Design Technique 1
Transistor sizing
Increase Intrinsic parasitic cap and create CL of the
preceding stage
Progressive sizing
Distributed RC line:
InN MN CL
•M1 > M2 > M3 > … > MN
(the FET closest to the
In3 M3 C3 output is the smallest)
In2 M2 C2 •Not simple in Layout!

In1 M1 C1
28
EE141
29
EE141
Input reordering: Put late arrival signal near the
output node.
critical path critical path
charged 0→1 charged

In3 1 M3 CL
In1 M3 CL
In2 1 M2 In2 1 M2 C2 discharged

C2 charged
In1 In3 1 M1 C1 discharged
M1 C1 charged
0→1
Delay determined by time to Delay determined by time to

discharge CL, C1 and C2 discharge CL
30
EE141
Logic Restructuring (A)
F =NAND8 Gate
(C) (B)
In general, C > B > A in speed 31
EE141
Design Technique 3: Logic Restructuring
Tradeoff between Area and Speed
(and Power?), CL = 100 fF
(from Neil Weste, 2nd Ed, 93) 32

EE141
Fast Complex Gates: Layout Technique
(A): 4 internal cap

2 output diff cap
(B): 4 internal cap
4 output diff cap
(A) Is better than (B)
(A) (B) 33
EE141
Optimizing Performance in Combinational
Networks
Out
In
1 2 N CL
CIN
N
 fi 
Delay = t p 0 ∑ 1 +  (in units of tp0)
i =1  γ 
For given N: Ci +1 / Ci = Ci / Ci −1
To find N: Ci +1 / Ci ≈ 4 Æ Effective Fanout (Cap. Stage Ratio)
How to generalize this to any combinational logic path? E.g.,

How do we size the ALU datapath to achieve maximum speed?
34
EE141
Logical Effort
Inverter has the smallest logical effort and
intrinsic delay of all static CMOS gates
Logical effort of a gate presents the ratio of its
input capacitance to the inverter capacitance
when sized to deliver the same current
( tHL = tLH)
Logical effort increases with the gate
complexity
35
EE141
Review of Delay Model
Delay = t p = 0.69 Req (Cint + Cext ) ( Eq. 5.27)
= 0.69 Req Cint (1 + Cext / Cint ) = t p 0 (1 + Cext / Cint )
t p 0 : Intrinsic Delay or Unloaded Delay (with Cext = 0 )
Req : Equivalent resistance of the gate
Sizing factor of S relative to a minimum-sized Inverter

t p = 0.69( Rref / S )( SCiref )(1 + Cext /( SCiref ))
Cext Cext
= 0.69 Rref Ciref (1 + ) = t p 0 (1 + ) ( Eq.5.28)
SCiref SCiref
36
EE141
Review of Delay Model (cont’d)
Cint = γC g , Cext = fC g
C g : Input gate capacitance

γ : Proportional factor that is only a function of
technology, and is close to 1
f : Effective fan-out (ratio of input cap and output cap)
Cext fC g f
t p = t p 0 (1 + ) = t p 0 (1 + ) = t p 0 (1 + ) ( Eq.5.30)
SCiref γC g γ
Delay of an Inverter in only a function of the ratio between

Its external load cap. And its input capacitance
( γ is constant)
37
EE141
Logical Effort
Logical effort is the ratio of input capacitance of a gate to the input
capacitance of an inverter with the same output current µ n = 2 µ p
VDD VDD VDD
A 2 A 2 B 2 B 4
F
F
A 4
A 2
A 1 F
A 1 B 1
B 2
Inverter 2-input NAND 2-input NOR
g=1 g = 4/3 g = 5/3

38
EE141
Logical Effort
From Sutherland, Sproull

39
EE141
Example – 8-input AND
40
EE141
Estimated Intrinsic Delay Factor
41
EE141
Logical Effort for Complex Gate
Cext C  g⋅ f 
t p = t p 0 (1 + ) = t p 0 (1 + ext ) = t p 0  p + 
Cint γC g  γ 
= t p 0 ( p + g ⋅ f ) (Assume γ = 1)
• p – Ratio of the Intrinsic delay between the complex

gate and the simple inverter.
• g - Logical effort : How much more input
capacitance a gate represents to deliver the same
output current as an inverter.
• f - Effective fan-out): Ratio between the external
load and input capacitance of the gate. It is also
called Electrical Effort
• Normalize everything to an inverter: ginv =1, pinv = 1

42
EE141
Delay in a Logic Gates
Gate Effort:
h=gf
Logical Effective fanout = Cout/Cin
Effort
Gate delay:
d=h+p
Effort delay Intrinsic delay
•Logical effort is a function of topology, independent of sizing

•Effective fanout (electrical effort) is a function of load/gate
size
43
EE141
Logical Effort of Gates (I)
2
=
p
3;
4/
5 1
=
p=
:g
Normalized Delay
1;
ND
4 =
g
NA ter:
er
t
pu
3 v
In
in
Effort
2-
Delay
2
1
Intrinsic
Delay
1 2 3 4 5
Fanout f
44
EE141
Logical Effort of Gates (II)
t pNAND
Normalized delay (d) g = 4/3 t pINV
p=2
d = (4/3)f+2
g=1
p=1
d = f+1
F(Fan-in)
1 2 3 4 5 6 7
Fan-out (f)
45
EE141
Add Branching Effort
Branching effort (assume the same complex gate):
Con − path + Coff − path

b=
Con − path
On-path
Off-path
46
EE141
Multi-stage Logic Networks
N
 gi ⋅ fi  N
Delay = t p = t p 0 ∑  pi +  = t p 0 ∑ ( pi + g i ⋅ f i )
i =1  γ  i =1
(assume γ = 1)
•Stage Effort: hi = gifi ( g1 ⋅ f1 = g 2 ⋅ f 2 = = gN ⋅ fN )
•Path Electrical Effort (path effective fanout) F = CL/Cg,1

•Path Logical Effort: G = g1g2…gN N
fi N ∏f i
•Branching Effort: B = b1b2…bN Î F =∏ = i =1

( Eq.6.13)
i =1 bi B
•Path effort (total): H = GFB
N N N
•Path delay (total) D = ∑ d i = t p 0 ∑ ( pi + bi ⋅ g i ⋅ f i ) = t p 0 ∑ ( pi + hi )

i =1 i =1 i =1
47
EE141
Optimum Effort per Stage for a Fixed N Stages
When each stage bears the same effort:

hN = H
h=N H
Stage efforts: g1f1 = g2f2 = … = gNfN
Effective fanout of each stage: f i = h g i
Minimum path delay

N N N
Dˆ = ∑ (bi g i f i + pi ) = ∑ bi g i f i + ∑ pi = N ( H 1/ N ) + P
i =1 i =1 i =1
48
EE141
Optimal Number of Stages
For a given loading capacitance and and given input
capacitance of the first gate
Î Find optimal number of stages and optimal sizing
D = N ( H 1/ N ) + P ≈ NH 1/ N + Npinv
∂D
∂N
[ ( )]
= H 1/ N 1 − ln H 1/ N + pinv = 0
Substitute ‘best stage effort’ hˆ = H 1/ N

ˆ
hˆ(1 − ln(hˆ)) + pinv = 0 ( pinv : intrinsic delay of unit inverter)
hˆ ≈ 0.71 pinv + 2.82 ≈ 4

49
EE141
Sizing of Each Stage
F=Cout/Cin
Cin s1 s3 s4
s2
Cout
Cin = C g1 = s1 × g1 × Cref
b1 × s2 × g 2 × Cref f1 s2 × g 2 × Cref
f1 = ⇒ =
s1 × g1 × Cref b1 s1 × g1 × Cref
s1 × g1 i −1 f j
si = ( )∏ ( ) Î Sizing for each stage
gi j =1 b j
50
EE141
Example 6.6: Optimize Path (I)
F=Cout/Cin
Cin s1 s3 s4
s2
Cout F= 5
g1 = 1 g2 = 5/3 g3 = 5/3 g4 = 1
5 5 25
Effective fanout, F = 5, G = 1× × × 1 =
3 3 9
H = GF=125/9 = 13.9, B =1
h = 1.93 (optimal stage effort) = 4 H
hˆ = fˆ ⋅ gˆ = 1.93 ⇒
f1 = 1.93 / g1 = 1.93, f 2 = 1.93 / g 2 = 1.16,
f 3 = 1.93 / g 3 = 1.16, f 4 = 1.93 / g 4 = 1.93.
51
EE141
Example 6.6: Optimize Path (II)
F = 5 = Cout/Cin
Cin s1 s3 s4
s2
Cout
g1 = 1 g2 = 5/3 g3 = 5/3 g4 = 1
f 1= 1.93 f2 = 1.16 f3 = 1.16 f4 = 1.93
S1 =1 S2 =? S3=? S4 = ?
b1s2 g 2 f1s1 g1 1.93 ×1×1

f1 = 1.93 = ⇒ s2 = = = 1.15
s1 g1 b1 g 2 1× (5 / 3)
b2 s3 g 3 f 2 s2 g 2 1.16 × 1.15 × (5 / 3)
f 2 = 1.16 = ⇒ s3 = = = 1.33
s2 g 2 b2 g 3 1× (5 / 3)
b3 s4 g 4 f 3 s3 g 3 1.16 × 1.33 × (5 / 3)
f 3 = 1.16 = ⇒ s4 = = = 2.57
s3 g 3 b3 g 4 1× 1
52
EE141
Method of Logical Effort
Compute the total path effort: H = GFB

Find the best number of stages N ~ log4 H
Compute the stage effort h = H1/N
Sketch the path with this number of stages
Work either from either end, find sizes of
each complex gates
Reference: Sutherland, Sproull, Harris, “Logical Effort, Morgan-Kaufmann 1999.
53
EE141
Summary of Logic Effort
“Logic Effort,” by
Sutherland,
Sproull
Harris, 1999
54
EE141
Pass-Transistor
Logic
55
EE141
Pass-Transistor Logic
Vdd
B
Switch Out A
Out
Inputs
Network B
B
Vss
•N Transistors
•Considered as Static CMOS circuits: output
changes only when inputs change
56
EE141
Pass Transistor Logic Basics
Logic Function:
F = ∑ PiVi
i
= P1 (V1 ) + P2 (V2 ) + + Pn (Vn )
Pi = Control Signals
V i = Pass Signals ∈ {0 ,1 , X i , − X i , Z }
Z : High Impedance
B
Example: AND Gate
A
B
A, B: A is Input signal, B F = AB + 0B = AB
is the Control Signal
0
57
EE141
Example: Design of XNOR2
(a) Truth table
(b) Pass-network
Karnaugh map
A as the control signals

(c) Logic function B as the passed signals
F = − A ⋅ (− B) + A ⋅ ( B)
58
EE141
Example: Implementation of XNOR2
(a) Transmission Gate (Better)

(b) NMOS (Suffer from Vt degradation)
(c) Cross-couple Out = A B + AB + BA (combined
effect)
59
EE141
Example2: Construct Boolean Functions
•Truth Table:
•Implement:
60
EE141
Disadvantage of NMOS-Only Logic
3.0
In
In
1.5µ m/0.25 µm Out
2.0
Voltage [V]
VD D x x
Out
0.5 µ m/0.25µ m
0.5µ m/0.25 µm 1.0
0.0
0 0.5 1 1.5 2
Time [ns]
Suffer from
•Vt degradation (Vx = Vdd- Vt(x))
•Body effect (Vsb ≠ 0 , Vx has value and threshold voltage
Vt(x) is bigger than Vt(0))
61
EE141
NMOS-only Switch
C = 2.5V C = 2.5 V
M2
A = 2.5 V A = 2.5 V B
Mn
B
CL M1
• V(B) does not pull up to 2.5V, but 2.5V – Vt,n(B)

• NMOS (Mn) has higher threshold than PMOS (M2) (body
effect) Æ PMOS will be partially turned ON!
• Threshold voltage loss causes Static Power
Consumption!!
62
EE141
Level Restoring Transistor
VDD
Level Restorer VDD
Mr
B
M2
X
A Mn Out
M1
•Advantage: Full Swing (Vdd, GND)

•Restorer speed up Fall time (Feedback)
•Disadvantage:
• Mr Adds capacitance at Node X (slow down)
• Compete with Mn transistor for pull down
operation 63
EE141
Restorer Sizing
3.0
•Ratio problem among (Mr
and Mn)
2.0
W/Lr =1.75/0.25
Voltage [V]
W/L r =1.50/0.25
•Can be analyzed using
open circuit Æ Like an
1.0
Inverter circuit composed of
W/Lr =1.0/0.25 W/L r =1.25/0.25 Mr and Mn
0.0
0 100 200 300 400 500
Time [ps] •Adding upper limit on the
size of Restorer Transistor
(Mr)
64
EE141
Solution 2: Complementary/Differential
Pass Transistor Logic (CPL/DPL)
65
EE141
DCVSL (p.267)
VDD VDD
1 -> 0 M1 M2 0 -> 1
Out Out
A
A PDN1 PDN2
B
B
VSS VSS
Differential Cascode Voltage Switch Logic (DCVSL)
66
EE141
NAND4 Gate Using CPL
67
EE141
Swing-restored Pass-transistor Logic
Out = A ⊕ B ⊕ C ( XOR), Out = A ⊕ B ⊕ C ( XNOR)

68
EE141
Solution 3:
Single Transistor Pass Gate with VT=0
VDD
VDD • Still suffer from Body

0V 2.5V Effect of Pass
transistors
VDD 0V Out • Sneak dc-current
path
2.5V • Significant when in
idle state
WATCH OUT FOR SUBTHRESHOLD LEAKAGE CURRENTS!!

69
EE141
Solution 4: Use of Transmission Gate
C
C
A B A B
C
C
C = 2.5 V
A = 2.5 V
B
CL
C=0V
70
EE141
Analysis of TG (Transmission Gate)
G VDS ,n = VDD − Vout
NMOS:
VGS ,n = VDD − Vout
S D
(Initial =0V) PMOS: VDS , p = Vout − VDD
D S
VGS , p = −VDD
G
I D = I DS ,n + I SD , p
VDD − Vout
Req ,n =
I DS ,n
VDD − Vout
Req , p =
I SD , p
Req ,TG = Req ,n || Req , p
71
EE141
Analysis of TG (I)
72
EE141
Analysis of TG (II)
73
EE141
Resistance of Transmission Gate
74
EE141
Application1: Inverting 2-to-1 Multiplexer
VDD
S
A
M2 S S
VDD
S F
M1
B F
GND
F = ( S ⋅ A + S ⋅ B) A S S B
75
EE141
Application2: 6-T(ransistor) XOR Gate
Truth Table F = A⊕ B
B
B A F
0 0 A 0 M2
B
0 1 A 1 A
A
1 0 A 1 F
M1 M3/M4
1 1 A 0 B
B
B=0: Pass A Signal
6T includes
B=1: Inverting A Signal
the inverter of B
76
EE141
Application3: Transmission Gate Full Adder
(to be discussed in Chapter 11)
P = A⊕ B P
VDD
P = A⊕ B
VDD Ci
A S = P ⊕ Ci = A ⊕ B ⊕ Ci
P S Sum Generation
A A P Ci
A P VDD
B B
VDD A
P
P Co Carry Generation
Ci Ci Ci COut = P ⋅ Ci + P ⋅ A
A
Setup P
Similar delays for Sum and Carry

77
EE141
Delay in Transmission Gate Networks
2.5 2.5 2.5 2.5
V1 Vi-1 Vi Vi+1 Vn-1 Vn
In
C C C C C
0 0 0 0
(a)
Req Req Req Req

V1 Vi Vi+1 Vn-1 Vn
In
C C C C C
(b)
m
Req Req Req Req Req Req

In
C CC C C CC C
(c)
78
EE141
Delay of Transmission gate Network
79
EE141
Delay Optimization
Buffer can be
(a) Inverter pairs

(b) One inverter +
Final correcting
inverter
80
EE141
Summary
Fan-in and Fan-out of gates play an important
role in CMOS circuit speed.
Concept of Logic Efforts can generalize the
invert chain design to complex gate chain
design.
Pass Transistor Logic leads low-power, low-
footprint designs, but it should be used with
special care.
81
EE141

Chapter6-1 Part I 12-10-2003

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Chapter6-1 Part I 12-10-2003

Uploaded by

Copyright:

Available Formats

Chapter 6 (I)

Output = f(In) Output = f(In, Previous In)

•The outputs of the gates assume at all times the

•This is in contrast to the dynamic CMOS circuit

Pull-up Network (PUN) and Pull-down Network (PDN)

D 0 → VDD S 0 → VDD - VTn

PDN VDD → 0 VDD → |VTp|

NMOS Transistors pass a “strong” 0 but a “weak” 1

PMOS Transistors pass a “strong” 1 but a “weak” 0

PDN : G = A + B ⇒ Connect to GND

(a) pull-down network (b) Deriving the pull-up network A

NAND is preferred than NOR implementation!!

= R1C1 + R1C2 + ( R1 + R3 )C3 + ( R1 + R3 )C4 + ( R1 + R3 + Ri )Ci

(Elmore delay for node i) 23

Propagation (HÆ L) delay deteriorates rapidly as a

Gates with a fan-in greater than or equal to 4 becomes

In2 M2 C2 •Not simple in Layout!

critical path critical path

charged 0→1 charged

In2 1 M2 In2 1 M2 C2 discharged

Delay determined by time to Delay determined by time to

(from Neil Weste, 2nd Ed, 93) 32

(A): 4 internal cap

(A) Is better than (B)

How to generalize this to any combinational logic path? E.g.,

Sizing factor of S relative to a minimum-sized Inverter

C g : Input gate capacitance

Delay of an Inverter in only a function of the ratio between

Inverter 2-input NAND 2-input NOR

g=1 g = 4/3 g = 5/3

From Sutherland, Sproull

• p – Ratio of the Intrinsic delay between the complex

• Normalize everything to an inverter: ginv =1, pinv = 1

•Logical effort is a function of topology, independent of sizing

Branching effort (assume the same complex gate):

Con − path + Coff − path

•Stage Effort: hi = gifi ( g1 ⋅ f1 = g 2 ⋅ f 2 = = gN ⋅ fN )

•Path Electrical Effort (path effective fanout) F = CL/Cg,1

•Branching Effort: B = b1b2…bN Î F =∏ = i =1

•Path delay (total) D = ∑ d i = t p 0 ∑ ( pi + bi ⋅ g i ⋅ f i ) = t p 0 ∑ ( pi + hi )

When each stage bears the same effort:

Effective fanout of each stage: f i = h g i

Minimum path delay

Substitute ‘best stage effort’ hˆ = H 1/ N

hˆ(1 − ln(hˆ)) + pinv = 0 ( pinv : intrinsic delay of unit inverter)

hˆ ≈ 0.71 pinv + 2.82 ≈ 4

b1s2 g 2 f1s1 g1 1.93 ×1×1

 Compute the total path effort: H = GFB

Reference: Sutherland, Sproull, Harris, “Logical Effort, Morgan-Kaufmann 1999.

= P1 (V1 ) + P2 (V2 ) + + Pn (Vn )

(a) Truth table

A as the control signals

(a) Transmission Gate (Better)

• V(B) does not pull up to 2.5V, but 2.5V – Vt,n(B)

•Advantage: Full Swing (Vdd, GND)

Differential Cascode Voltage Switch Logic (DCVSL)

Out = A ⊕ B ⊕ C ( XOR), Out = A ⊕ B ⊕ C ( XNOR)

VDD • Still suffer from Body

WATCH OUT FOR SUBTHRESHOLD LEAKAGE CURRENTS!!

Similar delays for Sum and Carry

Req Req Req Req

Req Req Req Req Req Req

Compute the total path effort: H = GFB