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AA18
AA18
AA18
of Pages: 01
Total No. of Questions: 08
INSTRUCTIONS TO CANDIDATES:
1. Attempt any FIVE questions out of EIGHT questions.
2. Each question carries TWENTY marks.
o m
b) Explain the concept of control dependence with an example. With what problem a
pipeline may suffer if a control dependence is there? [10]
.r c
2. a) Explain detecting and enhancing loop level parallelism for VLIW processor?
m
[10]
p e
b) Explain the taxonomy of parallel architectures.
o
[10]
.r c
3. Explain in detail the symmetric shared memory architectures with reference to
p a
multiprocessor cache coherence problem. [20]
b r
4. Explain different classes of pipeline hazards with examples.
[20]
a
6. Discuss about various code scheduling approaches for ILP by taking suitable examples. [20]
rp
7. Explain in detail the distributed shared memory architecture highlighting the directory based
b
cache coherence protocol. Substantiate your explanation with suitable examples and state
diagrams? [20]
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